summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--firmware/export/s5l8700.h36
-rw-r--r--firmware/target/arm/s5l8700/system-s5l8700.c29
-rw-r--r--firmware/target/arm/s5l8700/uart-s5l8700.c129
-rw-r--r--firmware/target/arm/s5l8700/uart-s5l8701.c160
-rw-r--r--firmware/target/arm/s5l8700/uart-target.h38
5 files changed, 380 insertions, 12 deletions
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h
index 420212ff3b..e8497ff337 100644
--- a/firmware/export/s5l8700.h
+++ b/firmware/export/s5l8700.h
@@ -118,6 +118,13 @@
#define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */
#define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */
#define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */
+#if CONFIG_CPU==S5L8701
+#define CLOCKGATE_UARTC0 8
+#define CLOCKGATE_UARTC1 9
+#define CLOCKGATE_UARTC2 13
+#else /* S5L8700 */
+#define CLOCKGATE_UARTC 8
+#endif
#define PWRMODE (*(REG32_PTR_T)(0x3C50002C)) /* Power mode control register */
#define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */
#define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */
@@ -136,11 +143,16 @@
#define INTMSK_TIMERD (1<<5)
#define INTMSK_ECC (1<<19)
#define INTMSK_USB_OTG (1<<16)
+#define INTMSK_UART0 (0) /* Unknown */
+#define INTMSK_UART1 (1<<12)
+#define INTMSK_UART2 (1<<7)
#else
#define INTMSK_TIMERA (1<<5)
#define INTMSK_TIMERB (1<<7)
#define INTMSK_TIMERC (1<<8)
#define INTMSK_TIMERD (1<<9)
+#define INTMSK_UART0 (1<<22)
+#define INTMSK_UART1 (1<<14)
#endif
#define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */
#define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */
@@ -577,6 +589,29 @@
#define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */
/* 25. UART */
+#if CONFIG_CPU==S5L8701
+/* s5l8701 UC870X HW: 3 UARTC, 1 port per UARTC */
+#define S5L8701_N_UARTC 3
+#define S5L8701_N_PORTS 3
+
+#define UARTC0_BASE_ADDR 0x3CC00000
+#define UARTC0_N_PORTS 1
+#define UARTC0_PORT_OFFSET 0x0
+#define UARTC1_BASE_ADDR 0x3CC08000
+#define UARTC1_N_PORTS 1
+#define UARTC1_PORT_OFFSET 0x0
+#define UARTC2_BASE_ADDR 0x3CC0C000
+#define UARTC2_N_PORTS 1
+#define UARTC2_PORT_OFFSET 0x0
+
+#else
+/* s5l8700 UC870X HW: 1 UARTC, 2 ports */
+#define S5L8700_N_UARTC 1
+#define S5L8700_N_PORTS 2
+
+#define UARTC_BASE_ADDR 0x3CC00000
+#define UARTC_N_PORTS 2
+#define UARTC_PORT_OFFSET 0x8000
/* UART 0 */
#define ULCON0 (*(REG32_PTR_T)(0x3CC00000)) /* Line Control Register */
@@ -603,6 +638,7 @@
#define UTXH1 (*(REG32_PTR_T)(0x3CC08020)) /* Transmit Buffer Register */
#define URXH1 (*(REG32_PTR_T)(0x3CC08024)) /* Receive Buffer Register */
#define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */
+#endif
/* 26. LCD INTERFACE CONTROLLER */
#if CONFIG_CPU==S5L8700
diff --git a/firmware/target/arm/s5l8700/system-s5l8700.c b/firmware/target/arm/s5l8700/system-s5l8700.c
index 601955fbac..728fea0432 100644
--- a/firmware/target/arm/s5l8700/system-s5l8700.c
+++ b/firmware/target/arm/s5l8700/system-s5l8700.c
@@ -27,6 +27,7 @@
#include "storage.h"
#include "pmu-target.h"
#endif
+#include "uart-target.h"
/* MIUSDPARA_BOOST taken from OF (see crt0.S). MIUSDPARA_UNBOOST is derived
* from MIUSDPARA_BOOST due to the fact that the minimum allowed DRAM timings
@@ -63,7 +64,7 @@ default_interrupt(INT_DMA);
default_interrupt(INT_ALARM_RTC);
default_interrupt(INT_PRI_RTC);
default_interrupt(RESERVED1);
-default_interrupt(INT_UART);
+default_interrupt(INT_UART1);
default_interrupt(INT_USB_HOST);
default_interrupt(INT_USB_FUNC);
default_interrupt(INT_LCDC_0);
@@ -81,9 +82,10 @@ default_interrupt(RESERVED2);
default_interrupt(INT_MSTICK);
default_interrupt(INT_ADC_WAKEUP);
default_interrupt(INT_ADC);
-default_interrupt(INT_UNK1);
-default_interrupt(INT_UNK2);
-default_interrupt(INT_UNK3);
+#if CONFIG_CPU==S5L8701
+default_interrupt(INT_UNK);
+default_interrupt(INT_UART2);
+#endif
void INT_TIMER(void)
@@ -98,16 +100,16 @@ void INT_TIMER(void)
#if CONFIG_CPU==S5L8701
static void (* const irqvector[])(void) =
{ /* still 90% unverified and probably incorrect */
- EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMER,INT_WDT,INT_UNK1,
- INT_UNK2,INT_UNK3,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
- INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,INT_ECC,
+ EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMER,INT_WDT,INT_UART2,
+ INT_UNK,INT_UNK,INT_DMA,INT_ALARM_RTC,INT_UART1,INT_UNK,INT_UNK,INT_USB_HOST,
+ INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_CALM,INT_ATA,INT_UNK,INT_SPDIF_OUT,INT_ECC,
INT_SDCI,INT_LCD,INT_WHEEL,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
};
#else
static void (* const irqvector[])(void) =
{
EXT0,EXT1,EXT2,EINT_VBUS,EINTG,INT_TIMERA,INT_WDT,INT_TIMERB,
- INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART,INT_USB_HOST,
+ INT_TIMERC,INT_TIMERD,INT_DMA,INT_ALARM_RTC,INT_PRI_RTC,RESERVED1,INT_UART1,INT_USB_HOST,
INT_USB_FUNC,INT_LCDC_0,INT_LCDC_1,INT_ECC,INT_CALM,INT_ATA,INT_UART0,INT_SPDIF_OUT,
INT_SDCI,INT_LCD,INT_WHEEL,INT_IIC,RESERVED2,INT_MSTICK,INT_ADC_WAKEUP,INT_ADC
};
@@ -116,16 +118,16 @@ static void (* const irqvector[])(void) =
#if CONFIG_CPU==S5L8701
static const char * const irqname[] =
{ /* still 90% unverified and probably incorrect */
- "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMER","INT_WDT","INT_UNK1",
- "INT_UNK2","INT_UNK3","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
- "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT","INT_ECC",
+ "EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMER","INT_WDT","INT_UART2",
+ "INT_UNK1","INT_UNK2","INT_DMA","INT_ALARM_RTC","INT_UART1","INT_UNK3","INT_UNK4","INT_USB_HOST",
+ "INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_CALM","INT_ATA","INT_UNK5","INT_SPDIF_OUT","INT_ECC",
"INT_SDCI","INT_LCD","INT_WHEEL","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
};
#else
static const char * const irqname[] =
{
"EXT0","EXT1","EXT2","EINT_VBUS","EINTG","INT_TIMERA","INT_WDT","INT_TIMERB",
- "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART","INT_USB_HOST",
+ "INT_TIMERC","INT_TIMERD","INT_DMA","INT_ALARM_RTC","INT_PRI_RTC","Reserved","INT_UART1","INT_USB_HOST",
"INT_USB_FUNC","INT_LCDC_0","INT_LCDC_1","INT_ECC","INT_CALM","INT_ATA","INT_UART0","INT_SPDIF_OUT",
"INT_SDCI","INT_LCD","INT_WHEEL","INT_IIC","Reserved","INT_MSTICK","INT_ADC_WAKEUP","INT_ADC"
};
@@ -172,6 +174,9 @@ void system_init(void)
#ifdef IPOD_NANO2G
pmu_init();
#endif
+#ifdef HAVE_SERIAL
+ uart_init();
+#endif
}
void system_reboot(void)
diff --git a/firmware/target/arm/s5l8700/uart-s5l8700.c b/firmware/target/arm/s5l8700/uart-s5l8700.c
new file mode 100644
index 0000000000..80207e94df
--- /dev/null
+++ b/firmware/target/arm/s5l8700/uart-s5l8700.c
@@ -0,0 +1,129 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2014 by Cástor Muñoz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "config.h"
+#include "system.h"
+
+#include "s5l8700.h"
+#include "uc870x.h"
+
+
+/*
+ * XXX: This code is based on datasheets and NEVER TESTED !!!
+ */
+
+
+/*
+ * s5l8700 UC870X HW: 1 UARTC, 2 ports
+ */
+static struct uartc_port *uartc_port_l[UARTC_N_PORTS];
+const struct uartc s5l8700_uartc =
+{
+ .id = 0,
+ .baddr = UARTC_BASE_ADDR,
+ .port_off = UARTC_PORT_OFFSET,
+ .n_ports = UARTC_N_PORTS,
+ .port_l = uartc_port_l,
+};
+
+static int intmsk_uart[S5L8700_N_PORTS] = { INTMSK_UART0, INTMSK_UART1 };
+
+/*
+ * Device level functions specific to S5L8700
+ */
+void uart_target_enable_gpio(int uart_id, int port_id)
+{
+ (void) uart_id;
+ switch (port_id) {
+ /* configure UARTx Tx/Rx GPIO ports */
+ case 0:
+ PCON0 = (PCON0 & 0x0fff) | 0xa000;
+ break;
+ case 1:
+ PCON6 = (PCON6 & 0xfff00fff) | 0x00044000;
+ break;
+ }
+}
+
+void uart_target_disable_gpio(int uart_id, int port_id)
+{
+ (void) uart_id;
+ switch (port_id) {
+ /* configure default reset values */
+ case 0:
+ PCON0 = (PCON0 & 0x0fff) | 0x0000;
+ break;
+ case 1:
+ PCON6 = (PCON6 & 0xfff00fff) | 0x00000000;
+ break;
+ }
+}
+
+void uart_target_enable_irq(int uart_id, int port_id)
+{
+ (void) uart_id;
+ INTMSK |= intmsk_uart[port_id];
+}
+
+void uart_target_disable_irq(int uart_id, int port_id)
+{
+ (void) uart_id;
+ INTMSK &= ~intmsk_uart[port_id];
+}
+
+void uart_target_clear_irq(int uart_id, int port_id)
+{
+ (void) uart_id;
+ SRCPND |= intmsk_uart[port_id];
+}
+
+void uart_target_enable_clocks(int uart_id)
+{
+ (void) uart_id;
+ PWRCON &= ~(1 << CLOCKGATE_UARTC);
+}
+
+void uart_target_disable_clocks(int uart_id)
+{
+ (void) uart_id;
+ PWRCON |= (1 << CLOCKGATE_UARTC);
+}
+
+/*
+ * ISRs
+ */
+void ICODE_ATTR INT_UART0(void)
+{
+ uartc_callback(&s5l8700_uartc, 0);
+}
+
+void ICODE_ATTR INT_UART1(void)
+{
+ uartc_callback(&s5l8700_uartc, 1);
+}
+
+/* Main init */
+void uart_init(void)
+{
+ uartc_open(&s5l8700_uartc);
+}
diff --git a/firmware/target/arm/s5l8700/uart-s5l8701.c b/firmware/target/arm/s5l8700/uart-s5l8701.c
new file mode 100644
index 0000000000..00c9322e47
--- /dev/null
+++ b/firmware/target/arm/s5l8700/uart-s5l8701.c
@@ -0,0 +1,160 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2014 by Cástor Muñoz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "config.h"
+#include "system.h"
+
+#include "s5l8700.h"
+#include "uc870x.h"
+
+
+/*
+ * s5l8701 UC870X HW: 3 UARTC, 1 port per UARTC
+ */
+static struct uartc_port *uartc0_port_l[UARTC0_N_PORTS];
+const struct uartc s5l8701_uartc0 =
+{
+ .id = 0,
+ .baddr = UARTC0_BASE_ADDR,
+ .port_off = UARTC0_PORT_OFFSET,
+ .n_ports = UARTC0_N_PORTS,
+ .port_l = uartc0_port_l,
+};
+
+/* UARTC1,2 not used on Nano2G */
+#ifndef IPOD_NANO2G
+static struct uartc_port *uartc1_port_l[UARTC1_N_PORTS];
+const struct uartc s5l8701_uartc1 =
+{
+ .id = 1,
+ .baddr = UARTC1_BASE_ADDR,
+ .port_off = UARTC1_PORT_OFFSET,
+ .n_ports = UARTC1_N_PORTS,
+ .port_l = uartc1_port_l,
+};
+
+static struct uartc_port *uartc2_port_l[UARTC2_N_PORTS];
+const struct uartc s5l8701_uartc2 =
+{
+ .id = 2,
+ .baddr = UARTC2_BASE_ADDR,
+ .port_off = UARTC2_PORT_OFFSET,
+ .n_ports = UARTC2_N_PORTS,
+ .port_l = uartc2_port_l,
+};
+#endif
+
+static uint8_t clockgate_uartc[S5L8701_N_UARTC] = {
+ CLOCKGATE_UARTC0, CLOCKGATE_UARTC1, CLOCKGATE_UARTC2 };
+
+static int intmsk_uart[S5L8701_N_UARTC] = {
+ INTMSK_UART0, INTMSK_UART1, INTMSK_UART2 };
+
+/*
+ * Device level functions specific to S5L8701
+ */
+void uart_target_enable_gpio(int uart_id, int port_id)
+{
+ (void) port_id;
+ switch (uart_id) {
+ /* configure UARTx Tx/Rx GPIO ports */
+ case 0:
+ PCON1 = (PCON1 & 0xffffff00) | 0x00000044;
+ break;
+ case 1:
+ case 2:
+ /* unknown */
+ default:
+ break;
+ }
+}
+
+void uart_target_disable_gpio(int uart_id, int port_id)
+{
+ (void) port_id;
+ switch (uart_id) {
+ /* configure minimal power consumption */
+ case 0:
+ PCON1 = (PCON1 & 0xffffff00) | 0x00000011;
+ break;
+ case 1:
+ case 2:
+ default:
+ break;
+ }
+}
+
+void uart_target_enable_irq(int uart_id, int port_id)
+{
+ (void) port_id;
+ INTMSK |= intmsk_uart[uart_id];
+}
+
+void uart_target_disable_irq(int uart_id, int port_id)
+{
+ (void) port_id;
+ INTMSK &= ~intmsk_uart[uart_id];
+}
+
+void uart_target_clear_irq(int uart_id, int port_id)
+{
+ (void) port_id;
+ SRCPND |= intmsk_uart[uart_id];
+}
+
+void uart_target_enable_clocks(int uart_id)
+{
+ PWRCON &= ~(1 << clockgate_uartc[uart_id]);
+}
+
+void uart_target_disable_clocks(int uart_id)
+{
+ PWRCON |= (1 << clockgate_uartc[uart_id]);
+}
+
+/*
+ * ISRs
+ */
+void ICODE_ATTR INT_UART0(void)
+{
+ uartc_callback(&s5l8701_uartc0, 0);
+}
+
+/* UARTC1,2 not used on Nano2G */
+#ifndef IPOD_NANO2G
+void ICODE_ATTR INT_UART1(void)
+{
+ uartc_callback(&s5l8701_uartc1, 0);
+}
+
+void ICODE_ATTR INT_UART2(void)
+{
+ uartc_callback(&s5l8701_uartc2, 0);
+}
+#endif
+
+/* Main init */
+void uart_init(void)
+{
+ uartc_open(&s5l8701_uartc0);
+}
diff --git a/firmware/target/arm/s5l8700/uart-target.h b/firmware/target/arm/s5l8700/uart-target.h
new file mode 100644
index 0000000000..d6d45b9073
--- /dev/null
+++ b/firmware/target/arm/s5l8700/uart-target.h
@@ -0,0 +1,38 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2014 by Cástor Muñoz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __UART_TARGET_H__
+#define __UART_TARGET_H__
+
+/* Define this to show debug data on "View HW Info" */
+/* #define UC870X_DEBUG */
+
+void uart_init(void);
+
+/* s5l870x low level routines */
+void uart_target_enable_clocks(int uart_id);
+void uart_target_disable_clocks(int uart_id);
+void uart_target_enable_irq(int uart_id, int port_id);
+void uart_target_disable_irq(int uart_id, int port_id);
+void uart_target_clear_irq(int uart_id, int port_id);
+void uart_target_enable_gpio(int uart_id, int port_id);
+void uart_target_disable_gpio(int uart_id, int port_id);
+
+#endif /* __UART_TARGET_H__ */