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authorAidan MacDonald <amachronic@protonmail.com>2021-12-02 21:31:54 +0000
committerAidan MacDonald <amachronic@protonmail.com>2021-12-02 21:31:54 +0000
commit2512ed1c56a7c415f5a13ac2f38f72278e3ac660 (patch)
treee500f3c7ea491f996fe9c33aaa7ed62b9ca234b7
parent4162a4618426b259c8b87c75c127f6f47b2b7ab0 (diff)
downloadrockbox-2512ed1c56a7c415f5a13ac2f38f72278e3ac660.tar.gz
rockbox-2512ed1c56a7c415f5a13ac2f38f72278e3ac660.zip
Make inline functions in headers 'static inline'
Future-proofing against newer versions of GCC/binutils which are stricter about the use of 'inline' functions in headers. Change-Id: Id620812ed340f0d790ba6c5b8b5cb1d700acfbbf
-rw-r--r--firmware/export/i2c-async.h9
-rw-r--r--firmware/target/mips/ingenic_x1000/clk-x1000.h4
-rw-r--r--firmware/target/mips/ingenic_x1000/sfc-x1000.h4
3 files changed, 9 insertions, 8 deletions
diff --git a/firmware/export/i2c-async.h b/firmware/export/i2c-async.h
index 2877d1875c..f31a73452b 100644
--- a/firmware/export/i2c-async.h
+++ b/firmware/export/i2c-async.h
@@ -247,14 +247,15 @@ extern int i2c_reg_modify1(int bus, uint8_t addr, uint8_t reg,
uint8_t clr, uint8_t set, uint8_t* val);
/* Variant to write a single 8-bit value to a register */
-inline int i2c_reg_write1(int bus, uint8_t addr, uint8_t reg, uint8_t val)
+static inline int i2c_reg_write1(int bus, uint8_t addr,
+ uint8_t reg, uint8_t val)
{
return i2c_reg_write(bus, addr, reg, 1, &val);
}
/* Variant to read an 8-bit value from a register; returns the value
* directly, or returns -1 on any error. */
-inline int i2c_reg_read1(int bus, uint8_t addr, uint8_t reg)
+static inline int i2c_reg_read1(int bus, uint8_t addr, uint8_t reg)
{
uint8_t v;
int i = i2c_reg_read(bus, addr, reg, 1, &v);
@@ -265,8 +266,8 @@ inline int i2c_reg_read1(int bus, uint8_t addr, uint8_t reg)
}
/* Variant to set or clear one bit in an 8-bit register */
-inline int i2c_reg_setbit1(int bus, uint8_t addr, uint8_t reg,
- int bit, int value, uint8_t* val)
+static inline int i2c_reg_setbit1(int bus, uint8_t addr, uint8_t reg,
+ int bit, int value, uint8_t* val)
{
uint8_t clr = 0, set = 0;
if(value)
diff --git a/firmware/target/mips/ingenic_x1000/clk-x1000.h b/firmware/target/mips/ingenic_x1000/clk-x1000.h
index e19c56d0ba..f7153da564 100644
--- a/firmware/target/mips/ingenic_x1000/clk-x1000.h
+++ b/firmware/target/mips/ingenic_x1000/clk-x1000.h
@@ -80,13 +80,13 @@ extern void clk_set_ccr_div(uint32_t divbits);
extern void clk_set_ddr(x1000_clk_t src, uint32_t div);
/* Returns the smallest n such that infreq/n <= outfreq */
-inline uint32_t clk_calc_div(uint32_t infreq, uint32_t outfreq)
+static inline uint32_t clk_calc_div(uint32_t infreq, uint32_t outfreq)
{
return (infreq + (outfreq - 1)) / outfreq;
}
/* Returns the smallest n such that (infreq >> n) <= outfreq */
-inline uint32_t clk_calc_shift(uint32_t infreq, uint32_t outfreq)
+static inline uint32_t clk_calc_shift(uint32_t infreq, uint32_t outfreq)
{
uint32_t div = clk_calc_div(infreq, outfreq);
return __builtin_clz(div) ^ 31;
diff --git a/firmware/target/mips/ingenic_x1000/sfc-x1000.h b/firmware/target/mips/ingenic_x1000/sfc-x1000.h
index d28bcb6740..afb4aa3ce6 100644
--- a/firmware/target/mips/ingenic_x1000/sfc-x1000.h
+++ b/firmware/target/mips/ingenic_x1000/sfc-x1000.h
@@ -87,13 +87,13 @@ extern void sfc_irq_end(void);
extern void sfc_set_clock(uint32_t freq);
/* Set the device configuration register */
-inline void sfc_set_dev_conf(uint32_t conf)
+static inline void sfc_set_dev_conf(uint32_t conf)
{
REG_SFC_DEV_CONF = conf;
}
/* Control the state of the write protect pin */
-inline void sfc_set_wp_enable(bool en)
+static inline void sfc_set_wp_enable(bool en)
{
jz_writef(SFC_GLB, WP_EN(en ? 1 : 0));
}