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author | Solomon Peachy <pizza@shaftnet.org> | 2023-01-13 16:59:58 -0500 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2023-01-13 17:02:23 -0500 |
commit | 255a34c6858b65f42f83675522219651fa567154 (patch) | |
tree | e02e1e6c27ce76a51a42d32fcbee145ab7d5768d | |
parent | 641e91aa2ff4d81eca57a5279be4c8387de3510f (diff) | |
download | rockbox-255a34c685.tar.gz rockbox-255a34c685.zip |
fix red from #641e91aa2f
Change-Id: I7e648a7bdf1d706258afd49c1edd63655b2d2830
-rw-r--r-- | firmware/export/jz4740.h | 3 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h index 379c9f8aaa..354379a950 100644 --- a/firmware/export/jz4740.h +++ b/firmware/export/jz4740.h @@ -4986,6 +4986,7 @@ do{ \ #define IPU_V_BASE 0xB3080000 #define IPU__SIZE 0x00001000 +#ifndef __ASSEMBLY__ struct ipu_module { unsigned int reg_ctrl; // 0x0 @@ -5022,7 +5023,7 @@ struct Ration2m float ratio; int n, m; }; - +#endif /* !__ASSEMBLY__ */ // Register offset #define REG_CTRL 0x0 diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index ef99048812..3a1321b992 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c @@ -533,7 +533,7 @@ static void serial_setbrg(void) *uart_lcr = tmp; } -static int serial_preinit(void); +static int serial_preinit(void) { volatile u8 *uart_fcr = (volatile u8 *)(CFG_UART_BASE + OFF_FCR); volatile u8 *uart_lcr = (volatile u8 *)(CFG_UART_BASE + OFF_LCR); |