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authorJens Arnold <amiconn@rockbox.org>2009-10-19 21:38:52 +0000
committerJens Arnold <amiconn@rockbox.org>2009-10-19 21:38:52 +0000
commit2dd45f7c6d21079f4de0a6c55659e1d0224d02ba (patch)
tree0d3d415591f87cb3626aa569dd19af4ad3ebe14f
parent09de59708dbc0a3df99d6153bca46b9efd7ba830 (diff)
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Make RoLo work on PP5002. * Rename CACHE_CTL flag values on PP5002 for consistency.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23277 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/export/pp5002.h7
-rw-r--r--firmware/rolo.c17
-rw-r--r--firmware/target/arm/crt0-pp-bl.S2
-rw-r--r--firmware/target/arm/system-pp5002.c4
4 files changed, 17 insertions, 13 deletions
diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h
index cdf0318e55..b0c31d9474 100644
--- a/firmware/export/pp5002.h
+++ b/firmware/export/pp5002.h
@@ -214,8 +214,9 @@
/* Cache Control */
#define CACHE_CTL (*(volatile unsigned long *)(0xcf004024))
-#define CACHE_RUN 0x1
-#define CACHE_INIT 0x2
+#define CACHE_CTL_DISABLE 0x0
+#define CACHE_CTL_RUN 0x1
+#define CACHE_CTL_INIT 0x2
#define CACHE_MASK (*(volatile unsigned long *)(0xf000f020))
#define CACHE_OPERATION (*(volatile unsigned long *)(0xf000f024))
@@ -239,6 +240,8 @@
#define PLL_MULT (*(volatile unsigned long *)(0xcf00501c))
#define PLL_UNLOCK (*(volatile unsigned long *)(0xcf005038))
+#define MMAP_FIRST (*(volatile unsigned long *)(0xf000f000))
+#define MMAP_LAST (*(volatile unsigned long *)(0xf000f01c))
#define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000))
#define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004))
#define MMAP1_LOGICAL (*(volatile unsigned long *)(0xf000f008))
diff --git a/firmware/rolo.c b/firmware/rolo.c
index 58404eecff..c7927978bd 100644
--- a/firmware/rolo.c
+++ b/firmware/rolo.c
@@ -44,9 +44,8 @@
#define FIRMWARE_OFFSET_FILE_DATA 0x200
#endif
-#if !defined(IRIVER_IFP7XX_SERIES) && \
- (CONFIG_CPU != PP5002)
-/* FIX: this doesn't work on iFP, 3rd Gen ipods */
+#if !defined(IRIVER_IFP7XX_SERIES)
+/* FIX: this doesn't work on iFP */
#define IRQ0_EDGE_TRIGGER 0x80
@@ -92,8 +91,9 @@ void rolo_restart_cop(void)
cpu_reply = 2;
asm volatile(
- "mov r0, #0x10000000 \n"
- "mov pc, r0 \n"
+ "mov r0, %0 \n"
+ "mov pc, r0 \n"
+ : : "I"(DRAM_START)
);
}
#endif /* NUM_CORES > 1 */
@@ -144,7 +144,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
"jmp (%0) \n"
: : "a"(dest)
);
-#elif defined(CPU_PP502x)
+#elif defined(CPU_PP)
CPU_INT_DIS = -1;
/* Flush cache */
@@ -169,8 +169,9 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
#endif
asm volatile(
- "mov r0, #0x10000000 \n"
- "mov pc, r0 \n"
+ "mov r0, %0 \n"
+ "mov pc, r0 \n"
+ : : "I"(DRAM_START)
);
#elif defined(CPU_ARM)
diff --git a/firmware/target/arm/crt0-pp-bl.S b/firmware/target/arm/crt0-pp-bl.S
index 85950bb257..1d2909e7f4 100644
--- a/firmware/target/arm/crt0-pp-bl.S
+++ b/firmware/target/arm/crt0-pp-bl.S
@@ -45,7 +45,7 @@ start:
.equ CPUSLEEPING, 0x8000
.equ COPSLEEPING, 0x4000
.equ CACHE_CTRL, 0xcf004024
- .equ CACHE_ENAB, 0x2 /* Actually the CACHE_INIT flag */
+ .equ CACHE_ENAB, 0x2 /* Actually the CACHE_CTL_INIT flag */
#else
.equ PROC_ID, 0x60000000
.equ CPU_CTRL, 0x60007000
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c
index 98bf5f21f1..976e5e585b 100644
--- a/firmware/target/arm/system-pp5002.c
+++ b/firmware/target/arm/system-pp5002.c
@@ -97,7 +97,7 @@ static void ipod_init_cache(void)
PROC_STAT &= ~0x700;
outl(0x4000, 0xcf004020);
- CACHE_CTL = CACHE_INIT;
+ CACHE_CTL = CACHE_CTL_INIT;
for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE;
b < e; b += 16) {
@@ -113,7 +113,7 @@ static void ipod_init_cache(void)
CACHE_MASK = 0x00001c00;
CACHE_OPERATION = 0x3fc0;
- CACHE_CTL = CACHE_INIT | CACHE_RUN;
+ CACHE_CTL = CACHE_CTL_INIT | CACHE_CTL_RUN;
}
#ifdef HAVE_ADJUSTABLE_CPU_FREQ