diff options
| author | Vencislav Atanasov <user890104@freemyipod.org> | 2024-11-24 01:10:11 +0200 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2024-11-24 20:02:44 -0500 |
| commit | 375a6bc9b1e6a7fa14daff1e82a4b82547f7d9bc (patch) | |
| tree | 98577b3fc8b1c05aa55414d4de5f95862db2a63e | |
| parent | 18fdb41b2c1de45dd8b9a4e30b4199b57c390e29 (diff) | |
| download | rockbox-375a6bc9b1.tar.gz rockbox-375a6bc9b1.zip | |
s5l87xx: Use pointer arithmetic in register address calculation
This allows to reuse a register definition across similar SoCs that have the same layout of registers (same offsets), but are using a different base address for the peripheral. The include guard was also fixed to reflect the new file name of the header.
Some registers were renamed in order to match the datasheet and for consistency with the other register numbering.
Change-Id: I0192e227a3c467504b8fcd1eb684a7fc861f7896
| -rw-r--r-- | firmware/export/s5l87xx.h | 1727 | ||||
| -rw-r--r-- | firmware/target/arm/ipod/button-clickwheel.c | 6 | ||||
| -rw-r--r-- | firmware/target/arm/s5l8702/ipod6g/power-6g.c | 4 | ||||
| -rw-r--r-- | firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c | 4 | ||||
| -rw-r--r-- | firmware/target/arm/s5l8702/spi-s5l8702.c | 4 | ||||
| -rw-r--r-- | firmware/target/arm/s5l8702/system-s5l8702.c | 7 | ||||
| -rw-r--r-- | firmware/target/arm/s5l8702/uart-s5l8702.c | 4 |
7 files changed, 870 insertions, 886 deletions
diff --git a/firmware/export/s5l87xx.h b/firmware/export/s5l87xx.h index 20701aaeac..7dc2d692ea 100644 --- a/firmware/export/s5l87xx.h +++ b/firmware/export/s5l87xx.h @@ -19,15 +19,17 @@ * ****************************************************************************/ -#ifndef __S5L8700_H__ -#define __S5L8700_H__ +#ifndef __S5L87XX_H__ +#define __S5L87XX_H__ #ifndef ASM #include <stdint.h> #endif -#define REG16_PTR_T volatile uint16_t * -#define REG32_PTR_T volatile uint32_t * +#define REG16_PTR_T volatile uint16_t * +#define REG32_PTR_T volatile uint32_t * +#define VOID_PTR_PTR_T void* volatile* +#define CONST_VOID_PTR_PTR_T const void* volatile* #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ @@ -54,124 +56,130 @@ /* 04. CALMADM2E */ /* Following registers are mapped on IO Area in data memory area of Calm. */ -#define CONFIG0 (*(REG16_PTR_T)(0x3F000000)) /* configuration/control register 0 */ -#define CONFIG1 (*(REG16_PTR_T)(0x3F000002)) /* configuration/control register 1*/ -#define COMMUN (*(REG16_PTR_T)(0x3F000004)) /* Communication Control Register */ -#define DDATA0 (*(REG16_PTR_T)(0x3F000006)) /* Communication data from host to ADM */ -#define DDATA1 (*(REG16_PTR_T)(0x3F000008)) /* Communication data from host to ADM */ -#define DDATA2 (*(REG16_PTR_T)(0x3F00000A)) /* Communication data from host to ADM */ -#define DDATA3 (*(REG16_PTR_T)(0x3F00000C)) /* Communication data from host to ADM */ -#define DDATA4 (*(REG16_PTR_T)(0x3F00000E)) /* Communication data from host to ADM */ -#define DDATA5 (*(REG16_PTR_T)(0x3F000010)) /* Communication data from host to ADM */ -#define DDATA6 (*(REG16_PTR_T)(0x3F000012)) /* Communication data from host to ADM */ -#define DDATA7 (*(REG16_PTR_T)(0x3F000014)) /* Communication data from host to ADM */ -#define UDATA0 (*(REG16_PTR_T)(0x3F000016)) /* Communication data from ADM to host */ -#define UDATA1 (*(REG16_PTR_T)(0x3F000018)) /* Communication data from ADM to host */ -#define UDATA2 (*(REG16_PTR_T)(0x3F00001A)) /* Communication data from ADM to host */ -#define UDATA3 (*(REG16_PTR_T)(0x3F00001C)) /* Communication data from ADM to host */ -#define UDATA4 (*(REG16_PTR_T)(0x3F00001E)) /* Communication data from ADM to host */ -#define UDATA5 (*(REG16_PTR_T)(0x3F000020)) /* Communication data from ADM to host */ -#define UDATA6 (*(REG16_PTR_T)(0x3F000022)) /* Communication data from ADM to host */ -#define UDATA7 (*(REG16_PTR_T)(0x3F000024)) /* Communication data from ADM to host */ -#define IBASE_H (*(REG16_PTR_T)(0x3F000026)) /* Higher half of start address for ADM instruction area */ -#define IBASE_L (*(REG16_PTR_T)(0x3F000028)) /* Lower half of start address for ADM instruction area */ -#define DBASE_H (*(REG16_PTR_T)(0x3F00002A)) /* Higher half of start address for CalmRISC data area */ -#define DBASE_L (*(REG16_PTR_T)(0x3F00002C)) /* Lower half of start address for CalmRISC data area */ -#define XBASE_H (*(REG16_PTR_T)(0x3F00002E)) /* Higher half of start address for Mac X area */ -#define XBASE_L (*(REG16_PTR_T)(0x3F000030)) /* Lower half of start address for Mac X area */ -#define YBASE_H (*(REG16_PTR_T)(0x3F000032)) /* Higher half of start address for Mac Y area */ -#define YBASE_L (*(REG16_PTR_T)(0x3F000034)) /* Lower half of start address for Mac Y area */ -#define S0BASE_H (*(REG16_PTR_T)(0x3F000036)) /* Higher half of start address for sequential buffer 0 area */ -#define S0BASE_L (*(REG16_PTR_T)(0x3F000038)) /* Lower half of start address for sequential buffer 0 area */ -#define S1BASE_H (*(REG16_PTR_T)(0x3F00003A)) /* Higher half of start address for sequential buffer 1 area */ -#define S1BASE_L (*(REG16_PTR_T)(0x3F00003C)) /* Lower half of start address for sequential buffer 1 area */ -#define CACHECON (*(REG16_PTR_T)(0x3F00003E)) /* Cache Control Register */ -#define CACHESTAT (*(REG16_PTR_T)(0x3F000040)) /* Cache status register */ -#define SBFCON (*(REG16_PTR_T)(0x3F000042)) /* Sequential Buffer Control Register */ -#define SBFSTAT (*(REG16_PTR_T)(0x3F000044)) /* Sequential Buffer Status Register */ -#define SBL0OFF_H (*(REG16_PTR_T)(0x3F000046)) /* Higher bits of Offset register of sequential block 0 area */ -#define SBL0OFF_L (*(REG16_PTR_T)(0x3F000048)) /* Lower bits of Offset register of sequential block 0 area */ -#define SBL1OFF_H (*(REG16_PTR_T)(0x3F00004A)) /* Higher bits of Offset register of sequential block 1 area */ -#define SBL1OFF_L (*(REG16_PTR_T)(0x3F00004C)) /* Lower bits of Offset register of sequential block 1 area */ -#define SBL0BEGIN_H (*(REG16_PTR_T)(0x3F00004E)) /* Higher bits of Begin Offset of sequential block 0 area in ring mode */ -#define SBL0BEGIN_L (*(REG16_PTR_T)(0x3F000050)) /* Lower bits of Begin Offset of sequential block 0 area in ring mode */ -#define SBL1BEGIN_H (*(REG16_PTR_T)(0x3F000052)) /* Higher bits of Begin Offset of sequential block 1 area in ring mode */ -#define SBL1BEGIN_L (*(REG16_PTR_T)(0x3F000054)) /* Lower bits of Begin Offset of sequential block 1 area in ring mode */ -#define SBL0END_H (*(REG16_PTR_T)(0x3F000056)) /* Lower bits of End Offset of sequential block 0 area in ring mode */ -#define SBL0END_L (*(REG16_PTR_T)(0x3F000058)) /* Higher bits of End Offset of sequential block 0 area in ring mode */ -#define SBL1END_H (*(REG16_PTR_T)(0x3F00005A)) /* Lower bits of End Offset of sequential block 1 area in ring mode */ -#define SBL1END_L (*(REG16_PTR_T)(0x3F00005C)) /* Higher bits of End Offset of sequential block 1 area in ring mode */ +#define ADM_BASE 0x3F000000 + +#define CONFIG0 (*(REG16_PTR_T)(ADM_BASE)) /* configuration/control register 0 */ +#define CONFIG1 (*(REG16_PTR_T)(ADM_BASE + 0x02)) /* configuration/control register 1*/ +#define COMMUN (*(REG16_PTR_T)(ADM_BASE + 0x04)) /* Communication Control Register */ +#define DDATA0 (*(REG16_PTR_T)(ADM_BASE + 0x06)) /* Communication data from host to ADM */ +#define DDATA1 (*(REG16_PTR_T)(ADM_BASE + 0x08)) /* Communication data from host to ADM */ +#define DDATA2 (*(REG16_PTR_T)(ADM_BASE + 0x0A)) /* Communication data from host to ADM */ +#define DDATA3 (*(REG16_PTR_T)(ADM_BASE + 0x0C)) /* Communication data from host to ADM */ +#define DDATA4 (*(REG16_PTR_T)(ADM_BASE + 0x0E)) /* Communication data from host to ADM */ +#define DDATA5 (*(REG16_PTR_T)(ADM_BASE + 0x10)) /* Communication data from host to ADM */ +#define DDATA6 (*(REG16_PTR_T)(ADM_BASE + 0x12)) /* Communication data from host to ADM */ +#define DDATA7 (*(REG16_PTR_T)(ADM_BASE + 0x14)) /* Communication data from host to ADM */ +#define UDATA0 (*(REG16_PTR_T)(ADM_BASE + 0x16)) /* Communication data from ADM to host */ +#define UDATA1 (*(REG16_PTR_T)(ADM_BASE + 0x18)) /* Communication data from ADM to host */ +#define UDATA2 (*(REG16_PTR_T)(ADM_BASE + 0x1A)) /* Communication data from ADM to host */ +#define UDATA3 (*(REG16_PTR_T)(ADM_BASE + 0x1C)) /* Communication data from ADM to host */ +#define UDATA4 (*(REG16_PTR_T)(ADM_BASE + 0x1E)) /* Communication data from ADM to host */ +#define UDATA5 (*(REG16_PTR_T)(ADM_BASE + 0x20)) /* Communication data from ADM to host */ +#define UDATA6 (*(REG16_PTR_T)(ADM_BASE + 0x22)) /* Communication data from ADM to host */ +#define UDATA7 (*(REG16_PTR_T)(ADM_BASE + 0x24)) /* Communication data from ADM to host */ +#define IBASE_H (*(REG16_PTR_T)(ADM_BASE + 0x26)) /* Higher half of start address for ADM instruction area */ +#define IBASE_L (*(REG16_PTR_T)(ADM_BASE + 0x28)) /* Lower half of start address for ADM instruction area */ +#define DBASE_H (*(REG16_PTR_T)(ADM_BASE + 0x2A)) /* Higher half of start address for CalmRISC data area */ +#define DBASE_L (*(REG16_PTR_T)(ADM_BASE + 0x2C)) /* Lower half of start address for CalmRISC data area */ +#define XBASE_H (*(REG16_PTR_T)(ADM_BASE + 0x2E)) /* Higher half of start address for Mac X area */ +#define XBASE_L (*(REG16_PTR_T)(ADM_BASE + 0x30)) /* Lower half of start address for Mac X area */ +#define YBASE_H (*(REG16_PTR_T)(ADM_BASE + 0x32)) /* Higher half of start address for Mac Y area */ +#define YBASE_L (*(REG16_PTR_T)(ADM_BASE + 0x34)) /* Lower half of start address for Mac Y area */ +#define S0BASE_H (*(REG16_PTR_T)(ADM_BASE + 0x36)) /* Higher half of start address for sequential buffer 0 area */ +#define S0BASE_L (*(REG16_PTR_T)(ADM_BASE + 0x38)) /* Lower half of start address for sequential buffer 0 area */ +#define S1BASE_H (*(REG16_PTR_T)(ADM_BASE + 0x3A)) /* Higher half of start address for sequential buffer 1 area */ +#define S1BASE_L (*(REG16_PTR_T)(ADM_BASE + 0x3C)) /* Lower half of start address for sequential buffer 1 area */ +#define CACHECON (*(REG16_PTR_T)(ADM_BASE + 0x3E)) /* Cache Control Register */ +#define CACHESTAT (*(REG16_PTR_T)(ADM_BASE + 0x40)) /* Cache status register */ +#define SBFCON (*(REG16_PTR_T)(ADM_BASE + 0x42)) /* Sequential Buffer Control Register */ +#define SBFSTAT (*(REG16_PTR_T)(ADM_BASE + 0x44)) /* Sequential Buffer Status Register */ +#define SBL0OFF_H (*(REG16_PTR_T)(ADM_BASE + 0x46)) /* Higher bits of Offset register of sequential block 0 area */ +#define SBL0OFF_L (*(REG16_PTR_T)(ADM_BASE + 0x48)) /* Lower bits of Offset register of sequential block 0 area */ +#define SBL1OFF_H (*(REG16_PTR_T)(ADM_BASE + 0x4A)) /* Higher bits of Offset register of sequential block 1 area */ +#define SBL1OFF_L (*(REG16_PTR_T)(ADM_BASE + 0x4C)) /* Lower bits of Offset register of sequential block 1 area */ +#define SBL0BEGIN_H (*(REG16_PTR_T)(ADM_BASE + 0x4E)) /* Higher bits of Begin Offset of sequential block 0 area in ring mode */ +#define SBL0BEGIN_L (*(REG16_PTR_T)(ADM_BASE + 0x50)) /* Lower bits of Begin Offset of sequential block 0 area in ring mode */ +#define SBL1BEGIN_H (*(REG16_PTR_T)(ADM_BASE + 0x52)) /* Higher bits of Begin Offset of sequential block 1 area in ring mode */ +#define SBL1BEGIN_L (*(REG16_PTR_T)(ADM_BASE + 0x54)) /* Lower bits of Begin Offset of sequential block 1 area in ring mode */ +#define SBL0END_H (*(REG16_PTR_T)(ADM_BASE + 0x56)) /* Lower bits of End Offset of sequential block 0 area in ring mode */ +#define SBL0END_L (*(REG16_PTR_T)(ADM_BASE + 0x58)) /* Higher bits of End Offset of sequential block 0 area in ring mode */ +#define SBL1END_H (*(REG16_PTR_T)(ADM_BASE + 0x5A)) /* Lower bits of End Offset of sequential block 1 area in ring mode */ +#define SBL1END_L (*(REG16_PTR_T)(ADM_BASE + 0x5C)) /* Higher bits of End Offset of sequential block 1 area in ring mode */ /* Following registers are components of SFRS of the target system */ -#define ADM_CONFIG (*(REG32_PTR_T)(0x39000000)) /* Configuration/Control Register */ -#define ADM_COMMUN (*(REG32_PTR_T)(0x39000004)) /* Communication Control Register */ -#define ADM_DDATA0 (*(REG32_PTR_T)(0x39000010)) /* Communication data from host to ADM */ -#define ADM_DDATA1 (*(REG32_PTR_T)(0x39000014)) /* Communication data from host to ADM */ -#define ADM_DDATA2 (*(REG32_PTR_T)(0x39000018)) /* Communication data from host to ADM */ -#define ADM_DDATA3 (*(REG32_PTR_T)(0x3900001C)) /* Communication data from host to ADM */ -#define ADM_DDATA4 (*(REG32_PTR_T)(0x39000020)) /* Communication data from host to ADM */ -#define ADM_DDATA5 (*(REG32_PTR_T)(0x39000024)) /* Communication data from host to ADM */ -#define ADM_DDATA6 (*(REG32_PTR_T)(0x39000028)) /* Communication data from host to ADM */ -#define ADM_DDATA7 (*(REG32_PTR_T)(0x3900002C)) /* Communication data from host to ADM */ -#define ADM_UDATA0 (*(REG32_PTR_T)(0x39000030)) /* Communication data from ADM to host */ -#define ADM_UDATA1 (*(REG32_PTR_T)(0x39000034)) /* Communication data from ADM to host */ -#define ADM_UDATA2 (*(REG32_PTR_T)(0x39000038)) /* Communication data from ADM to host */ -#define ADM_UDATA3 (*(REG32_PTR_T)(0x3900003C)) /* Communication data from ADM to host */ -#define ADM_UDATA4 (*(REG32_PTR_T)(0x39000040)) /* Communication data from ADM to host */ -#define ADM_UDATA5 (*(REG32_PTR_T)(0x39000044)) /* Communication data from ADM to host */ -#define ADM_UDATA6 (*(REG32_PTR_T)(0x39000048)) /* Communication data from ADM to host */ -#define ADM_UDATA7 (*(REG32_PTR_T)(0x3900004C)) /* Communication data from ADM to host */ -#define ADM_IBASE (*(REG32_PTR_T)(0x39000050)) /* Start Address for ADM Instruction Area */ -#define ADM_DBASE (*(REG32_PTR_T)(0x39000054)) /* Start Address for CalmRISC Data Area */ -#define ADM_XBASE (*(REG32_PTR_T)(0x39000058)) /* Start Address for Mac X Area */ -#define ADM_YBASE (*(REG32_PTR_T)(0x3900005C)) /* Start Address for Mac Y Area */ -#define ADM_S0BASE (*(REG32_PTR_T)(0x39000060)) /* Start Address for Sequential Block 0 Area */ -#define ADM_S1BASE (*(REG32_PTR_T)(0x39000064)) /* Start Address for Sequential Block 1 Area */ +#define ADM_SFR_BASE 0x39000000 + +#define ADM_CONFIG (*(REG32_PTR_T)(ADM_SFR_BASE)) /* Configuration/Control Register */ +#define ADM_COMMUN (*(REG32_PTR_T)(ADM_SFR_BASE + 0x04)) /* Communication Control Register */ +#define ADM_DDATA0 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x10)) /* Communication data from host to ADM */ +#define ADM_DDATA1 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x14)) /* Communication data from host to ADM */ +#define ADM_DDATA2 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x18)) /* Communication data from host to ADM */ +#define ADM_DDATA3 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x1C)) /* Communication data from host to ADM */ +#define ADM_DDATA4 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x20)) /* Communication data from host to ADM */ +#define ADM_DDATA5 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x24)) /* Communication data from host to ADM */ +#define ADM_DDATA6 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x28)) /* Communication data from host to ADM */ +#define ADM_DDATA7 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x2C)) /* Communication data from host to ADM */ +#define ADM_UDATA0 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x30)) /* Communication data from ADM to host */ +#define ADM_UDATA1 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x34)) /* Communication data from ADM to host */ +#define ADM_UDATA2 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x38)) /* Communication data from ADM to host */ +#define ADM_UDATA3 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x3C)) /* Communication data from ADM to host */ +#define ADM_UDATA4 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x40)) /* Communication data from ADM to host */ +#define ADM_UDATA5 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x44)) /* Communication data from ADM to host */ +#define ADM_UDATA6 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x48)) /* Communication data from ADM to host */ +#define ADM_UDATA7 (*(REG32_PTR_T)(ADM_SFR_BASE + 0x4C)) /* Communication data from ADM to host */ +#define ADM_IBASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x50)) /* Start Address for ADM Instruction Area */ +#define ADM_DBASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x54)) /* Start Address for CalmRISC Data Area */ +#define ADM_XBASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x58)) /* Start Address for Mac X Area */ +#define ADM_YBASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x5C)) /* Start Address for Mac Y Area */ +#define ADM_S0BASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x60)) /* Start Address for Sequential Block 0 Area */ +#define ADM_S1BASE (*(REG32_PTR_T)(ADM_SFR_BASE + 0x64)) /* Start Address for Sequential Block 1 Area */ /* 05. CLOCK & POWER MANAGEMENT */ +#define CLK_BASE 0x3C500000 + #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 -#define CLKCON (*(REG32_PTR_T)(0x3C500000)) /* Clock control register */ -#define PLL0PMS (*(REG32_PTR_T)(0x3C500004)) /* PLL PMS value register */ -#define PLL1PMS (*(REG32_PTR_T)(0x3C500008)) /* PLL PMS value register */ -#define PLL2PMS (*(REG32_PTR_T)(0x3C50000C)) /* PLL PMS value register - S5L8701 only? */ -#define CLKCON3 (*(REG32_PTR_T)(0x3C500010)) /* Clock control register 3 */ -#define PLL0LCNT (*(REG32_PTR_T)(0x3C500014)) /* PLL0 lock count register */ -#define PLL1LCNT (*(REG32_PTR_T)(0x3C500018)) /* PLL1 lock count register */ -#define PLL2LCNT (*(REG32_PTR_T)(0x3C50001C)) /* PLL2 lock count register - S5L8701 only? */ -#define PLLLOCK (*(REG32_PTR_T)(0x3C500020)) /* PLL lock status register */ -#define PLLCON (*(REG32_PTR_T)(0x3C500024)) /* PLL control register */ -#define PWRCON (*(REG32_PTR_T)(0x3C500028)) /* Clock power control register */ -#define PWRMODE (*(REG32_PTR_T)(0x3C50002C)) /* Power mode control register */ -#define SWRCON (*(REG32_PTR_T)(0x3C500030)) /* Software reset control register */ -#define RSTSR (*(REG32_PTR_T)(0x3C500034)) /* Reset status register */ -#define DSPCLKMD (*(REG32_PTR_T)(0x3C500038)) /* DSP clock mode register */ -#define CLKCON2 (*(REG32_PTR_T)(0x3C50003C)) /* Clock control register 2 */ -#define PWRCONEXT (*(REG32_PTR_T)(0x3C500040)) /* Clock power control register 2 */ +#define CLKCON (*(REG32_PTR_T)(CLK_BASE)) /* Clock control register */ +#define PLL0PMS (*(REG32_PTR_T)(CLK_BASE + 0x04)) /* PLL PMS value register */ +#define PLL1PMS (*(REG32_PTR_T)(CLK_BASE + 0x08)) /* PLL PMS value register */ +#define PLL2PMS (*(REG32_PTR_T)(CLK_BASE + 0x0C)) /* PLL PMS value register - S5L8701 only? */ +#define CLKCON3 (*(REG32_PTR_T)(CLK_BASE + 0x10)) /* Clock control register 3 */ +#define PLL0LCNT (*(REG32_PTR_T)(CLK_BASE + 0x14)) /* PLL0 lock count register */ +#define PLL1LCNT (*(REG32_PTR_T)(CLK_BASE + 0x18)) /* PLL1 lock count register */ +#define PLL2LCNT (*(REG32_PTR_T)(CLK_BASE + 0x1C)) /* PLL2 lock count register - S5L8701 only? */ +#define PLLLOCK (*(REG32_PTR_T)(CLK_BASE + 0x20)) /* PLL lock status register */ +#define PLLCON (*(REG32_PTR_T)(CLK_BASE + 0x24)) /* PLL control register */ +#define PWRCON (*(REG32_PTR_T)(CLK_BASE + 0x28)) /* Clock power control register */ +#define PWRMODE (*(REG32_PTR_T)(CLK_BASE + 0x2C)) /* Power mode control register */ +#define SWRCON (*(REG32_PTR_T)(CLK_BASE + 0x30)) /* Software reset control register */ +#define RSTSR (*(REG32_PTR_T)(CLK_BASE + 0x34)) /* Reset status register */ +#define DSPCLKMD (*(REG32_PTR_T)(CLK_BASE + 0x38)) /* DSP clock mode register */ +#define CLKCON2 (*(REG32_PTR_T)(CLK_BASE + 0x3C)) /* Clock control register 2 */ +#define PWRCONEXT (*(REG32_PTR_T)(CLK_BASE + 0x40)) /* Clock power control register 2 */ #elif CONFIG_CPU==S5L8702 -#define CLKCON0 (*((REG32_PTR_T)(0x3C500000))) -#define CLKCON1 (*((REG32_PTR_T)(0x3C500004))) -#define CLKCON2 (*((REG32_PTR_T)(0x3C500008))) -#define CLKCON3 (*((REG32_PTR_T)(0x3C50000C))) -#define CLKCON4 (*((REG32_PTR_T)(0x3C500010))) -#define CLKCON5 (*((REG32_PTR_T)(0x3C500014))) -#define PLL0PMS (*((REG32_PTR_T)(0x3C500020))) -#define PLL1PMS (*((REG32_PTR_T)(0x3C500024))) -#define PLL2PMS (*((REG32_PTR_T)(0x3C500028))) -#define PLL0LCNT (*((REG32_PTR_T)(0x3C500030))) -#define PLL1LCNT (*((REG32_PTR_T)(0x3C500034))) -#define PLL2LCNT (*((REG32_PTR_T)(0x3C500038))) -#define PLLLOCK (*((REG32_PTR_T)(0x3C500040))) -#define PLLMODE (*((REG32_PTR_T)(0x3C500044))) -#define PWRCON(i) (*((REG32_PTR_T)(0x3C500000 \ +#define CLKCON0 (*((REG32_PTR_T)(CLK_BASE))) +#define CLKCON1 (*((REG32_PTR_T)(CLK_BASE + 0x04))) +#define CLKCON2 (*((REG32_PTR_T)(CLK_BASE + 0x08))) +#define CLKCON3 (*((REG32_PTR_T)(CLK_BASE + 0x0C))) +#define CLKCON4 (*((REG32_PTR_T)(CLK_BASE + 0x10))) +#define CLKCON5 (*((REG32_PTR_T)(CLK_BASE + 0x14))) +#define PLL0PMS (*((REG32_PTR_T)(CLK_BASE + 0x20))) +#define PLL1PMS (*((REG32_PTR_T)(CLK_BASE + 0x24))) +#define PLL2PMS (*((REG32_PTR_T)(CLK_BASE + 0x28))) +#define PLL0LCNT (*((REG32_PTR_T)(CLK_BASE + 0x30))) +#define PLL1LCNT (*((REG32_PTR_T)(CLK_BASE + 0x34))) +#define PLL2LCNT (*((REG32_PTR_T)(CLK_BASE + 0x38))) +#define PLLLOCK (*((REG32_PTR_T)(CLK_BASE + 0x40))) +#define PLLMODE (*((REG32_PTR_T)(CLK_BASE + 0x44))) +#define PWRCON(i) (*((REG32_PTR_T)(CLK_BASE \ + ((i) == 4 ? 0x6C : \ ((i) == 3 ? 0x68 : \ ((i) == 2 ? 0x58 : \ ((i) == 1 ? 0x4C : \ 0x48))))))) /* SW Reset Control Register */ -#define SWRCON (*((REG32_PTR_T)(0x3C500050))) +#define SWRCON (*((REG32_PTR_T)(CLK_BASE + 0x50))) /* Reset Status Register */ -#define RSTSR (*((REG32_PTR_T)(0x3C500054))) +#define RSTSR (*((REG32_PTR_T)(CLK_BASE + 0x54))) #define RSTSR_WDR_BIT (1 << 2) #define RSTSR_SWR_BIT (1 << 1) #define RSTSR_HWR_BIT (1 << 0) @@ -214,9 +222,12 @@ #endif /* 06. INTERRUPT CONTROLLER UNIT */ -#define SRCPND (*(REG32_PTR_T)(0x39C00000)) /* Indicates the interrupt request status. */ -#define INTMOD (*(REG32_PTR_T)(0x39C00004)) /* Interrupt mode register. */ -#define INTMSK (*(REG32_PTR_T)(0x39C00008)) /* Determines which interrupt source is masked. The */ +#define INT_BASE 0x39C00000 + +#define SRCPND (*(REG32_PTR_T)(INT_BASE)) /* Indicates the interrupt request status. */ +#define INTMOD (*(REG32_PTR_T)(INT_BASE + 0x04)) /* Interrupt mode register. */ +#define INTMSK (*(REG32_PTR_T)(INT_BASE + 0x08)) /* Determines which interrupt source is masked. + The masked interrupt source will not be serviced. */ #if CONFIG_CPU==S5L8700 #define INTMSK_TIMERA (1<<5) @@ -241,14 +252,14 @@ #define INTMSK_UART2 (1<<7) #endif -#define PRIORITY (*(REG32_PTR_T)(0x39C0000C)) /* IRQ priority control register */ -#define INTPND (*(REG32_PTR_T)(0x39C00010)) /* Indicates the interrupt request status. */ -#define INTOFFSET (*(REG32_PTR_T)(0x39C00014)) /* Indicates the IRQ interrupt request source */ +#define PRIORITY (*(REG32_PTR_T)(INT_BASE + 0x0C)) /* IRQ priority control register */ +#define INTPND (*(REG32_PTR_T)(INT_BASE + 0x10)) /* Indicates the interrupt request status. */ +#define INTOFFSET (*(REG32_PTR_T)(INT_BASE + 0x14)) /* Indicates the IRQ interrupt request source */ #if CONFIG_CPU==S5L8700 -#define EINTPOL (*(REG32_PTR_T)(0x39C00018)) /* Indicates external interrupt polarity */ -#define EINTPEND (*(REG32_PTR_T)(0x39C0001C)) /* Indicates whether external interrupts are pending. */ -#define EINTMSK (*(REG32_PTR_T)(0x39C00020)) /* Indicates whether external interrupts are masked */ +#define EINTPOL (*(REG32_PTR_T)(INT_BASE + 0x18)) /* Indicates external interrupt polarity */ +#define EINTPEND (*(REG32_PTR_T)(INT_BASE + 0x1C)) /* Indicates whether external interrupts are pending. */ +#define EINTMSK (*(REG32_PTR_T)(INT_BASE + 0x20)) /* Indicates whether external interrupts are masked */ #elif CONFIG_CPU==S5L8701 /* * s5l8701 GPIO (External) Interrupt Controller. @@ -264,112 +275,111 @@ * Group2[31:0] PDAT11:PDAT10:PDAT7:PDAT6 * Group3[31:0] PDAT15:PDAT14:PDAT13:PDAT12 */ -#define GPIOIC_INTLEVEL(g) (*(REG32_PTR_T)(0x39C00018 + 4*(g))) -#define GPIOIC_INTSTAT(g) (*(REG32_PTR_T)(0x39C00028 + 4*(g))) -#define GPIOIC_INTEN(g) (*(REG32_PTR_T)(0x39C00038 + 4*(g))) -#define GPIOIC_INTTYPE(g) (*(REG32_PTR_T)(0x39C00048 + 4*(g))) +#define GPIOIC_INTLEVEL(g) (*(REG32_PTR_T)(INT_BASE + 0x18 + 4*(g))) +#define GPIOIC_INTSTAT(g) (*(REG32_PTR_T)(INT_BASE + 0x28 + 4*(g))) +#define GPIOIC_INTEN(g) (*(REG32_PTR_T)(INT_BASE + 0x38 + 4*(g))) +#define GPIOIC_INTTYPE(g) (*(REG32_PTR_T)(INT_BASE + 0x48 + 4*(g))) #endif /* 07. MEMORY INTERFACE UNIT (MIU) */ #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 +#define MIU_BASE 0x38200000 +#elif CONFIG_CPU==S5L8702 +#define MIU_BASE 0x38100000 +#endif + +#define MIU_REG(off) (*((REG32_PTR_T)(MIU_BASE + (off)))) + /* SDRAM */ -#define MIUCON (*(REG32_PTR_T)(0x38200000)) /* External Memory configuration register */ -#define MIUCOM (*(REG32_PTR_T)(0x38200004)) /* Command and status register */ -#define MIUAREF (*(REG32_PTR_T)(0x38200008)) /* Auto-refresh control register */ -#define MIUMRS (*(REG32_PTR_T)(0x3820000C)) /* SDRAM Mode Register Set Value Register */ -#define MIUSDPARA (*(REG32_PTR_T)(0x38200010)) /* SDRAM parameter register */ +#define MIUCON (*(REG32_PTR_T)(MIU_BASE)) /* External Memory configuration register */ +#define MIUCOM (*(REG32_PTR_T)(MIU_BASE + 0x04)) /* Command and status register */ +#define MIUAREF (*(REG32_PTR_T)(MIU_BASE + 0x08)) /* Auto-refresh control register */ +#define MIUMRS (*(REG32_PTR_T)(MIU_BASE + 0x0C)) /* SDRAM Mode Register Set Value Register */ +#define MIUSDPARA (*(REG32_PTR_T)(MIU_BASE + 0x10)) /* SDRAM parameter register */ /* DDR */ -#define MEMCONF (*(REG32_PTR_T)(0x38200020)) /* External Memory configuration register */ -#define USRCMD (*(REG32_PTR_T)(0x38200024)) /* Command and Status register */ -#define AREF (*(REG32_PTR_T)(0x38200028)) /* Auto-refresh control register */ -#define MRS (*(REG32_PTR_T)(0x3820002C)) /* DRAM mode register set value register */ -#define DPARAM (*(REG32_PTR_T)(0x38200030)) /* DRAM parameter register (Unit of ‘tXXX’ : tCK */ -#define SMEMCONF (*(REG32_PTR_T)(0x38200034)) /* Static memory mode register set value register */ -#define MIUS01PARA (*(REG32_PTR_T)(0x38200038)) /* SRAM0, SRAM1 static memory parameter register (In S5L8700, SRAM0 is Nor Flash) */ -#define MIUS23PARA (*(REG32_PTR_T)(0x3820003C)) /* SRAM2 and SRAM3 static memory parameter register */ - -#define MIUORG (*(REG32_PTR_T)(0x38200040)) /* SDR/DDR selection */ -#define MIUDLYDQS (*(REG32_PTR_T)(0x38200044)) /* DQS/DQS-rst delay parameter */ -#define MIUDLYCLK (*(REG32_PTR_T)(0x38200048)) /* SDR/DDR Clock delay parameter */ -#define MIU_DSS_SEL_B (*(REG32_PTR_T)(0x3820004C)) /* SSTL2 Drive Strength parameter for Bi-direction signal */ -#define MIU_DSS_SEL_O (*(REG32_PTR_T)(0x38200050)) /* SSTL2 Drive Strength parameter for Output signal */ -#define MIU_DSS_SEL_C (*(REG32_PTR_T)(0x38200054)) /* SSTL2 Drive Strength parameter for Clock signal */ -#define PAD_DSS_SEL_NOR (*(REG32_PTR_T)(0x38200058)) /* Wide range I/O Drive Strength parameter for NOR interface */ -#define PAD_DSS_SEL_ATA (*(REG32_PTR_T)(0x3820005C)) /* Wide range I/O Drive Strength parameter for ATA interface */ -#define SSTL2_PAD_ON (*(REG32_PTR_T)(0x38200060)) /* SSTL2 pad ON/OFF select */ -#elif CONFIG_CPU==S5L8702 -#define MIU_BASE (0x38100000) -#define MIU_REG(off) (*((REG32_PTR_T)(MIU_BASE + (off)))) -/* following registers are similar to s5l8700x */ -#define MIUCON (*((REG32_PTR_T)(0x38100000))) -#define MIUCOM (*((REG32_PTR_T)(0x38100004))) -#define MIUAREF (*((REG32_PTR_T)(0x38100008))) -#define MIUMRS (*((REG32_PTR_T)(0x3810000C))) -#define MIUSDPARA (*((REG32_PTR_T)(0x38100010))) -#endif +#define MEMCONF (*(REG32_PTR_T)(MIU_BASE + 0x20)) /* External Memory configuration register */ +#define USRCMD (*(REG32_PTR_T)(MIU_BASE + 0x24)) /* Command and Status register */ +#define AREF (*(REG32_PTR_T)(MIU_BASE + 0x28)) /* Auto-refresh control register */ +#define MRS (*(REG32_PTR_T)(MIU_BASE + 0x2C)) /* DRAM mode register set value register */ +#define DPARAM (*(REG32_PTR_T)(MIU_BASE + 0x30)) /* DRAM parameter register (Unit of ‘tXXX’ : tCK */ +#define SMEMCONF (*(REG32_PTR_T)(MIU_BASE + 0x34)) /* Static memory mode register set value register */ +#define MIUS01PARA (*(REG32_PTR_T)(MIU_BASE + 0x38)) /* SRAM0, SRAM1 static memory parameter register (In S5L8700, SRAM0 is Nor Flash) */ +#define MIUS23PARA (*(REG32_PTR_T)(MIU_BASE + 0x3C)) /* SRAM2 and SRAM3 static memory parameter register */ + +#define MIUORG (*(REG32_PTR_T)(MIU_BASE + 0x40)) /* SDR/DDR selection */ +#define MIUDLYDQS (*(REG32_PTR_T)(MIU_BASE + 0x44)) /* DQS/DQS-rst delay parameter */ +#define MIUDLYCLK (*(REG32_PTR_T)(MIU_BASE + 0x48)) /* SDR/DDR Clock delay parameter */ +#define MIU_DSS_SEL_B (*(REG32_PTR_T)(MIU_BASE + 0x4C)) /* SSTL2 Drive Strength parameter for Bi-direction signal */ +#define MIU_DSS_SEL_O (*(REG32_PTR_T)(MIU_BASE + 0x50)) /* SSTL2 Drive Strength parameter for Output signal */ +#define MIU_DSS_SEL_C (*(REG32_PTR_T)(MIU_BASE + 0x54)) /* SSTL2 Drive Strength parameter for Clock signal */ +#define PAD_DSS_SEL_NOR (*(REG32_PTR_T)(MIU_BASE + 0x58)) /* Wide range I/O Drive Strength parameter for NOR interface */ +#define PAD_DSS_SEL_ATA (*(REG32_PTR_T)(MIU_BASE + 0x5C)) /* Wide range I/O Drive Strength parameter for ATA interface */ +#define SSTL2_PAD_ON (*(REG32_PTR_T)(MIU_BASE + 0x60)) /* SSTL2 pad ON/OFF select */ /* 08. IODMA CONTROLLER */ -#define DMABASE0 (*(REG32_PTR_T)(0x38400000)) /* Base address register for channel 0 */ -#define DMACON0 (*(REG32_PTR_T)(0x38400004)) /* Configuration register for channel 0 */ -#define DMATCNT0 (*(REG32_PTR_T)(0x38400008)) /* Transfer count register for channel 0 */ -#define DMACADDR0 (*(REG32_PTR_T)(0x3840000C)) /* Current memory address register for channel 0 */ -#define DMACTCNT0 (*(REG32_PTR_T)(0x38400010)) /* Current transfer count register for channel 0 */ -#define DMACOM0 (*(REG32_PTR_T)(0x38400014)) /* Channel 0 command register */ -#define DMANOFF0 (*(REG32_PTR_T)(0x38400018)) /* Channel 0 offset2 register */ -#define DMABASE1 (*(REG32_PTR_T)(0x38400020)) /* Base address register for channel 1 */ -#define DMACON1 (*(REG32_PTR_T)(0x38400024)) /* Configuration register for channel 1 */ -#define DMATCNT1 (*(REG32_PTR_T)(0x38400028)) /* Transfer count register for channel 1 */ -#define DMACADDR1 (*(REG32_PTR_T)(0x3840002C)) /* Current memory address register for channel 1 */ -#define DMACTCNT1 (*(REG32_PTR_T)(0x38400030)) /* Current transfer count register for channel 1 */ -#define DMACOM1 (*(REG32_PTR_T)(0x38400034)) /* Channel 1 command register */ -#define DMABASE2 (*(REG32_PTR_T)(0x38400040)) /* Base address register for channel 2 */ -#define DMACON2 (*(REG32_PTR_T)(0x38400044)) /* Configuration register for channel 2 */ -#define DMATCNT2 (*(REG32_PTR_T)(0x38400048)) /* Transfer count register for channel 2 */ -#define DMACADDR2 (*(REG32_PTR_T)(0x3840004C)) /* Current memory address register for channel 2 */ -#define DMACTCNT2 (*(REG32_PTR_T)(0x38400050)) /* Current transfer count register for channel 2 */ -#define DMACOM2 (*(REG32_PTR_T)(0x38400054)) /* Channel 2 command register */ -#define DMABASE3 (*(REG32_PTR_T)(0x38400060)) /* Base address register for channel 3 */ -#define DMACON3 (*(REG32_PTR_T)(0x38400064)) /* Configuration register for channel 3 */ -#define DMATCNT3 (*(REG32_PTR_T)(0x38400068)) /* Transfer count register for channel 3 */ -#define DMACADDR3 (*(REG32_PTR_T)(0x3840006C)) /* Current memory address register for channel 3 */ -#define DMACTCNT3 (*(REG32_PTR_T)(0x38400070)) /* Current transfer count register for channel 3 */ -#define DMACOM3 (*(REG32_PTR_T)(0x38400074)) /* Channel 3 command register */ +#define DMA_BASE 0x38400000 + +#define DMABASE0 (*(REG32_PTR_T)(DMA_BASE)) /* Base address register for channel 0 */ +#define DMACON0 (*(REG32_PTR_T)(DMA_BASE + 0x04)) /* Configuration register for channel 0 */ +#define DMATCNT0 (*(REG32_PTR_T)(DMA_BASE + 0x08)) /* Transfer count register for channel 0 */ +#define DMACADDR0 (*(REG32_PTR_T)(DMA_BASE + 0x0C)) /* Current memory address register for channel 0 */ +#define DMACTCNT0 (*(REG32_PTR_T)(DMA_BASE + 0x10)) /* Current transfer count register for channel 0 */ +#define DMACOM0 (*(REG32_PTR_T)(DMA_BASE + 0x14)) /* Channel 0 command register */ +#define DMANOFF0 (*(REG32_PTR_T)(DMA_BASE + 0x18)) /* Channel 0 offset2 register */ +#define DMABASE1 (*(REG32_PTR_T)(DMA_BASE + 0x20)) /* Base address register for channel 1 */ +#define DMACON1 (*(REG32_PTR_T)(DMA_BASE + 0x24)) /* Configuration register for channel 1 */ +#define DMATCNT1 (*(REG32_PTR_T)(DMA_BASE + 0x28)) /* Transfer count register for channel 1 */ +#define DMACADDR1 (*(REG32_PTR_T)(DMA_BASE + 0x2C)) /* Current memory address register for channel 1 */ +#define DMACTCNT1 (*(REG32_PTR_T)(DMA_BASE + 0x30)) /* Current transfer count register for channel 1 */ +#define DMACOM1 (*(REG32_PTR_T)(DMA_BASE + 0x34)) /* Channel 1 command register */ +#define DMABASE2 (*(REG32_PTR_T)(DMA_BASE + 0x40)) /* Base address register for channel 2 */ +#define DMACON2 (*(REG32_PTR_T)(DMA_BASE + 0x44)) /* Configuration register for channel 2 */ +#define DMATCNT2 (*(REG32_PTR_T)(DMA_BASE + 0x48)) /* Transfer count register for channel 2 */ +#define DMACADDR2 (*(REG32_PTR_T)(DMA_BASE + 0x4C)) /* Current memory address register for channel 2 */ +#define DMACTCNT2 (*(REG32_PTR_T)(DMA_BASE + 0x50)) /* Current transfer count register for channel 2 */ +#define DMACOM2 (*(REG32_PTR_T)(DMA_BASE + 0x54)) /* Channel 2 command register */ +#define DMABASE3 (*(REG32_PTR_T)(DMA_BASE + 0x60)) /* Base address register for channel 3 */ +#define DMACON3 (*(REG32_PTR_T)(DMA_BASE + 0x64)) /* Configuration register for channel 3 */ +#define DMATCNT3 (*(REG32_PTR_T)(DMA_BASE + 0x68)) /* Transfer count register for channel 3 */ +#define DMACADDR3 (*(REG32_PTR_T)(DMA_BASE + 0x6C)) /* Current memory address register for channel 3 */ +#define DMACTCNT3 (*(REG32_PTR_T)(DMA_BASE + 0x70)) /* Current transfer count register for channel 3 */ +#define DMACOM3 (*(REG32_PTR_T)(DMA_BASE + 0x74)) /* Channel 3 command register */ #if CONFIG_CPU==S5L8700 -#define DMAALLST (*(REG32_PTR_T)(0x38400100)) /* All channel status register */ +#define DMAALLST (*(REG32_PTR_T)(DMA_BASE + 0x100)) /* All channel status register */ #elif CONFIG_CPU==S5L8701 -#define DMABASE4 (*(REG32_PTR_T)(0x38400080)) /* Base address register for channel 4 */ -#define DMACON4 (*(REG32_PTR_T)(0x38400084)) /* Configuration register for channel 4 */ -#define DMATCNT4 (*(REG32_PTR_T)(0x38400088)) /* Transfer count register for channel 4 */ -#define DMACADDR4 (*(REG32_PTR_T)(0x3840008C)) /* Current memory address register for channel 4 */ -#define DMACTCNT4 (*(REG32_PTR_T)(0x38400090)) /* Current transfer count register for channel 4 */ -#define DMACOM4 (*(REG32_PTR_T)(0x38400094)) /* Channel 4 command register */ -#define DMABASE5 (*(REG32_PTR_T)(0x384000A0)) /* Base address register for channel 5 */ -#define DMACON5 (*(REG32_PTR_T)(0x384000A4)) /* Configuration register for channel 5 */ -#define DMATCNT5 (*(REG32_PTR_T)(0x384000A8)) /* Transfer count register for channel 5 */ -#define DMACADDR5 (*(REG32_PTR_T)(0x384000AC)) /* Current memory address register for channel 5 */ -#define DMACTCNT5 (*(REG32_PTR_T)(0x384000B0)) /* Current transfer count register for channel 5 */ -#define DMACOM5 (*(REG32_PTR_T)(0x384000B4)) /* Channel 5 command register */ -#define DMABASE6 (*(REG32_PTR_T)(0x384000C0)) /* Base address register for channel 6 */ -#define DMACON6 (*(REG32_PTR_T)(0x384000C4)) /* Configuration register for channel 6 */ -#define DMATCNT6 (*(REG32_PTR_T)(0x384000C8)) /* Transfer count register for channel 6 */ -#define DMACADDR6 (*(REG32_PTR_T)(0x384000CC)) /* Current memory address register for channel 6 */ -#define DMACTCNT6 (*(REG32_PTR_T)(0x384000D0)) /* Current transfer count register for channel 6 */ -#define DMACOM6 (*(REG32_PTR_T)(0x384000D4)) /* Channel 6 command register */ -#define DMABASE7 (*(REG32_PTR_T)(0x384000E0)) /* Base address register for channel 7 */ -#define DMACON7 (*(REG32_PTR_T)(0x384000E4)) /* Configuration register for channel 7 */ -#define DMATCNT7 (*(REG32_PTR_T)(0x384000E8)) /* Transfer count register for channel 7 */ -#define DMACADDR7 (*(REG32_PTR_T)(0x384000EC)) /* Current memory address register for channel 7 */ -#define DMACTCNT7 (*(REG32_PTR_T)(0x384000F0)) /* Current transfer count register for channel 7 */ -#define DMACOM7 (*(REG32_PTR_T)(0x384000F4)) /* Channel 7 command register */ -#define DMABASE8 (*(REG32_PTR_T)(0x38400100)) /* Base address register for channel 8 */ -#define DMACON8 (*(REG32_PTR_T)(0x38400104)) /* Configuration register for channel 8 */ -#define DMATCNT8 (*(REG32_PTR_T)(0x38400108)) /* Transfer count register for channel 8 */ -#define DMACADDR8 (*(REG32_PTR_T)(0x3840010C)) /* Current memory address register for channel 8 */ -#define DMACTCNT8 (*(REG32_PTR_T)(0x38400110)) /* Current transfer count register for channel 8 */ -#define DMACOM8 (*(REG32_PTR_T)(0x38400114)) /* Channel 8 command register */ -#define DMAALLST (*(REG32_PTR_T)(0x38400180)) /* All channel status register */ +#define DMABASE4 (*(REG32_PTR_T)(DMA_BASE + 0x80)) /* Base address register for channel 4 */ +#define DMACON4 (*(REG32_PTR_T)(DMA_BASE + 0x84)) /* Configuration register for channel 4 */ +#define DMATCNT4 (*(REG32_PTR_T)(DMA_BASE + 0x88)) /* Transfer count register for channel 4 */ +#define DMACADDR4 (*(REG32_PTR_T)(DMA_BASE + 0x8C)) /* Current memory address register for channel 4 */ +#define DMACTCNT4 (*(REG32_PTR_T)(DMA_BASE + 0x90)) /* Current transfer count register for channel 4 */ +#define DMACOM4 (*(REG32_PTR_T)(DMA_BASE + 0x94)) /* Channel 4 command register */ +#define DMABASE5 (*(REG32_PTR_T)(DMA_BASE + 0xA0)) /* Base address register for channel 5 */ +#define DMACON5 (*(REG32_PTR_T)(DMA_BASE + 0xA4)) /* Configuration register for channel 5 */ +#define DMATCNT5 (*(REG32_PTR_T)(DMA_BASE + 0xA8)) /* Transfer count register for channel 5 */ +#define DMACADDR5 (*(REG32_PTR_T)(DMA_BASE + 0xAC)) /* Current memory address register for channel 5 */ +#define DMACTCNT5 (*(REG32_PTR_T)(DMA_BASE + 0xB0)) /* Current transfer count register for channel 5 */ +#define DMACOM5 (*(REG32_PTR_T)(DMA_BASE + 0xB4)) /* Channel 5 command register */ +#define DMABASE6 (*(REG32_PTR_T)(DMA_BASE + 0xC0)) /* Base address register for channel 6 */ +#define DMACON6 (*(REG32_PTR_T)(DMA_BASE + 0xC4)) /* Configuration register for channel 6 */ +#define DMATCNT6 (*(REG32_PTR_T)(DMA_BASE + 0xC8)) /* Transfer count register for channel 6 */ +#define DMACADDR6 (*(REG32_PTR_T)(DMA_BASE + 0xCC)) /* Current memory address register for channel 6 */ +#define DMACTCNT6 (*(REG32_PTR_T)(DMA_BASE + 0xD0)) /* Current transfer count register for channel 6 */ +#define DMACOM6 (*(REG32_PTR_T)(DMA_BASE + 0xD4)) /* Channel 6 command register */ +#define DMABASE7 (*(REG32_PTR_T)(DMA_BASE + 0xE0)) /* Base address register for channel 7 */ +#define DMACON7 (*(REG32_PTR_T)(DMA_BASE + 0xE4)) /* Configuration register for channel 7 */ +#define DMATCNT7 (*(REG32_PTR_T)(DMA_BASE + 0xE8)) /* Transfer count register for channel 7 */ +#define DMACADDR7 (*(REG32_PTR_T)(DMA_BASE + 0xEC)) /* Current memory address register for channel 7 */ +#define DMACTCNT7 (*(REG32_PTR_T)(DMA_BASE + 0xF0)) /* Current transfer count register for channel 7 */ +#define DMACOM7 (*(REG32_PTR_T)(DMA_BASE + 0xF4)) /* Channel 7 command register */ +#define DMABASE8 (*(REG32_PTR_T)(DMA_BASE + 0x100)) /* Base address register for channel 8 */ +#define DMACON8 (*(REG32_PTR_T)(DMA_BASE + 0x104)) /* Configuration register for channel 8 */ +#define DMATCNT8 (*(REG32_PTR_T)(DMA_BASE + 0x108)) /* Transfer count register for channel 8 */ +#define DMACADDR8 (*(REG32_PTR_T)(DMA_BASE + 0x10C)) /* Current memory address register for channel 8 */ +#define DMACTCNT8 (*(REG32_PTR_T)(DMA_BASE + 0x110)) /* Current transfer count register for channel 8 */ +#define DMACOM8 (*(REG32_PTR_T)(DMA_BASE + 0x114)) /* Channel 8 command register */ +#define DMAALLST (*(REG32_PTR_T)(DMA_BASE + 0x180)) /* All channel status register */ #endif #define DMACON_DEVICE_SHIFT 30 @@ -397,61 +407,68 @@ #define DMAALLST_CHAN3_MASK (0xF << 12) /* 10. REAL TIMER CLOCK (RTC) */ -#define RTCCON (*(REG32_PTR_T)(0x3D200000)) /* RTC Control Register */ -#define RTCRST (*(REG32_PTR_T)(0x3D200004)) /* RTC Round Reset Register */ -#define RTCALM (*(REG32_PTR_T)(0x3D200008)) /* RTC Alarm Control Register */ -#define ALMSEC (*(REG32_PTR_T)(0x3D20000C)) /* Alarm Second Data Register */ -#define ALMMIN (*(REG32_PTR_T)(0x3D200010)) /* Alarm Minute Data Register */ -#define ALMHOUR (*(REG32_PTR_T)(0x3D200014)) /* Alarm Hour Data Register */ -#define ALMDATE (*(REG32_PTR_T)(0x3D200018)) /* Alarm Date Data Register */ -#define ALMDAY (*(REG32_PTR_T)(0x3D20001C)) /* Alarm Day of Week Data Register */ -#define ALMMON (*(REG32_PTR_T)(0x3D200020)) /* Alarm Month Data Register */ -#define ALMYEAR (*(REG32_PTR_T)(0x3D200024)) /* Alarm Year Data Register */ -#define BCDSEC (*(REG32_PTR_T)(0x3D200028)) /* BCD Second Register */ -#define BCDMIN (*(REG32_PTR_T)(0x3D20002C)) /* BCD Minute Register */ -#define BCDHOUR (*(REG32_PTR_T)(0x3D200030)) /* BCD Hour Register */ -#define BCDDATE (*(REG32_PTR_T)(0x3D200034)) /* BCD Date Register */ -#define BCDDAY (*(REG32_PTR_T)(0x3D200038)) /* BCD Day of Week Register */ -#define BCDMON (*(REG32_PTR_T)(0x3D20003C)) /* BCD Month Register */ -#define BCDYEAR (*(REG32_PTR_T)(0x3D200040)) /* BCD Year Register */ -#define RTCIM (*(REG32_PTR_T)(0x3D200044)) /* RTC Interrupt Mode Register */ -#define RTCPEND (*(REG32_PTR_T)(0x3D200048)) /* RTC Interrupt Pending Register */ +#define RTC_BASE 0x3D200000 + +#define RTCCON (*(REG32_PTR_T)(RTC_BASE)) /* RTC Control Register */ +#define RTCRST (*(REG32_PTR_T)(RTC_BASE + 0x04)) /* RTC Round Reset Register */ +#define RTCALM (*(REG32_PTR_T)(RTC_BASE + 0x08)) /* RTC Alarm Control Register */ +#define ALMSEC (*(REG32_PTR_T)(RTC_BASE + 0x0C)) /* Alarm Second Data Register */ +#define ALMMIN (*(REG32_PTR_T)(RTC_BASE + 0x10)) /* Alarm Minute Data Register */ +#define ALMHOUR (*(REG32_PTR_T)(RTC_BASE + 0x14)) /* Alarm Hour Data Register */ +#define ALMDATE (*(REG32_PTR_T)(RTC_BASE + 0x18)) /* Alarm Date Data Register */ +#define ALMDAY (*(REG32_PTR_T)(RTC_BASE + 0x1C)) /* Alarm Day of Week Data Register */ +#define ALMMON (*(REG32_PTR_T)(RTC_BASE + 0x20)) /* Alarm Month Data Register */ +#define ALMYEAR (*(REG32_PTR_T)(RTC_BASE + 0x24)) /* Alarm Year Data Register */ +#define BCDSEC (*(REG32_PTR_T)(RTC_BASE + 0x28)) /* BCD Second Register */ +#define BCDMIN (*(REG32_PTR_T)(RTC_BASE + 0x2C)) /* BCD Minute Register */ +#define BCDHOUR (*(REG32_PTR_T)(RTC_BASE + 0x30)) /* BCD Hour Register */ +#define BCDDATE (*(REG32_PTR_T)(RTC_BASE + 0x34)) /* BCD Date Register */ +#define BCDDAY (*(REG32_PTR_T)(RTC_BASE + 0x38)) /* BCD Day of Week Register */ +#define BCDMON (*(REG32_PTR_T)(RTC_BASE + 0x3C)) /* BCD Month Register */ +#define BCDYEAR (*(REG32_PTR_T)(RTC_BASE + 0x40)) /* BCD Year Register */ +#define RTCIM (*(REG32_PTR_T)(RTC_BASE + 0x44)) /* RTC Interrupt Mode Register */ +#define RTCPEND (*(REG32_PTR_T)(RTC_BASE + 0x48)) /* RTC Interrupt Pending Register */ /* 09. WATCHDOG TIMER*/ -#define WDTCON (*(REG32_PTR_T)(0x3C800000)) /* Control Register */ -#define WDTCNT (*(REG32_PTR_T)(0x3C800004)) /* 11-bits internal counter */ +#define WDT_BASE 0x3C800000 + +#define WDTCON (*(REG32_PTR_T)(WDT_BASE)) /* Control Register */ +#define WDTCNT (*(REG32_PTR_T)(WDT_BASE + 0x04)) /* 11-bits internal counter */ /* 11. 16 BIT TIMER */ -#define TACON (*(REG32_PTR_T)(0x3C700000)) /* Control Register for timer A */ -#define TACMD (*(REG32_PTR_T)(0x3C700004)) /* Command Register for timer A */ -#define TADATA0 (*(REG32_PTR_T)(0x3C700008)) /* Data0 Register */ -#define TADATA1 (*(REG32_PTR_T)(0x3C70000C)) /* Data1 Register */ -#define TAPRE (*(REG32_PTR_T)(0x3C700010)) /* Pre-scale register */ -#define TACNT (*(REG32_PTR_T)(0x3C700014)) /* Counter register */ -#define TBCON (*(REG32_PTR_T)(0x3C700020)) /* Control Register for timer B */ -#define TBCMD (*(REG32_PTR_T)(0x3C700024)) /* Command Register for timer B */ -#define TBDATA0 (*(REG32_PTR_T)(0x3C700028)) /* Data0 Register */ -#define TBDATA1 (*(REG32_PTR_T)(0x3C70002C)) /* Data1 Register */ -#define TBPRE (*(REG32_PTR_T)(0x3C700030)) /* Pre-scale register */ -#define TBCNT (*(REG32_PTR_T)(0x3C700034)) /* Counter register */ -#define TCCON (*(REG32_PTR_T)(0x3C700040)) /* Control Register for timer C */ -#define TCCMD (*(REG32_PTR_T)(0x3C700044)) /* Command Register for timer C */ -#define TCDATA0 (*(REG32_PTR_T)(0x3C700048)) /* Data0 Register */ -#define TCDATA1 (*(REG32_PTR_T)(0x3C70004C)) /* Data1 Register */ -#define TCPRE (*(REG32_PTR_T)(0x3C700050)) /* Pre-scale register */ -#define TCCNT (*(REG32_PTR_T)(0x3C700054)) /* Counter register */ -#define TDCON (*(REG32_PTR_T)(0x3C700060)) /* Control Register for timer D */ -#define TDCMD (*(REG32_PTR_T)(0x3C700064)) /* Command Register for timer D */ -#define TDDATA0 (*(REG32_PTR_T)(0x3C700068)) /* Data0 Register */ -#define TDDATA1 (*(REG32_PTR_T)(0x3C70006C)) /* Data1 Register */ -#define TDPRE (*(REG32_PTR_T)(0x3C700070)) /* Pre-scale register */ -#define TDCNT (*(REG32_PTR_T)(0x3C700074)) /* Counter register */ +#define TIMER_BASE 0x3C700000 + +#define TACON (*(REG32_PTR_T)(TIMER_BASE)) /* Control Register for timer A */ +#define TACMD (*(REG32_PTR_T)(TIMER_BASE + 0x04)) /* Command Register for timer A */ +#define TADATA0 (*(REG32_PTR_T)(TIMER_BASE + 0x08)) /* Data0 Register */ +#define TADATA1 (*(REG32_PTR_T)(TIMER_BASE + 0x0C)) /* Data1 Register */ +#define TAPRE (*(REG32_PTR_T)(TIMER_BASE + 0x10)) /* Pre-scale register */ +#define TACNT (*(REG32_PTR_T)(TIMER_BASE + 0x14)) /* Counter register */ +#define TBCON (*(REG32_PTR_T)(TIMER_BASE + 0x20)) /* Control Register for timer B */ +#define TBCMD (*(REG32_PTR_T)(TIMER_BASE + 0x24)) /* Command Register for timer B */ +#define TBDATA0 (*(REG32_PTR_T)(TIMER_BASE + 0x28)) /* Data0 Register */ +#define TBDATA1 (*(REG32_PTR_T)(TIMER_BASE + 0x2C)) /* Data1 Register */ +#define TBPRE (*(REG32_PTR_T)(TIMER_BASE + 0x30)) /* Pre-scale register */ +#define TBCNT (*(REG32_PTR_T)(TIMER_BASE + 0x34)) /* Counter register */ +#define TCCON (*(REG32_PTR_T)(TIMER_BASE + 0x40)) /* Control Register for timer C */ +#define TCCMD (*(REG32_PTR_T)(TIMER_BASE + 0x44)) /* Command Register for timer C */ +#define TCDATA0 (*(REG32_PTR_T)(TIMER_BASE + 0x48)) /* Data0 Register */ +#define TCDATA1 (*(REG32_PTR_T)(TIMER_BASE + 0x4C)) /* Data1 Register */ +#define TCPRE (*(REG32_PTR_T)(TIMER_BASE + 0x50)) /* Pre-scale register */ +#define TCCNT (*(REG32_PTR_T)(TIMER_BASE + 0x54)) /* Counter register */ +#define TDCON (*(REG32_PTR_T)(TIMER_BASE + 0x60)) /* Control Register for timer D */ +#define TDCMD (*(REG32_PTR_T)(TIMER_BASE + 0x64)) /* Command Register for timer D */ +#define TDDATA0 (*(REG32_PTR_T)(TIMER_BASE + 0x68)) /* Data0 Register */ +#define TDDATA1 (*(REG32_PTR_T)(TIMER_BASE + 0x6C)) /* Data1 Register */ +#define TDPRE (*(REG32_PTR_T)(TIMER_BASE + 0x70)) /* Pre-scale register */ +#define TDCNT (*(REG32_PTR_T)(TIMER_BASE + 0x74)) /* Counter register */ #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 #define TIMER_FREQ (1843200 * 4 * 26 / 1 / 4) /* 47923200 Hz */ -#define FIVE_USEC_TIMER (((uint64_t)(*(REG32_PTR_T)(0x3C700080)) << 32) \ - | (*(REG32_PTR_T)(0x3C700084))) /* 64bit 5usec timer */ +#define TREG_80 (*(REG32_PTR_T)(TIMER_BASE + 0x80)) +#define TREG_84 (*(REG32_PTR_T)(TIMER_BASE + 0x84)) +#define FIVE_USEC_TIMER (((uint64_t)TREG_80 << 32) | TREG_84) /* 64bit 5usec timer */ #define USEC_TIMER (FIVE_USEC_TIMER * 5) /* usecs */ #elif CONFIG_CPU==S5L8702 /* 16/32-bit timers: @@ -482,31 +499,32 @@ */ #define TIMER_FREQ 12000000 /* ECLK */ -#define TECON (*((REG32_PTR_T)(0x3C7000A0))) -#define TECMD (*((REG32_PTR_T)(0x3C7000A4))) -#define TEDATA0 (*((REG32_PTR_T)(0x3C7000A8))) -#define TEDATA1 (*((REG32_PTR_T)(0x3C7000AC))) -#define TEPRE (*((REG32_PTR_T)(0x3C7000B0))) -#define TECNT (*((REG32_PTR_T)(0x3C7000B4))) -#define TFCON (*((REG32_PTR_T)(0x3C7000C0))) -#define TFCMD (*((REG32_PTR_T)(0x3C7000C4))) -#define TFDATA0 (*((REG32_PTR_T)(0x3C7000C8))) -#define TFDATA1 (*((REG32_PTR_T)(0x3C7000CC))) -#define TFPRE (*((REG32_PTR_T)(0x3C7000D0))) -#define TFCNT (*((REG32_PTR_T)(0x3C7000D4))) -#define TGCON (*((REG32_PTR_T)(0x3C7000E0))) -#define TGCMD (*((REG32_PTR_T)(0x3C7000E4))) -#define TGDATA0 (*((REG32_PTR_T)(0x3C7000E8))) -#define TGDATA1 (*((REG32_PTR_T)(0x3C7000EC))) -#define TGPRE (*((REG32_PTR_T)(0x3C7000F0))) -#define TGCNT (*((REG32_PTR_T)(0x3C7000F4))) -#define THCON (*((REG32_PTR_T)(0x3C700100))) -#define THCMD (*((REG32_PTR_T)(0x3C700104))) -#define THDATA0 (*((REG32_PTR_T)(0x3C700108))) -#define THDATA1 (*((REG32_PTR_T)(0x3C70010C))) -#define THPRE (*((REG32_PTR_T)(0x3C700110))) -#define THCNT (*((REG32_PTR_T)(0x3C700114))) -#define TSTAT (*((REG32_PTR_T)(0x3C700118))) +#define TECON (*((REG32_PTR_T)(TIMER_BASE + 0xA0))) +#define TECMD (*((REG32_PTR_T)(TIMER_BASE + 0xA4))) +#define TEDATA0 (*((REG32_PTR_T)(TIMER_BASE + 0xA8))) +#define TEDATA1 (*((REG32_PTR_T)(TIMER_BASE + 0xAC))) +#define TEPRE (*((REG32_PTR_T)(TIMER_BASE + 0xB0))) +#define TECNT (*((REG32_PTR_T)(TIMER_BASE + 0xB4))) +#define TFCON (*((REG32_PTR_T)(TIMER_BASE + 0xC0))) +#define TFCMD (*((REG32_PTR_T)(TIMER_BASE + 0xC4))) +#define TFDATA0 (*((REG32_PTR_T)(TIMER_BASE + 0xC8))) +#define TFDATA1 (*((REG32_PTR_T)(TIMER_BASE + 0xCC))) +#define TFPRE (*((REG32_PTR_T)(TIMER_BASE + 0xD0))) +#define TFCNT (*((REG32_PTR_T)(TIMER_BASE + 0xD4))) +#define TGCON (*((REG32_PTR_T)(TIMER_BASE + 0xE0))) +#define TGCMD (*((REG32_PTR_T)(TIMER_BASE + 0xE4))) +#define TGDATA0 (*((REG32_PTR_T)(TIMER_BASE + 0xE8))) +#define TGDATA1 (*((REG32_PTR_T)(TIMER_BASE + 0xEC))) +#define TGPRE (*((REG32_PTR_T)(TIMER_BASE + 0xF0))) +#define TGCNT (*((REG32_PTR_T)(TIMER_BASE + 0xF4))) +#define THCON (*((REG32_PTR_T)(TIMER_BASE + 0x100))) +#define THCMD (*((REG32_PTR_T)(TIMER_BASE + 0x104))) +#define THDATA0 (*((REG32_PTR_T)(TIMER_BASE + 0x108))) +#define THDATA1 (*((REG32_PTR_T)(TIMER_BASE + 0x10C))) +#define THPRE (*((REG32_PTR_T)(TIMER_BASE + 0x110))) +#define THCNT (*((REG32_PTR_T)(TIMER_BASE + 0x114))) +#define TSTAT (*((REG32_PTR_T)(TIMER_BASE + 0x118))) + #define USEC_TIMER TECNT #endif @@ -588,43 +606,35 @@ /* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */ #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 -#define SDCI_CTRL (*(REG32_PTR_T)(0x3C300000)) /* Control Register */ -#define SDCI_DCTRL (*(REG32_PTR_T)(0x3C300004)) /* Data Control Register */ -#define SDCI_CMD (*(REG32_PTR_T)(0x3C300008)) /* Command Register */ -#define SDCI_ARGU (*(REG32_PTR_T)(0x3C30000C)) /* Argument Register */ -#define SDCI_STATE (*(REG32_PTR_T)(0x3C300010)) /* State Register */ -#define SDCI_STAC (*(REG32_PTR_T)(0x3C300014)) /* Status Clear Register */ -#define SDCI_DSTA (*(REG32_PTR_T)(0x3C300018)) /* Data Status Register */ -#define SDCI_FSTA (*(REG32_PTR_T)(0x3C30001C)) /* FIFO Status Register */ -#define SDCI_RESP0 (*(REG32_PTR_T)(0x3C300020)) /* Response0 Register */ -#define SDCI_RESP1 (*(REG32_PTR_T)(0x3C300024)) /* Response1 Register */ -#define SDCI_RESP2 (*(REG32_PTR_T)(0x3C300028)) /* Response2 Register */ -#define SDCI_RESP3 (*(REG32_PTR_T)(0x3C30002C)) /* Response3 Register */ -#define SDCI_CLKDIV (*(REG32_PTR_T)(0x3C300030)) /* Clock Divider Register */ -#define SDIO_CSR (*(REG32_PTR_T)(0x3C300034)) /* SDIO Control & Status Register */ -#define SDIO_IRQ (*(REG32_PTR_T)(0x3C300038)) /* Interrupt Source Register */ +#define SDCI_BASE 0x3C300000 #elif CONFIG_CPU==S5L8702 -#define SDCI_CTRL (*((REG32_PTR_T)(0x38b00000))) -#define SDCI_DCTRL (*((REG32_PTR_T)(0x38b00004))) -#define SDCI_CMD (*((REG32_PTR_T)(0x38b00008))) -#define SDCI_ARGU (*((REG32_PTR_T)(0x38b0000c))) -#define SDCI_STATE (*((REG32_PTR_T)(0x38b00010))) -#define SDCI_STAC (*((REG32_PTR_T)(0x38b00014))) -#define SDCI_DSTA (*((REG32_PTR_T)(0x38b00018))) -#define SDCI_FSTA (*((REG32_PTR_T)(0x38b0001c))) -#define SDCI_RESP0 (*((REG32_PTR_T)(0x38b00020))) -#define SDCI_RESP1 (*((REG32_PTR_T)(0x38b00024))) -#define SDCI_RESP2 (*((REG32_PTR_T)(0x38b00028))) -#define SDCI_RESP3 (*((REG32_PTR_T)(0x38b0002c))) -#define SDCI_CDIV (*((REG32_PTR_T)(0x38b00030))) -#define SDCI_SDIO_CSR (*((REG32_PTR_T)(0x38b00034))) -#define SDCI_IRQ (*((REG32_PTR_T)(0x38b00038))) -#define SDCI_IRQ_MASK (*((REG32_PTR_T)(0x38b0003c))) -#define SDCI_DATA (*((REG32_PTR_T)(0x38b00040))) -#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044))) -#define SDCI_DMASIZE (*((REG32_PTR_T)(0x38b00048))) -#define SDCI_DMACOUNT (*((REG32_PTR_T)(0x38b0004c))) -#define SDCI_RESET (*((REG32_PTR_T)(0x38b0006c))) +#define SDCI_BASE 0x38b00000 +#endif + +#define SDCI_CTRL (*(REG32_PTR_T)(SDCI_BASE)) /* Control Register */ +#define SDCI_DCTRL (*(REG32_PTR_T)(SDCI_BASE + 0x04)) /* Data Control Register */ +#define SDCI_CMD (*(REG32_PTR_T)(SDCI_BASE + 0x08)) /* Command Register */ +#define SDCI_ARGU (*(REG32_PTR_T)(SDCI_BASE + 0x0C)) /* Argument Register */ +#define SDCI_STATE (*(REG32_PTR_T)(SDCI_BASE + 0x10)) /* State Register */ +#define SDCI_STAC (*(REG32_PTR_T)(SDCI_BASE + 0x14)) /* Status Clear Register */ +#define SDCI_DSTA (*(REG32_PTR_T)(SDCI_BASE + 0x18)) /* Data Status Register */ +#define SDCI_FSTA (*(REG32_PTR_T)(SDCI_BASE + 0x1C)) /* FIFO Status Register */ +#define SDCI_RESP0 (*(REG32_PTR_T)(SDCI_BASE + 0x20)) /* Response0 Register */ +#define SDCI_RESP1 (*(REG32_PTR_T)(SDCI_BASE + 0x24)) /* Response1 Register */ +#define SDCI_RESP2 (*(REG32_PTR_T)(SDCI_BASE + 0x28)) /* Response2 Register */ +#define SDCI_RESP3 (*(REG32_PTR_T)(SDCI_BASE + 0x2C)) /* Response3 Register */ +#define SDCI_CLKDIV (*(REG32_PTR_T)(SDCI_BASE + 0x30)) /* Clock Divider Register */ +#define SDIO_CSR (*(REG32_PTR_T)(SDCI_BASE + 0x34)) /* SDIO Control & Status Register */ +#define SDCI_IRQ (*(REG32_PTR_T)(SDCI_BASE + 0x38)) /* Interrupt Source Register */ +#define SDCI_IRQ_MASK (*(REG32_PTR_T)(SDCI_BASE + 0x3c)) + +#if CONFIG_CPU==S5L8702 +#define SDCI_DATA (*(REG32_PTR_T)(SDCI_BASE + 0x40)) +#define SDCI_DMAADDR (*(VOID_PTR_PTR_T)(SDCI_BASE + 0x44)) +#define SDCI_DMASIZE (*(REG32_PTR_T)(SDCI_BASE + 0x48)) +#define SDCI_DMACOUNT (*(REG32_PTR_T)(SDCI_BASE + 0x4c)) +#define SDCI_RESET (*(REG32_PTR_T)(SDCI_BASE + 0x6c)) +#endif #define SDCI_CTRL_SDCIEN BIT(0) #define SDCI_CTRL_CARD_TYPE_MASK BIT(1) @@ -785,58 +795,66 @@ #define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0) #define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1) #define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2) -#endif /* 14. MEMORY STICK HOST CONTROLLER */ -#define MSPRE (*(REG32_PTR_T)(0x3C600000)) /* Prescaler Register */ -#define MSINTEN (*(REG32_PTR_T)(0x3C600004)) /* Interrupt Enable Register */ -#define MSCMD (*(REG32_PTR_T)(0x3C601000)) /* Command Register */ -#define MSFIFO (*(REG32_PTR_T)(0x3C601008)) /* Receive/Transmit Register */ -#define MSPP (*(REG32_PTR_T)(0x3C601010)) /* Parallel Port Control/Data Register */ -#define MSCTRL2 (*(REG32_PTR_T)(0x3C601014)) /* Control Register 2 */ -#define MSACD (*(REG32_PTR_T)(0x3C601018)) /* ACD Command Register */ +#define MS_BASE 0x3C600000 +#define MS_CMD_BASE (MS_BASE + 0x1000) + +#define MSPRE (*(REG32_PTR_T)(MS_BASE)) /* Prescaler Register */ +#define MSINTEN (*(REG32_PTR_T)(MS_BASE + 0x04)) /* Interrupt Enable Register */ +#define MSCMD (*(REG32_PTR_T)(MS_CMD_BASE)) /* Command Register */ +#define MSFIFO (*(REG32_PTR_T)(MS_CMD_BASE + 0x08)) /* Receive/Transmit Register */ +#define MSPP (*(REG32_PTR_T)(MS_CMD_BASE + 0x10)) /* Parallel Port Control/Data Register */ +#define MSCTRL2 (*(REG32_PTR_T)(MS_CMD_BASE + 0x14)) /* Control Register 2 */ +#define MSACD (*(REG32_PTR_T)(MS_CMD_BASE + 0x18)) /* ACD Command Register */ /* 15. SPDIF TRANSMITTER (SPDIFOUT) */ -#define SPDCLKCON (*(REG32_PTR_T)(0x3CB00000)) /* Clock Control Register */ -#define SPDCON (*(REG32_PTR_T)(0x3CB00004)) /* Control Register 0020 */ -#define SPDBSTAS (*(REG32_PTR_T)(0x3CB00008)) /* Burst Status Register */ -#define SPDCSTAS (*(REG32_PTR_T)(0x3CB0000C)) /* Channel Status Register 0x2000 8000 */ -#define SPDDAT (*(REG32_PTR_T)(0x3CB00010)) /* SPDIFOUT Data Buffer */ -#define SPDCNT (*(REG32_PTR_T)(0x3CB00014)) /* Repetition Count Register */ +#define SPD_BASE 0x3CB00000 + +#define SPDCLKCON (*(REG32_PTR_T)(SPD_BASE)) /* Clock Control Register */ +#define SPDCON (*(REG32_PTR_T)(SPD_BASE + 0x04)) /* Control Register 0020 */ +#define SPDBSTAS (*(REG32_PTR_T)(SPD_BASE + 0x08)) /* Burst Status Register */ +#define SPDCSTAS (*(REG32_PTR_T)(SPD_BASE + 0x0C)) /* Channel Status Register 0x2000 8000 */ +#define SPDDAT (*(REG32_PTR_T)(SPD_BASE + 0x10)) /* SPDIFOUT Data Buffer */ +#define SPDCNT (*(REG32_PTR_T)(SPD_BASE + 0x14)) /* Repetition Count Register */ /* 16. REED-SOLOMON ECC CODEC */ -#define ECC_DATA_PTR (*(REG32_PTR_T)(0x39E00004)) /* Data Area Start Pointer */ -#define ECC_SPARE_PTR (*(REG32_PTR_T)(0x39E00008)) /* Spare Area Start Pointer */ -#define ECC_CTRL (*(REG32_PTR_T)(0x39E0000C)) /* ECC Control Register */ -#define ECC_RESULT (*(REG32_PTR_T)(0x39E00010)) /* ECC Result */ -#define ECC_UNK1 (*(REG32_PTR_T)(0x39E00014)) /* No idea what this is, but the OFW uses it on S5L8701 */ -#define ECC_EVAL0 (*(REG32_PTR_T)(0x39E00020)) /* Error Eval0 Poly */ -#define ECC_EVAL1 (*(REG32_PTR_T)(0x39E00024)) /* Error Eval1 Poly */ -#define ECC_LOC0 (*(REG32_PTR_T)(0x39E00028)) /* Error Loc0 Poly */ -#define ECC_LOC1 (*(REG32_PTR_T)(0x39E0002C)) /* Error Loc1 Poly */ -#define ECC_PARITY0 (*(REG32_PTR_T)(0x39E00030)) /* Encode Parity0 Poly */ -#define ECC_PARITY1 (*(REG32_PTR_T)(0x39E00034)) /* Encode Pariyt1 Poly */ -#define ECC_PARITY2 (*(REG32_PTR_T)(0x39E00038)) /* Encode Parity2 Poly */ -#define ECC_INT_CLR (*(REG32_PTR_T)(0x39E00040)) /* Interrupt Clear Register */ -#define ECC_SYND0 (*(REG32_PTR_T)(0x39E00044)) /* Syndrom0 Poly */ -#define ECC_SYND1 (*(REG32_PTR_T)(0x39E00048)) /* Syndrom1 Poly */ -#define ECC_SYND2 (*(REG32_PTR_T)(0x39E0004C)) /* Syndrom2 Poly */ +#define ECC_BASE 0x39E00000 + +#define ECC_DATA_PTR (*(REG32_PTR_T)(ECC_BASE + 0x04)) /* Data Area Start Pointer */ +#define ECC_SPARE_PTR (*(REG32_PTR_T)(ECC_BASE + 0x08)) /* Spare Area Start Pointer */ +#define ECC_CTRL (*(REG32_PTR_T)(ECC_BASE + 0x0C)) /* ECC Control Register */ +#define ECC_RESULT (*(REG32_PTR_T)(ECC_BASE + 0x10)) /* ECC Result */ +#define ECC_UNK1 (*(REG32_PTR_T)(ECC_BASE + 0x14)) /* No idea what this is, but the OFW uses it on S5L8701 */ +#define ECC_EVAL0 (*(REG32_PTR_T)(ECC_BASE + 0x20)) /* Error Eval0 Poly */ +#define ECC_EVAL1 (*(REG32_PTR_T)(ECC_BASE + 0x24)) /* Error Eval1 Poly */ +#define ECC_LOC0 (*(REG32_PTR_T)(ECC_BASE + 0x28)) /* Error Loc0 Poly */ +#define ECC_LOC1 (*(REG32_PTR_T)(ECC_BASE + 0x2C)) /* Error Loc1 Poly */ +#define ECC_PARITY0 (*(REG32_PTR_T)(ECC_BASE + 0x30)) /* Encode Parity0 Poly */ +#define ECC_PARITY1 (*(REG32_PTR_T)(ECC_BASE + 0x34)) /* Encode Pariyt1 Poly */ +#define ECC_PARITY2 (*(REG32_PTR_T)(ECC_BASE + 0x38)) /* Encode Parity2 Poly */ +#define ECC_INT_CLR (*(REG32_PTR_T)(ECC_BASE + 0x40)) /* Interrupt Clear Register */ +#define ECC_SYND0 (*(REG32_PTR_T)(ECC_BASE + 0x44)) /* Syndrom0 Poly */ +#define ECC_SYND1 (*(REG32_PTR_T)(ECC_BASE + 0x48)) /* Syndrom1 Poly */ +#define ECC_SYND2 (*(REG32_PTR_T)(ECC_BASE + 0x4C)) /* Syndrom2 Poly */ #define ECCCTRL_STARTDECODING (1 << 0) #define ECCCTRL_STARTENCODING (1 << 1) #define ECCCTRL_STARTDECNOSYND (1 << 2) /* 17. IIS Tx/Rx INTERFACE */ -#define I2SCLKCON (*(REG32_PTR_T)(0x3CA00000)) /* Clock Control Register */ -#define I2STXCON (*(REG32_PTR_T)(0x3CA00004)) /* Tx configuration Register */ -#define I2STXCOM (*(REG32_PTR_T)(0x3CA00008)) /* Tx command Register */ -#define I2STXDB0 (*(REG32_PTR_T)(0x3CA00010)) /* Tx data buffer */ -#define I2SRXCON (*(REG32_PTR_T)(0x3CA00030)) /* Rx configuration Register */ -#define I2SRXCOM (*(REG32_PTR_T)(0x3CA00034)) /* Rx command Register */ -#define I2SRXDB (*(REG32_PTR_T)(0x3CA00038)) /* Rx data buffer */ -#define I2SSTATUS (*(REG32_PTR_T)(0x3CA0003C)) /* status register */ +#define I2S_BASE 0x3CA00000 + +#define I2SCLKCON (*(REG32_PTR_T)(I2S_BASE)) /* Clock Control Register */ +#define I2STXCON (*(REG32_PTR_T)(I2S_BASE + 0x04)) /* Tx configuration Register */ +#define I2STXCOM (*(REG32_PTR_T)(I2S_BASE + 0x08)) /* Tx command Register */ +#define I2STXDB0 (*(REG32_PTR_T)(I2S_BASE + 0x10)) /* Tx data buffer */ +#define I2SRXCON (*(REG32_PTR_T)(I2S_BASE + 0x30)) /* Rx configuration Register */ +#define I2SRXCOM (*(REG32_PTR_T)(I2S_BASE + 0x34)) /* Rx command Register */ +#define I2SRXDB (*(REG32_PTR_T)(I2S_BASE + 0x38)) /* Rx data buffer */ +#define I2SSTATUS (*(REG32_PTR_T)(I2S_BASE + 0x3C)) /* status register */ #if CONFIG_CPU==S5L8702 -#define I2SCLKDIV (*(REG32_PTR_T)(0x3CA00040)) +#define I2SCLKDIV (*(REG32_PTR_T)(I2S_BASE + 0x40)) #define I2SCLKGATE(i) ((i) == 2 ? CLOCKGATE_I2S2 : \ (i) == 1 ? CLOCKGATE_I2S1 : \ @@ -845,14 +863,13 @@ /* 18. IIC BUS INTERFACE */ #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 -#define IICCON (*(REG32_PTR_T)(0x3C900000)) /* Control Register */ -#define IICSTAT (*(REG32_PTR_T)(0x3C900004)) /* Control/Status Register */ -#define IICADD (*(REG32_PTR_T)(0x3C900008)) /* Bus Address Register */ -#define IICDS (*(REG32_PTR_T)(0x3C90000C)) -#elif CONFIG_CPU==S5L8702 -#define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \ - CLOCKGATE_I2C0) +#define IIC_BASE 0x3C900000 +#define IICCON (*(REG32_PTR_T)(IIC_BASE)) /* Control Register */ +#define IICSTAT (*(REG32_PTR_T)(IIC_BASE + 0x04)) /* Control/Status Register */ +#define IICADD (*(REG32_PTR_T)(IIC_BASE + 0x08)) /* Bus Address Register */ +#define IICDS (*(REG32_PTR_T)(IIC_BASE + 0x0C)) +#elif CONFIG_CPU==S5L8702 /* s5l8702 I2C controller is similar to s5l8700, known differences are: * IICCON[5] is not used in s5l8702. @@ -866,26 +883,32 @@ transmited or received, in Master mode the tx/rx of the next byte starts when it is written as "1". */ +#define IIC_BASE 0x3C600000 + +#define IICCON(bus) (*((REG32_PTR_T)(IIC_BASE + 0x300000 * (bus)))) +#define IICSTAT(bus) (*((REG32_PTR_T)(IIC_BASE + 0x04 + 0x300000 * (bus)))) +#define IICADD(bus) (*((REG32_PTR_T)(IIC_BASE + 0x08 + 0x300000 * (bus)))) +#define IICDS(bus) (*((REG32_PTR_T)(IIC_BASE + 0x0C + 0x300000 * (bus)))) +#define IICUNK10(bus) (*((REG32_PTR_T)(IIC_BASE + 0x10 + 0x300000 * (bus)))) +#define IICUNK14(bus) (*((REG32_PTR_T)(IIC_BASE + 0x14 + 0x300000 * (bus)))) +#define IICUNK18(bus) (*((REG32_PTR_T)(IIC_BASE + 0x18 + 0x300000 * (bus)))) +#define IICSTA2(bus) (*((REG32_PTR_T)(IIC_BASE + 0x20 + 0x300000 * (bus)))) -#define IICCON(bus) (*((REG32_PTR_T)(0x3C600000 + 0x300000 * (bus)))) -#define IICSTAT(bus) (*((REG32_PTR_T)(0x3C600004 + 0x300000 * (bus)))) -#define IICADD(bus) (*((REG32_PTR_T)(0x3C600008 + 0x300000 * (bus)))) -#define IICDS(bus) (*((REG32_PTR_T)(0x3C60000C + 0x300000 * (bus)))) -#define IICUNK10(bus) (*((REG32_PTR_T)(0x3C600010 + 0x300000 * (bus)))) -#define IICUNK14(bus) (*((REG32_PTR_T)(0x3C600014 + 0x300000 * (bus)))) -#define IICUNK18(bus) (*((REG32_PTR_T)(0x3C600018 + 0x300000 * (bus)))) -#define IICSTA2(bus) (*((REG32_PTR_T)(0x3C600020 + 0x300000 * (bus)))) +#define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \ + CLOCKGATE_I2C0) #endif /* 19. SPI (SERIAL PERHIPERAL INTERFACE) */ #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 -#define SPCLKCON (*(REG32_PTR_T)(0x3CD00000)) /* Clock Control Register */ -#define SPCON (*(REG32_PTR_T)(0x3CD00004)) /* Control Register */ -#define SPSTA (*(REG32_PTR_T)(0x3CD00008)) /* Status Register */ -#define SPPIN (*(REG32_PTR_T)(0x3CD0000C)) /* Pin Control Register */ -#define SPTDAT (*(REG32_PTR_T)(0x3CD00010)) /* Tx Data Register */ -#define SPRDAT (*(REG32_PTR_T)(0x3CD00014)) /* Rx Data Register */ -#define SPPRE (*(REG32_PTR_T)(0x3CD00018)) /* Baud Rate Prescaler Register */ +#define SPI_BASE 0x3CD00000 + +#define SPCLKCON (*(REG32_PTR_T)(SPI_BASE)) /* Clock Control Register */ +#define SPCON (*(REG32_PTR_T)(SPI_BASE + 0x04)) /* Control Register */ +#define SPSTA (*(REG32_PTR_T)(SPI_BASE + 0x08)) /* Status Register */ +#define SPPIN (*(REG32_PTR_T)(SPI_BASE + 0x0C)) /* Pin Control Register */ +#define SPTDAT (*(REG32_PTR_T)(SPI_BASE + 0x10)) /* Tx Data Register */ +#define SPRDAT (*(REG32_PTR_T)(SPI_BASE + 0x14)) /* Rx Data Register */ +#define SPPRE (*(REG32_PTR_T)(SPI_BASE + 0x18)) /* Baud Rate Prescaler Register */ #elif CONFIG_CPU==S5L8702 #define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \ (i) == 1 ? 0x3ce00000 : \ @@ -908,189 +931,152 @@ #endif /* 20. ADC CONTROLLER */ -#define ADCCON (*(REG32_PTR_T)(0x3CE00000)) /* ADC Control Register */ -#define ADCTSC (*(REG32_PTR_T)(0x3CE00004)) /* ADC Touch Screen Control Register */ -#define ADCDLY (*(REG32_PTR_T)(0x3CE00008)) /* ADC Start or Interval Delay Register */ -#define ADCDAT0 (*(REG32_PTR_T)(0x3CE0000C)) /* ADC Conversion Data Register */ -#define ADCDAT1 (*(REG32_PTR_T)(0x3CE00010)) /* ADC Conversion Data Register */ -#define ADCUPDN (*(REG32_PTR_T)(0x3CE00014)) /* Stylus Up or Down Interrpt Register */ +#define ADC_BASE 0x3CE00000 + +#define ADCCON (*(REG32_PTR_T)(ADC_BASE)) /* ADC Control Register */ +#define ADCTSC (*(REG32_PTR_T)(ADC_BASE + 0x04)) /* ADC Touch Screen Control Register */ +#define ADCDLY (*(REG32_PTR_T)(ADC_BASE + 0x08)) /* ADC Start or Interval Delay Register */ +#define ADCDAT0 (*(REG32_PTR_T)(ADC_BASE + 0x0C)) /* ADC Conversion Data Register */ +#define ADCDAT1 (*(REG32_PTR_T)(ADC_BASE + 0x10)) /* ADC Conversion Data Register */ +#define ADCUPDN (*(REG32_PTR_T)(ADC_BASE + 0x14)) /* Stylus Up or Down Interrpt Register */ /* 21. USB 2.0 FUNCTION CONTROLER SPECIAL REGISTER */ -#define USB_IR (*(REG32_PTR_T)(0x38800000)) /* Index Register */ -#define USB_EIR (*(REG32_PTR_T)(0x38800004)) /* Endpoint Interrupt Register */ -#define USB_EIER (*(REG32_PTR_T)(0x38800008)) /* Endpoint Interrupt Enable Register */ -#define USB_FAR (*(REG32_PTR_T)(0x3880000C)) /* Function Address Register */ -#define USB_FNR (*(REG32_PTR_T)(0x38800010)) /* Frame Number Register */ -#define USB_EDR (*(REG32_PTR_T)(0x38800014)) /* Endpoint Direction Register */ -#define USB_TR (*(REG32_PTR_T)(0x38800018)) /* Test Register */ -#define USB_SSR (*(REG32_PTR_T)(0x3880001C)) /* System Status Register */ -#define USB_SCR (*(REG32_PTR_T)(0x38800020)) /* System Control Register */ -#define USB_EP0SR (*(REG32_PTR_T)(0x38800024)) /* EP0 Status Register */ -#define USB_EP0CR (*(REG32_PTR_T)(0x38800028)) /* EP0 Control Register */ -#define USB_ESR (*(REG32_PTR_T)(0x3880002C)) /* Endpoints Status Register */ -#define USB_ECR (*(REG32_PTR_T)(0x38800030)) /* Endpoints Control Register */ -#define USB_BRCR (*(REG32_PTR_T)(0x38800034)) /* Byte Read Count Register */ -#define USB_BWCR (*(REG32_PTR_T)(0x38800038)) /* Byte Write Count Register */ -#define USB_MPR (*(REG32_PTR_T)(0x3880003C)) /* Max Packet Register */ -#define USB_MCR (*(REG32_PTR_T)(0x38800040)) /* Master Control Register */ -#define USB_MTCR (*(REG32_PTR_T)(0x38800044)) /* Master Transfer Counter Register */ -#define USB_MFCR (*(REG32_PTR_T)(0x38800048)) /* Master FIFO Counter Register */ -#define USB_MTTCR1 (*(REG32_PTR_T)(0x3880004C)) /* Master Total Transfer Counter1 Register */ -#define USB_MTTCR2 (*(REG32_PTR_T)(0x38800050)) /* Master Total Transfer Counter2 Register */ -#define USB_EP0BR (*(REG32_PTR_T)(0x38800060)) /* EP0 Buffer Register */ -#define USB_EP1BR (*(REG32_PTR_T)(0x38800064)) /* EP1 Buffer Register */ -#define USB_EP2BR (*(REG32_PTR_T)(0x38800068)) /* EP2 Buffer Register */ -#define USB_EP3BR (*(REG32_PTR_T)(0x3880006C)) /* EP3 Buffer Register */ -#define USB_EP4BR (*(REG32_PTR_T)(0x38800070)) /* EP4 Buffer Register */ -#define USB_EP5BR (*(REG32_PTR_T)(0x38800074)) /* EP5 Buffer Register */ -#define USB_EP6BR (*(REG32_PTR_T)(0x38800078)) /* EP6 Buffer Register */ -#define USB_MICR (*(REG32_PTR_T)(0x38800084)) /* Master Interface Counter Register */ -#define USB_MBAR1 (*(REG32_PTR_T)(0x38800088)) /* Memory Base Address Register1 */ -#define USB_MBAR2 (*(REG32_PTR_T)(0x3880008C)) /* Memory Base Address Register2 */ -#define USB_MCAR1 (*(REG32_PTR_T)(0x38800094)) /* Memory Current Address Register1 */ -#define USB_MCAR2 (*(REG32_PTR_T)(0x38800098)) /* Memory Current Address Register2 */ +#define USB_FC_BASE 0x38800000 + +#define USB_IR (*(REG32_PTR_T)(USB_FC_BASE)) /* Index Register */ +#define USB_EIR (*(REG32_PTR_T)(USB_FC_BASE + 0x04)) /* Endpoint Interrupt Register */ +#define USB_EIER (*(REG32_PTR_T)(USB_FC_BASE + 0x08)) /* Endpoint Interrupt Enable Register */ +#define USB_FAR (*(REG32_PTR_T)(USB_FC_BASE + 0x0C)) /* Function Address Register */ +#define USB_FNR (*(REG32_PTR_T)(USB_FC_BASE + 0x10)) /* Frame Number Register */ +#define USB_EDR (*(REG32_PTR_T)(USB_FC_BASE + 0x14)) /* Endpoint Direction Register */ +#define USB_TR (*(REG32_PTR_T)(USB_FC_BASE + 0x18)) /* Test Register */ +#define USB_SSR (*(REG32_PTR_T)(USB_FC_BASE + 0x1C)) /* System Status Register */ +#define USB_SCR (*(REG32_PTR_T)(USB_FC_BASE + 0x20)) /* System Control Register */ +#define USB_EP0SR (*(REG32_PTR_T)(USB_FC_BASE + 0x24)) /* EP0 Status Register */ +#define USB_EP0CR (*(REG32_PTR_T)(USB_FC_BASE + 0x28)) /* EP0 Control Register */ +#define USB_ESR (*(REG32_PTR_T)(USB_FC_BASE + 0x2C)) /* Endpoints Status Register */ +#define USB_ECR (*(REG32_PTR_T)(USB_FC_BASE + 0x30)) /* Endpoints Control Register */ +#define USB_BRCR (*(REG32_PTR_T)(USB_FC_BASE + 0x34)) /* Byte Read Count Register */ +#define USB_BWCR (*(REG32_PTR_T)(USB_FC_BASE + 0x38)) /* Byte Write Count Register */ +#define USB_MPR (*(REG32_PTR_T)(USB_FC_BASE + 0x3C)) /* Max Packet Register */ +#define USB_MCR (*(REG32_PTR_T)(USB_FC_BASE + 0x40)) /* Master Control Register */ +#define USB_MTCR (*(REG32_PTR_T)(USB_FC_BASE + 0x44)) /* Master Transfer Counter Register */ +#define USB_MFCR (*(REG32_PTR_T)(USB_FC_BASE + 0x48)) /* Master FIFO Counter Register */ +#define USB_MTTCR1 (*(REG32_PTR_T)(USB_FC_BASE + 0x4C)) /* Master Total Transfer Counter1 Register */ +#define USB_MTTCR2 (*(REG32_PTR_T)(USB_FC_BASE + 0x50)) /* Master Total Transfer Counter2 Register */ +#define USB_EP0BR (*(REG32_PTR_T)(USB_FC_BASE + 0x60)) /* EP0 Buffer Register */ +#define USB_EP1BR (*(REG32_PTR_T)(USB_FC_BASE + 0x64)) /* EP1 Buffer Register */ +#define USB_EP2BR (*(REG32_PTR_T)(USB_FC_BASE + 0x68)) /* EP2 Buffer Register */ +#define USB_EP3BR (*(REG32_PTR_T)(USB_FC_BASE + 0x6C)) /* EP3 Buffer Register */ +#define USB_EP4BR (*(REG32_PTR_T)(USB_FC_BASE + 0x70)) /* EP4 Buffer Register */ +#define USB_EP5BR (*(REG32_PTR_T)(USB_FC_BASE + 0x74)) /* EP5 Buffer Register */ +#define USB_EP6BR (*(REG32_PTR_T)(USB_FC_BASE + 0x78)) /* EP6 Buffer Register */ +#define USB_MICR (*(REG32_PTR_T)(USB_FC_BASE + 0x84)) /* Master Interface Counter Register */ +#define USB_MBAR1 (*(REG32_PTR_T)(USB_FC_BASE + 0x88)) /* Memory Base Address Register1 */ +#define USB_MBAR2 (*(REG32_PTR_T)(USB_FC_BASE + 0x8C)) /* Memory Base Address Register2 */ +#define USB_MCAR1 (*(REG32_PTR_T)(USB_FC_BASE + 0x94)) /* Memory Current Address Register1 */ +#define USB_MCAR2 (*(REG32_PTR_T)(USB_FC_BASE + 0x98)) /* Memory Current Address Register2 */ /* 22. USB 1.1 HOST CONTROLLER SPECIAL REGISTER */ -#define HcRevision (*(REG32_PTR_T)(0x38600000)) -#define HcControl (*(REG32_PTR_T)(0x38600004)) -#define HcCommandStatus (*(REG32_PTR_T)(0x38600008)) -#define HcInterruptStatus (*(REG32_PTR_T)(0x3860000C)) -#define HcInterruptEnable (*(REG32_PTR_T)(0x38600010)) -#define HcInterruptDisable (*(REG32_PTR_T)(0x38600014)) -#define HcHCCA (*(REG32_PTR_T)(0x38600018)) -#define HcPeriodCurrentED (*(REG32_PTR_T)(0x3860001C)) -#define HcControlHeadED (*(REG32_PTR_T)(0x38600020)) -#define HcControlCurrentED (*(REG32_PTR_T)(0x38600024)) -#define HcBulkHeadED (*(REG32_PTR_T)(0x38600028)) -#define HcBulkCurrentED (*(REG32_PTR_T)(0x3860002C)) -#define HcDoneHead (*(REG32_PTR_T)(0x38600030)) -#define HcFmInterval (*(REG32_PTR_T)(0x38600034)) -#define HcFmRemaining (*(REG32_PTR_T)(0x38600038)) -#define HcFmNumber (*(REG32_PTR_T)(0x3860003C)) -#define HcPeriodicStart (*(REG32_PTR_T)(0x38600040)) -#define HcLSThreshold (*(REG32_PTR_T)(0x38600044)) -#define HcRhDescriptorA (*(REG32_PTR_T)(0x38600048)) -#define HcRhDescriptorB (*(REG32_PTR_T)(0x3860004C)) -#define HcRhStatus (*(REG32_PTR_T)(0x38600050)) -#define HcRhPortStatus (*(REG32_PTR_T)(0x38600054)) +#define USB_HC_BASE 0x38600000 + +#define HcRevision (*(REG32_PTR_T)(USB_HC_BASE)) +#define HcControl (*(REG32_PTR_T)(USB_HC_BASE + 0x04)) +#define HcCommandStatus (*(REG32_PTR_T)(USB_HC_BASE + 0x08)) +#define HcInterruptStatus (*(REG32_PTR_T)(USB_HC_BASE + 0x0C)) +#define HcInterruptEnable (*(REG32_PTR_T)(USB_HC_BASE + 0x10)) +#define HcInterruptDisable (*(REG32_PTR_T)(USB_HC_BASE + 0x14)) +#define HcHCCA (*(REG32_PTR_T)(USB_HC_BASE + 0x18)) +#define HcPeriodCurrentED (*(REG32_PTR_T)(USB_HC_BASE + 0x1C)) +#define HcControlHeadED (*(REG32_PTR_T)(USB_HC_BASE + 0x20)) +#define HcControlCurrentED (*(REG32_PTR_T)(USB_HC_BASE + 0x24)) +#define HcBulkHeadED (*(REG32_PTR_T)(USB_HC_BASE + 0x28)) +#define HcBulkCurrentED (*(REG32_PTR_T)(USB_HC_BASE + 0x2C)) +#define HcDoneHead (*(REG32_PTR_T)(USB_HC_BASE + 0x30)) +#define HcFmInterval (*(REG32_PTR_T)(USB_HC_BASE + 0x34)) +#define HcFmRemaining (*(REG32_PTR_T)(USB_HC_BASE + 0x38)) +#define HcFmNumber (*(REG32_PTR_T)(USB_HC_BASE + 0x3C)) +#define HcPeriodicStart (*(REG32_PTR_T)(USB_HC_BASE + 0x40)) +#define HcLSThreshold (*(REG32_PTR_T)(USB_HC_BASE + 0x44)) +#define HcRhDescriptorA (*(REG32_PTR_T)(USB_HC_BASE + 0x48)) +#define HcRhDescriptorB (*(REG32_PTR_T)(USB_HC_BASE + 0x4C)) +#define HcRhStatus (*(REG32_PTR_T)(USB_HC_BASE + 0x50)) +#define HcRhPortStatus (*(REG32_PTR_T)(USB_HC_BASE + 0x54)) /* 23. USB 2.0 PHY CONTROL */ -#define PHYCTRL (*(REG32_PTR_T)(0x3C400000)) /* USB2.0 PHY Control Register */ -#define PHYPWR (*(REG32_PTR_T)(0x3C400004)) /* USB2.0 PHY Power Control Register */ -#define URSTCON (*(REG32_PTR_T)(0x3C400008)) /* USB Reset Control Register */ -#define UCLKCON (*(REG32_PTR_T)(0x3C400010)) /* USB Clock Control Register */ +#define USB_PHY_BASE 0x3C400000 + +#define PHYCTRL (*(REG32_PTR_T)(USB_PHY_BASE)) /* USB2.0 PHY Control Register */ +#define PHYPWR (*(REG32_PTR_T)(USB_PHY_BASE + 0x04)) /* USB2.0 PHY Power Control Register */ +#define URSTCON (*(REG32_PTR_T)(USB_PHY_BASE + 0x08)) /* USB Reset Control Register */ +#define UCLKCON (*(REG32_PTR_T)(USB_PHY_BASE + 0x10)) /* USB Clock Control Register */ /* 24. GPIO PORT CONTROL */ +#define GPIO_BASE 0x3CF00000 + +#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 +#define GPIO_OFFSET_BITS 4 +#elif CONFIG_CPU==S5L8702 +#define GPIO_OFFSET_BITS 5 +#endif + +#define PCON(i) (*((REG32_PTR_T)(GPIO_BASE + ((i) << GPIO_OFFSET_BITS)))) +#define PDAT(i) (*((REG32_PTR_T)(GPIO_BASE + 0x04 + ((i) << GPIO_OFFSET_BITS)))) +#define PUNA(i) (*((REG32_PTR_T)(GPIO_BASE + 0x08 + ((i) << GPIO_OFFSET_BITS)))) +#define PUNB(i) (*((REG32_PTR_T)(GPIO_BASE + 0x0c + ((i) << GPIO_OFFSET_BITS)))) + +#if CONFIG_CPU==S5L8702 +#define PUNC(i) (*((REG32_PTR_T)(GPIO_BASE + 0x10 + ((i) << GPIO_OFFSET_BITS)))) +#endif + +#define PCON0 PCON(0) /* Configures the pins of port 0 */ +#define PDAT0 PDAT(0) /* The data register for port 0 */ +#define PCON1 PCON(1) /* Configures the pins of port 1 */ +#define PDAT1 PDAT(1) /* The data register for port 1 */ +#define PCON2 PCON(2) /* Configures the pins of port 2 */ +#define PDAT2 PDAT(2) /* The data register for port 2 */ +#define PCON3 PCON(3) /* Configures the pins of port 3 */ +#define PDAT3 PDAT(3) /* The data register for port 3 */ +#define PCON4 PCON(4) /* Configures the pins of port 4 */ +#define PDAT4 PDAT(4) /* The data register for port 4 */ +#define PCON5 PCON(5) /* Configures the pins of port 5 */ +#define PDAT5 PDAT(5) /* The data register for port 5 */ +#define PUNK5 PUNB(5) /* Unknown thing for port 5 */ +#define PCON6 PCON(6) /* Configures the pins of port 6 */ +#define PDAT6 PDAT(6) /* The data register for port 6 */ +#define PCON7 PCON(7) /* Configures the pins of port 7 */ +#define PDAT7 PDAT(7) /* The data register for port 7 */ +#define PCON10 PCON(10) /* Configures the pins of port 10 */ +#define PDAT10 PDAT(10) /* The data register for port 10 */ +#define PCON11 PCON(11) /* Configures the pins of port 11 */ +#define PDAT11 PDAT(11) /* The data register for port 11 */ +#define PCON12 PCON(12) /* Configures the pins of port 12 */ +#define PDAT12 PDAT(12) /* The data register for port 12 */ +#define PCON13 PCON(13) /* Configures the pins of port 13 */ +#define PDAT13 PDAT(13) /* The data register for port 13 */ +#define PCON14 PCON(14) /* Configures the pins of port 14 */ +#define PDAT14 PDAT(14) /* The data register for port 14 */ +#define PCON15 PCON(15) /* Configures the pins of port 15 */ +#define PUNK15 PUNB(15) /* Unknown thing for port 15 */ + #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 -#define PCON0 (*(REG32_PTR_T)(0x3CF00000)) /* Configures the pins of port 0 */ -#define PDAT0 (*(REG32_PTR_T)(0x3CF00004)) /* The data register for port 0 */ -#define PCON1 (*(REG32_PTR_T)(0x3CF00010)) /* Configures the pins of port 1 */ -#define PDAT1 (*(REG32_PTR_T)(0x3CF00014)) /* The data register for port 1 */ -#define PCON2 (*(REG32_PTR_T)(0x3CF00020)) /* Configures the pins of port 2 */ -#define PDAT2 (*(REG32_PTR_T)(0x3CF00024)) /* The data register for port 2 */ -#define PCON3 (*(REG32_PTR_T)(0x3CF00030)) /* Configures the pins of port 3 */ -#define PDAT3 (*(REG32_PTR_T)(0x3CF00034)) /* The data register for port 3 */ -#define PCON4 (*(REG32_PTR_T)(0x3CF00040)) /* Configures the pins of port 4 */ -#define PDAT4 (*(REG32_PTR_T)(0x3CF00044)) /* The data register for port 4 */ -#define PCON5 (*(REG32_PTR_T)(0x3CF00050)) /* Configures the pins of port 5 */ -#define PDAT5 (*(REG32_PTR_T)(0x3CF00054)) /* The data register for port 5 */ -#define PUNK5 (*(REG32_PTR_T)(0x3CF0005C)) /* Unknown thing for port 5 */ -#define PCON6 (*(REG32_PTR_T)(0x3CF00060)) /* Configures the pins of port 6 */ -#define PDAT6 (*(REG32_PTR_T)(0x3CF00064)) /* The data register for port 6 */ -#define PCON7 (*(REG32_PTR_T)(0x3CF00070)) /* Configures the pins of port 7 */ -#define PDAT7 (*(REG32_PTR_T)(0x3CF00074)) /* The data register for port 7 */ -#define PCON10 (*(REG32_PTR_T)(0x3CF000A0)) /* Configures the pins of port 10 */ -#define PDAT10 (*(REG32_PTR_T)(0x3CF000A4)) /* The data register for port 10 */ -#define PCON11 (*(REG32_PTR_T)(0x3CF000B0)) /* Configures the pins of port 11 */ -#define PDAT11 (*(REG32_PTR_T)(0x3CF000B4)) /* The data register for port 11 */ -#define PCON13 (*(REG32_PTR_T)(0x3CF000D0)) /* Configures the pins of port 13 */ -#define PDAT13 (*(REG32_PTR_T)(0x3CF000D4)) /* The data register for port 13 */ -#define PCON14 (*(REG32_PTR_T)(0x3CF000E0)) /* Configures the pins of port 14 */ -#define PDAT14 (*(REG32_PTR_T)(0x3CF000E4)) /* The data register for port 14 */ -#define PCON15 (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port 15 */ -#define PUNK15 (*(REG32_PTR_T)(0x3CF000FC)) /* Unknown thing for port 15 */ -#define PCON_ASRAM (*(REG32_PTR_T)(0x3CF000F0)) /* Configures the pins of port nor flash */ -#define PCON_SDRAM (*(REG32_PTR_T)(0x3CF000F4)) /* Configures the pins of port sdram */ +#define PCON_ASRAM PCON15 /* Configures the pins of port nor flash */ +#define PCON_SDRAM PDAT15 /* Configures the pins of port sdram */ #elif CONFIG_CPU==S5L8702 -#define PCON(i) (*((REG32_PTR_T)(0x3cf00000 + ((i) << 5)))) -#define PDAT(i) (*((REG32_PTR_T)(0x3cf00004 + ((i) << 5)))) -#define PUNA(i) (*((REG32_PTR_T)(0x3cf00008 + ((i) << 5)))) -#define PUNB(i) (*((REG32_PTR_T)(0x3cf0000c + ((i) << 5)))) -#define PUNC(i) (*((REG32_PTR_T)(0x3cf00010 + ((i) << 5)))) -#define PCON0 (*((REG32_PTR_T)(0x3cf00000))) -#define PDAT0 (*((REG32_PTR_T)(0x3cf00004))) -#define PCON1 (*((REG32_PTR_T)(0x3cf00020))) -#define PDAT1 (*((REG32_PTR_T)(0x3cf00024))) -#define PCON2 (*((REG32_PTR_T)(0x3cf00040))) -#define PDAT2 (*((REG32_PTR_T)(0x3cf00044))) -#define PCON3 (*((REG32_PTR_T)(0x3cf00060))) -#define PDAT3 (*((REG32_PTR_T)(0x3cf00064))) -#define PCON4 (*((REG32_PTR_T)(0x3cf00080))) -#define PDAT4 (*((REG32_PTR_T)(0x3cf00084))) -#define PCON5 (*((REG32_PTR_T)(0x3cf000a0))) -#define PDAT5 (*((REG32_PTR_T)(0x3cf000a4))) -#define PCON6 (*((REG32_PTR_T)(0x3cf000c0))) -#define PDAT6 (*((REG32_PTR_T)(0x3cf000c4))) -#define PCON7 (*((REG32_PTR_T)(0x3cf000e0))) -#define PDAT7 (*((REG32_PTR_T)(0x3cf000e4))) -#define PCON8 (*((REG32_PTR_T)(0x3cf00100))) -#define PDAT8 (*((REG32_PTR_T)(0x3cf00104))) -#define PCON9 (*((REG32_PTR_T)(0x3cf00120))) -#define PDAT9 (*((REG32_PTR_T)(0x3cf00124))) -#define PCONA (*((REG32_PTR_T)(0x3cf00140))) -#define PDATA (*((REG32_PTR_T)(0x3cf00144))) -#define PCONB (*((REG32_PTR_T)(0x3cf00160))) -#define PDATB (*((REG32_PTR_T)(0x3cf00164))) -#define PCONC (*((REG32_PTR_T)(0x3cf00180))) -#define PDATC (*((REG32_PTR_T)(0x3cf00184))) -#define PCOND (*((REG32_PTR_T)(0x3cf001a0))) -#define PDATD (*((REG32_PTR_T)(0x3cf001a4))) -#define PCONE (*((REG32_PTR_T)(0x3cf001c0))) -#define PDATE (*((REG32_PTR_T)(0x3cf001c4))) -#define PCONF (*((REG32_PTR_T)(0x3cf001e0))) -#define PDATF (*((REG32_PTR_T)(0x3cf001e4))) -#define GPIOCMD (*((REG32_PTR_T)(0x3cf00200))) +#define GPIOCMD (*((REG32_PTR_T)(GPIO_BASE + 0x200))) #endif /* 25. UART */ #if CONFIG_CPU==S5L8700 /* s5l8700 UC87XX HW: 1 UARTC, 2 ports */ -#define S5L8700_N_UARTC 1 #define S5L8700_N_PORTS 2 #define UARTC_BASE_ADDR 0x3CC00000 #define UARTC_N_PORTS 2 #define UARTC_PORT_OFFSET 0x8000 - -/* UART 0 */ -#define ULCON0 (*(REG32_PTR_T)(0x3CC00000)) /* Line Control Register */ -#define UCON0 (*(REG32_PTR_T)(0x3CC00004)) /* Control Register */ -#define UFCON0 (*(REG32_PTR_T)(0x3CC00008)) /* FIFO Control Register */ -#define UMCON0 (*(REG32_PTR_T)(0x3CC0000C)) /* Modem Control Register */ -#define UTRSTAT0 (*(REG32_PTR_T)(0x3CC00010)) /* Tx/Rx Status Register */ -#define UERSTAT0 (*(REG32_PTR_T)(0x3CC00014)) /* Rx Error Status Register */ -#define UFSTAT0 (*(REG32_PTR_T)(0x3CC00018)) /* FIFO Status Register */ -#define UMSTAT0 (*(REG32_PTR_T)(0x3CC0001C)) /* Modem Status Register */ -#define UTXH0 (*(REG32_PTR_T)(0x3CC00020)) /* Transmit Buffer Register */ -#define URXH0 (*(REG32_PTR_T)(0x3CC00024)) /* Receive Buffer Register */ -#define UBRDIV0 (*(REG32_PTR_T)(0x3CC00028)) /* Baud Rate Divisor Register */ - -/* UART 1*/ -#define ULCON1 (*(REG32_PTR_T)(0x3CC08000)) /* Line Control Register */ -#define UCON1 (*(REG32_PTR_T)(0x3CC08004)) /* Control Register */ -#define UFCON1 (*(REG32_PTR_T)(0x3CC08008)) /* FIFO Control Register */ -#define UMCON1 (*(REG32_PTR_T)(0x3CC0800C)) /* Modem Control Register */ -#define UTRSTAT1 (*(REG32_PTR_T)(0x3CC08010)) /* Tx/Rx Status Register */ -#define UERSTAT1 (*(REG32_PTR_T)(0x3CC08014)) /* Rx Error Status Register */ -#define UFSTAT1 (*(REG32_PTR_T)(0x3CC08018)) /* FIFO Status Register */ -#define UMSTAT1 (*(REG32_PTR_T)(0x3CC0801C)) /* Modem Status Register */ -#define UTXH1 (*(REG32_PTR_T)(0x3CC08020)) /* Transmit Buffer Register */ -#define URXH1 (*(REG32_PTR_T)(0x3CC08024)) /* Receive Buffer Register */ -#define UBRDIV1 (*(REG32_PTR_T)(0x3CC08028)) /* Baud Rate Divisor Register */ #elif CONFIG_CPU==S5L8701 /* s5l8701 UC87XX HW: 3 UARTC, 1 port per UARTC */ #define S5L8701_N_UARTC 3 -#define S5L8701_N_PORTS 3 #define UARTC0_BASE_ADDR 0x3CC00000 #define UARTC0_N_PORTS 1 @@ -1117,177 +1103,161 @@ #define LCD_BASE 0x38300000 #endif -#define LCD_CON (*(REG32_PTR_T)(LCD_BASE+0x00)) /* Control register. */ -#define LCD_WCMD (*(REG32_PTR_T)(LCD_BASE+0x04)) /* Write command register. */ -#define LCD_RCMD (*(REG32_PTR_T)(LCD_BASE+0x0C)) /* Read command register. */ -#define LCD_RDATA (*(REG32_PTR_T)(LCD_BASE+0x10)) /* Read data register. */ -#define LCD_DBUFF (*(REG32_PTR_T)(LCD_BASE+0x14)) /* Read Data buffer */ -#define LCD_INTCON (*(REG32_PTR_T)(LCD_BASE+0x18)) /* Interrupt control register */ -#define LCD_STATUS (*(REG32_PTR_T)(LCD_BASE+0x1C)) /* LCD Interface status 0106 */ -#define LCD_PHTIME (*(REG32_PTR_T)(LCD_BASE+0x20)) /* Phase time register 0060 */ -#define LCD_RST_TIME (*(REG32_PTR_T)(LCD_BASE+0x24)) /* Reset active period 07FF */ -#define LCD_DRV_RST (*(REG32_PTR_T)(LCD_BASE+0x28)) /* Reset drive signal */ -#define LCD_WDATA (*(REG32_PTR_T)(LCD_BASE+0x40)) /* Write data register (0x40...0x5C) FIXME */ +#define LCD_CON (*(REG32_PTR_T)(LCD_BASE)) /* Control register. */ +#define LCD_WCMD (*(REG32_PTR_T)(LCD_BASE + 0x04)) /* Write command register. */ +#define LCD_RCMD (*(REG32_PTR_T)(LCD_BASE + 0x0C)) /* Read command register. */ +#define LCD_RDATA (*(REG32_PTR_T)(LCD_BASE + 0x10)) /* Read data register. */ +#define LCD_DBUFF (*(REG32_PTR_T)(LCD_BASE + 0x14)) /* Read Data buffer */ +#define LCD_INTCON (*(REG32_PTR_T)(LCD_BASE + 0x18)) /* Interrupt control register */ +#define LCD_STATUS (*(REG32_PTR_T)(LCD_BASE + 0x1C)) /* LCD Interface status 0106 */ +#define LCD_PHTIME (*(REG32_PTR_T)(LCD_BASE + 0x20)) /* Phase time register 0060 */ +#define LCD_RST_TIME (*(REG32_PTR_T)(LCD_BASE + 0x24)) /* Reset active period 07FF */ +#define LCD_DRV_RST (*(REG32_PTR_T)(LCD_BASE + 0x28)) /* Reset drive signal */ +#define LCD_WDATA (*(REG32_PTR_T)(LCD_BASE + 0x40)) /* Write data register (0x40...0x5C) FIXME */ /* 27. CLCD CONTROLLER */ -#define LCDCON1 (*(REG32_PTR_T)(0x39200000)) /* LCD control 1 register */ -#define LCDCON2 (*(REG32_PTR_T)(0x39200004)) /* LCD control 2 register */ -#define LCDTCON1 (*(REG32_PTR_T)(0x39200008)) /* LCD time control 1 register */ -#define LCDTCON2 (*(REG32_PTR_T)(0x3920000C)) /* LCD time control 2 register */ -#define LCDTCON3 (*(REG32_PTR_T)(0x39200010)) /* LCD time control 3 register */ -#define LCDOSD1 (*(REG32_PTR_T)(0x39200014)) /* LCD OSD control 1 register */ -#define LCDOSD2 (*(REG32_PTR_T)(0x39200018)) /* LCD OSD control 2 register */ -#define LCDOSD3 (*(REG32_PTR_T)(0x3920001C)) /* LCD OSD control 3 register */ -#define LCDB1SADDR1 (*(REG32_PTR_T)(0x39200020)) /* Frame buffer start address register for Back-Ground buffer 1 */ -#define LCDB2SADDR1 (*(REG32_PTR_T)(0x39200024)) /* Frame buffer start address register for Back-Ground buffer 2 */ -#define LCDF1SADDR1 (*(REG32_PTR_T)(0x39200028)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 1 */ -#define LCDF2SADDR1 (*(REG32_PTR_T)(0x3920002C)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 2 */ -#define LCDB1SADDR2 (*(REG32_PTR_T)(0x39200030)) /* Frame buffer end address register for Back-Ground buffer 1 */ -#define LCDB2SADDR2 (*(REG32_PTR_T)(0x39200034)) /* Frame buffer end address register for Back-Ground buffer 2 */ -#define LCDF1SADDR2 (*(REG32_PTR_T)(0x39200038)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 1 */ -#define LCDF2SADDR2 (*(REG32_PTR_T)(0x3920003C)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 2 */ -#define LCDB1SADDR3 (*(REG32_PTR_T)(0x39200040)) /* Virtual screen address set for Back-Ground buffer 1 */ -#define LCDB2SADDR3 (*(REG32_PTR_T)(0x39200044)) /* Virtual screen address set for Back-Ground buffer 2 */ -#define LCDF1SADDR3 (*(REG32_PTR_T)(0x39200048)) /* Virtual screen address set for Fore-Ground(OSD) buffer 1 */ -#define LCDF2SADDR3 (*(REG32_PTR_T)(0x3920004C)) /* Virtual screen address set for Fore-Ground(OSD) buffer 2 */ -#define LCDINTCON (*(REG32_PTR_T)(0x39200050)) /* Indicate the LCD interrupt control register */ -#define LCDKEYCON (*(REG32_PTR_T)(0x39200054)) /* Color key control register */ -#define LCDCOLVAL (*(REG32_PTR_T)(0x39200058)) /* Color key value ( transparent value) register */ -#define LCDBGCON (*(REG32_PTR_T)(0x3920005C)) /* Back-Ground color control */ -#define LCDFGCON (*(REG32_PTR_T)(0x39200060)) /* Fore-Ground color control */ -#define LCDDITHMODE (*(REG32_PTR_T)(0x39200064)) /* Dithering mode register. */ +#define LCDBASE 0x39200000 + +#define LCDCON1 (*(REG32_PTR_T)(LCDBASE)) /* LCD control 1 register */ +#define LCDCON2 (*(REG32_PTR_T)(LCDBASE + 0x04)) /* LCD control 2 register */ +#define LCDTCON1 (*(REG32_PTR_T)(LCDBASE + 0x08)) /* LCD time control 1 register */ +#define LCDTCON2 (*(REG32_PTR_T)(LCDBASE + 0x0C)) /* LCD time control 2 register */ +#define LCDTCON3 (*(REG32_PTR_T)(LCDBASE + 0x10)) /* LCD time control 3 register */ +#define LCDOSD1 (*(REG32_PTR_T)(LCDBASE + 0x14)) /* LCD OSD control 1 register */ +#define LCDOSD2 (*(REG32_PTR_T)(LCDBASE + 0x18)) /* LCD OSD control 2 register */ +#define LCDOSD3 (*(REG32_PTR_T)(LCDBASE + 0x1C)) /* LCD OSD control 3 register */ +#define LCDB1SADDR1 (*(REG32_PTR_T)(LCDBASE + 0x20)) /* Frame buffer start address register for Back-Ground buffer 1 */ +#define LCDB2SADDR1 (*(REG32_PTR_T)(LCDBASE + 0x24)) /* Frame buffer start address register for Back-Ground buffer 2 */ +#define LCDF1SADDR1 (*(REG32_PTR_T)(LCDBASE + 0x28)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 1 */ +#define LCDF2SADDR1 (*(REG32_PTR_T)(LCDBASE + 0x2C)) /* Frame buffer start address register for Fore-Ground (OSD) buffer 2 */ +#define LCDB1SADDR2 (*(REG32_PTR_T)(LCDBASE + 0x30)) /* Frame buffer end address register for Back-Ground buffer 1 */ +#define LCDB2SADDR2 (*(REG32_PTR_T)(LCDBASE + 0x34)) /* Frame buffer end address register for Back-Ground buffer 2 */ +#define LCDF1SADDR2 (*(REG32_PTR_T)(LCDBASE + 0x38)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 1 */ +#define LCDF2SADDR2 (*(REG32_PTR_T)(LCDBASE + 0x3C)) /* Frame buffer end address register for Fore-Ground (OSD) buffer 2 */ +#define LCDB1SADDR3 (*(REG32_PTR_T)(LCDBASE + 0x40)) /* Virtual screen address set for Back-Ground buffer 1 */ +#define LCDB2SADDR3 (*(REG32_PTR_T)(LCDBASE + 0x44)) /* Virtual screen address set for Back-Ground buffer 2 */ +#define LCDF1SADDR3 (*(REG32_PTR_T)(LCDBASE + 0x48)) /* Virtual screen address set for Fore-Ground(OSD) buffer 1 */ +#define LCDF2SADDR3 (*(REG32_PTR_T)(LCDBASE + 0x4C)) /* Virtual screen address set for Fore-Ground(OSD) buffer 2 */ +#define LCDINTCON (*(REG32_PTR_T)(LCDBASE + 0x50)) /* Indicate the LCD interrupt control register */ +#define LCDKEYCON (*(REG32_PTR_T)(LCDBASE + 0x54)) /* Color key control register */ +#define LCDCOLVAL (*(REG32_PTR_T)(LCDBASE + 0x58)) /* Color key value ( transparent value) register */ +#define LCDBGCON (*(REG32_PTR_T)(LCDBASE + 0x5C)) /* Back-Ground color control */ +#define LCDFGCON (*(REG32_PTR_T)(LCDBASE + 0x60)) /* Fore-Ground color control */ +#define LCDDITHMODE (*(REG32_PTR_T)(LCDBASE + 0x64)) /* Dithering mode register. */ /* 28. ATA CONTROLLER */ #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 -#define ATA_CONTROL (*(REG32_PTR_T)(0x38E00000)) /* Enable and clock down status */ -#define ATA_STATUS (*(REG32_PTR_T)(0x38E00004)) /* Status */ -#define ATA_COMMAND (*(REG32_PTR_T)(0x38E00008)) /* Command */ -#define ATA_SWRST (*(REG32_PTR_T)(0x38E0000C)) /* Software reset */ -#define ATA_IRQ (*(REG32_PTR_T)(0x38E00010)) /* Interrupt sources */ -#define ATA_IRQ_MASK (*(REG32_PTR_T)(0x38E00014)) /* Interrupt mask */ -#define ATA_CFG (*(REG32_PTR_T)(0x38E00018)) /* Configuration for ATA interface */ -#define ATA_PIO_TIME (*(REG32_PTR_T)(0x38E0002C)) /* PIO timing */ -#define ATA_UDMA_TIME (*(REG32_PTR_T)(0x38E00030)) /* UDMA timing */ -#define ATA_XFR_NUM (*(REG32_PTR_T)(0x38E00034)) /* Transfer number */ -#define ATA_XFR_CNT (*(REG32_PTR_T)(0x38E00038)) /* Current transfer count */ -#define ATA_TBUF_START (*(REG32_PTR_T)(0x38E0003C)) /* Start address of track buffer */ -#define ATA_TBUF_SIZE (*(REG32_PTR_T)(0x38E00040)) /* Size of track buffer */ -#define ATA_SBUF_START (*(REG32_PTR_T)(0x38E00044)) /* Start address of Source buffer1 */ -#define ATA_SBUF_SIZE (*(REG32_PTR_T)(0x38E00048)) /* Size of source buffer1 */ -#define ATA_CADR_TBUF (*(REG32_PTR_T)(0x38E0004C)) /* Current write address of track buffer */ -#define ATA_CADR_SBUF (*(REG32_PTR_T)(0x38E00050)) /* Current read address of source buffer */ -#define ATA_PIO_DTR (*(REG32_PTR_T)(0x38E00054)) /* PIO device data register */ -#define ATA_PIO_FED (*(REG32_PTR_T)(0x38E00058)) /* PIO device Feature/Error register */ -#define ATA_PIO_SCR (*(REG32_PTR_T)(0x38E0005C)) /* PIO sector count register */ -#define ATA_PIO_LLR (*(REG32_PTR_T)(0x38E00060)) /* PIO device LBA low register */ -#define ATA_PIO_LMR (*(REG32_PTR_T)(0x38E00064)) /* PIO device LBA middle register */ -#define ATA_PIO_LHR (*(REG32_PTR_T)(0x38E00068)) /* PIO device LBA high register */ -#define ATA_PIO_DVR (*(REG32_PTR_T)(0x38E0006C)) /* PIO device register */ -#define ATA_PIO_CSD (*(REG32_PTR_T)(0x38E00070)) /* PIO device command/status register */ -#define ATA_PIO_DAD (*(REG32_PTR_T)(0x38E00074)) /* PIO control/alternate status register */ -#define ATA_PIO_READY (*(REG32_PTR_T)(0x38E00078)) /* PIO data read/write ready */ -#define ATA_PIO_RDATA (*(REG32_PTR_T)(0x38E0007C)) /* PIO read data from device register */ -#define BUS_FIFO_STATUS (*(REG32_PTR_T)(0x38E00080)) /* Reserved */ -#define ATA_FIFO_STATUS (*(REG32_PTR_T)(0x38E00084)) /* Reserved */ +#define ATA_BASE 0x38E00000 #elif CONFIG_CPU==S5L8702 -#define ATA_CONTROL (*((REG32_PTR_T)(0x38700000))) -#define ATA_STATUS (*((REG32_PTR_T)(0x38700004))) -#define ATA_COMMAND (*((REG32_PTR_T)(0x38700008))) -#define ATA_SWRST (*((REG32_PTR_T)(0x3870000c))) -#define ATA_IRQ (*((REG32_PTR_T)(0x38700010))) -#define ATA_IRQ_MASK (*((REG32_PTR_T)(0x38700014))) -#define ATA_CFG (*((REG32_PTR_T)(0x38700018))) -#define ATA_MDMA_TIME (*((REG32_PTR_T)(0x38700028))) -#define ATA_PIO_TIME (*((REG32_PTR_T)(0x3870002c))) -#define ATA_UDMA_TIME (*((REG32_PTR_T)(0x38700030))) -#define ATA_XFR_NUM (*((REG32_PTR_T)(0x38700034))) -#define ATA_XFR_CNT (*((REG32_PTR_T)(0x38700038))) -#define ATA_TBUF_START (*((void* volatile*)(0x3870003c))) -#define ATA_TBUF_SIZE (*((REG32_PTR_T)(0x38700040))) -#define ATA_SBUF_START (*((void* volatile*)(0x38700044))) -#define ATA_SBUF_SIZE (*((REG32_PTR_T)(0x38700048))) -#define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c))) -#define ATA_CADR_SBUF (*((void* volatile*)(0x38700050))) -#define ATA_PIO_DTR (*((REG32_PTR_T)(0x38700054))) -#define ATA_PIO_FED (*((REG32_PTR_T)(0x38700058))) -#define ATA_PIO_SCR (*((REG32_PTR_T)(0x3870005c))) -#define ATA_PIO_LLR (*((REG32_PTR_T)(0x38700060))) -#define ATA_PIO_LMR (*((REG32_PTR_T)(0x38700064))) -#define ATA_PIO_LHR (*((REG32_PTR_T)(0x38700068))) -#define ATA_PIO_DVR (*((REG32_PTR_T)(0x3870006c))) -#define ATA_PIO_CSD (*((REG32_PTR_T)(0x38700070))) -#define ATA_PIO_DAD (*((REG32_PTR_T)(0x38700074))) -#define ATA_PIO_READY (*((REG32_PTR_T)(0x38700078))) -#define ATA_PIO_RDATA (*((REG32_PTR_T)(0x3870007c))) -#define ATA_BUS_FIFO_STATUS (*((REG32_PTR_T)(0x38700080))) -#define ATA_FIFO_STATUS (*((REG32_PTR_T)(0x38700084))) -#define ATA_DMA_ADDR (*((void* volatile*)(0x38700088))) +#define ATA_BASE 0x38700000 #endif +#define ATA_CONTROL (*(REG32_PTR_T)(ATA_BASE)) /* Enable and clock down status */ +#define ATA_STATUS (*(REG32_PTR_T)(ATA_BASE + 0x04)) /* Status */ +#define ATA_COMMAND (*(REG32_PTR_T)(ATA_BASE + 0x08)) /* Command */ +#define ATA_SWRST (*(REG32_PTR_T)(ATA_BASE + 0x0C)) /* Software reset */ +#define ATA_IRQ (*(REG32_PTR_T)(ATA_BASE + 0x10)) /* Interrupt sources */ +#define ATA_IRQ_MASK (*(REG32_PTR_T)(ATA_BASE + 0x14)) /* Interrupt mask */ +#define ATA_CFG (*(REG32_PTR_T)(ATA_BASE + 0x18)) /* Configuration for ATA interface */ +#define ATA_MDMA_TIME (*(REG32_PTR_T)(ATA_BASE + 0x28)) +#define ATA_PIO_TIME (*(REG32_PTR_T)(ATA_BASE + 0x2C)) /* PIO timing */ +#define ATA_UDMA_TIME (*(REG32_PTR_T)(ATA_BASE + 0x30)) /* UDMA timing */ +#define ATA_XFR_NUM (*(REG32_PTR_T)(ATA_BASE + 0x34)) /* Transfer number */ +#define ATA_XFR_CNT (*(REG32_PTR_T)(ATA_BASE + 0x38)) /* Current transfer count */ +#define ATA_TBUF_START (*(VOID_PTR_PTR_T)(ATA_BASE + 0x3C)) /* Start address of track buffer */ +#define ATA_TBUF_SIZE (*(REG32_PTR_T)(ATA_BASE + 0x40)) /* Size of track buffer */ +#define ATA_SBUF_START (*(VOID_PTR_PTR_T)(ATA_BASE + 0x44)) /* Start address of Source buffer1 */ +#define ATA_SBUF_SIZE (*(REG32_PTR_T)(ATA_BASE + 0x48)) /* Size of source buffer1 */ +#define ATA_CADR_TBUF (*(VOID_PTR_PTR_T)(ATA_BASE + 0x4C)) /* Current write address of track buffer */ +#define ATA_CADR_SBUF (*(VOID_PTR_PTR_T)(ATA_BASE + 0x50)) /* Current read address of source buffer */ +#define ATA_PIO_DTR (*(REG32_PTR_T)(ATA_BASE + 0x54)) /* PIO device data register */ +#define ATA_PIO_FED (*(REG32_PTR_T)(ATA_BASE + 0x58)) /* PIO device Feature/Error register */ +#define ATA_PIO_SCR (*(REG32_PTR_T)(ATA_BASE + 0x5C)) /* PIO sector count register */ +#define ATA_PIO_LLR (*(REG32_PTR_T)(ATA_BASE + 0x60)) /* PIO device LBA low register */ +#define ATA_PIO_LMR (*(REG32_PTR_T)(ATA_BASE + 0x64)) /* PIO device LBA middle register */ +#define ATA_PIO_LHR (*(REG32_PTR_T)(ATA_BASE + 0x68)) /* PIO device LBA high register */ +#define ATA_PIO_DVR (*(REG32_PTR_T)(ATA_BASE + 0x6C)) /* PIO device register */ +#define ATA_PIO_CSD (*(REG32_PTR_T)(ATA_BASE + 0x70)) /* PIO device command/status register */ +#define ATA_PIO_DAD (*(REG32_PTR_T)(ATA_BASE + 0x74)) /* PIO control/alternate status register */ +#define ATA_PIO_READY (*(REG32_PTR_T)(ATA_BASE + 0x78)) /* PIO data read/write ready */ +#define ATA_PIO_RDATA (*(REG32_PTR_T)(ATA_BASE + 0x7C)) /* PIO read data from device register */ +#define ATA_BUS_FIFO_STATUS (*(REG32_PTR_T)(ATA_BASE + 0x80)) /* Reserved */ +#define ATA_FIFO_STATUS (*(REG32_PTR_T)(ATA_BASE + 0x84)) /* Reserved */ +#define ATA_DMA_ADDR (*(VOID_PTR_PTR_T)(ATA_BASE + 0x88)) + /* 29. CHIP ID */ -#define REG_ONE (*(REG32_PTR_T)(0x3D100000)) /* Receive the first 32 bits from a fuse box */ -#define REG_TWO (*(REG32_PTR_T)(0x3D100004)) /* Receive the other 8 bits from a fuse box */ +#define CHIP_ID_BASE 0x3D100000 +#define REG_ONE (*(REG32_PTR_T)(CHIP_ID_BASE)) /* Receive the first 32 bits from a fuse box */ +#define REG_TWO (*(REG32_PTR_T)(CHIP_ID_BASE + 0x04)) /* Receive the other 8 bits from a fuse box */ +/* +The following peripherals are not present in the Samsung S5L8700 datasheet. +Information for them was gathered solely by reverse-engineering Apple's firmware. +*/ /* Hardware AES crypto unit - S5L8701+ */ #if CONFIG_CPU==S5L8701 -#define AESCONTROL (*(REG32_PTR_T)(0x39800000)) -#define AESGO (*(REG32_PTR_T)(0x39800004)) -#define AESUNKREG0 (*(REG32_PTR_T)(0x39800008)) -#define AESSTATUS (*(REG32_PTR_T)(0x3980000C)) -#define AESUNKREG1 (*(REG32_PTR_T)(0x39800010)) -#define AESKEYLEN (*(REG32_PTR_T)(0x39800014)) -#define AESOUTSIZE (*(REG32_PTR_T)(0x39800018)) -#define AESOUTADDR (*(REG32_PTR_T)(0x39800020)) -#define AESINSIZE (*(REG32_PTR_T)(0x39800024)) -#define AESINADDR (*(REG32_PTR_T)(0x39800028)) -#define AESAUXSIZE (*(REG32_PTR_T)(0x3980002C)) -#define AESAUXADDR (*(REG32_PTR_T)(0x39800030)) -#define AESSIZE3 (*(REG32_PTR_T)(0x39800034)) -#define AESTYPE (*(REG32_PTR_T)(0x3980006C)) +#define AES_BASE 0x39800000 #elif CONFIG_CPU==S5L8702 -#define AESCONTROL (*((REG32_PTR_T)(0x38c00000))) -#define AESGO (*((REG32_PTR_T)(0x38c00004))) -#define AESUNKREG0 (*((REG32_PTR_T)(0x38c00008))) -#define AESSTATUS (*((REG32_PTR_T)(0x38c0000c))) -#define AESUNKREG1 (*((REG32_PTR_T)(0x38c00010))) -#define AESKEYLEN (*((REG32_PTR_T)(0x38c00014))) -#define AESOUTSIZE (*((REG32_PTR_T)(0x38c00018))) -#define AESOUTADDR (*((void* volatile*)(0x38c00020))) -#define AESINSIZE (*((REG32_PTR_T)(0x38c00024))) -#define AESINADDR (*((const void* volatile*)(0x38c00028))) -#define AESAUXSIZE (*((REG32_PTR_T)(0x38c0002c))) -#define AESAUXADDR (*((void* volatile*)(0x38c00030))) -#define AESSIZE3 (*((REG32_PTR_T)(0x38c00034))) -#define AESKEY ((REG32_PTR_T)(0x38c0004c)) -#define AESTYPE (*((REG32_PTR_T)(0x38c0006c))) -#define AESIV ((REG32_PTR_T)(0x38c00074)) -#define AESTYPE2 (*((REG32_PTR_T)(0x38c00088))) -#define AESUNKREG2 (*((REG32_PTR_T)(0x38c0008c))) +#define AES_BASE 0x38c00000 +#endif + +#if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 +#define AESCONTROL (*((REG32_PTR_T)(AES_BASE))) +#define AESGO (*((REG32_PTR_T)(AES_BASE + 0x04))) +#define AESUNKREG0 (*((REG32_PTR_T)(AES_BASE + 0x08))) +#define AESSTATUS (*((REG32_PTR_T)(AES_BASE + 0x0c))) +#define AESUNKREG1 (*((REG32_PTR_T)(AES_BASE + 0x10))) +#define AESKEYLEN (*((REG32_PTR_T)(AES_BASE + 0x14))) +#define AESOUTSIZE (*((REG32_PTR_T)(AES_BASE + 0x18))) +#define AESINSIZE (*((REG32_PTR_T)(AES_BASE + 0x24))) +#define AESAUXSIZE (*((REG32_PTR_T)(AES_BASE + 0x2c))) +#define AESSIZE3 (*((REG32_PTR_T)(AES_BASE + 0x34))) +#define AESTYPE (*((REG32_PTR_T)(AES_BASE + 0x6c))) +#endif + +#if CONFIG_CPU==S5L8701 +#define AESOUTADDR (*((REG32_PTR_T)(AES_BASE + 0x20))) +#define AESINADDR (*((REG32_PTR_T)(AES_BASE + 0x28))) +#define AESAUXADDR (*((REG32_PTR_T)(AES_BASE + 0x30))) +#elif CONFIG_CPU==S5L8702 +#define AESOUTADDR (*((VOID_PTR_PTR_T)(AES_BASE + 0x20))) +#define AESINADDR (*((CONST_VOID_PTR_PTR_T)(AES_BASE + 0x28))) +#define AESAUXADDR (*((VOID_PTR_PTR_T)(AES_BASE + 0x30))) +#define AESKEY ((REG32_PTR_T)(AES_BASE + 0x4c)) +#define AESIV ((REG32_PTR_T)(AES_BASE + 0x74)) +#define AESTYPE2 (*((REG32_PTR_T)(AES_BASE + 0x88))) +#define AESUNKREG2 (*((REG32_PTR_T)(AES_BASE + 0x8c))) #endif /* SHA-1 unit - S5L8701+ */ #if CONFIG_CPU==S5L8701 -#define HASHCTRL (*(REG32_PTR_T)(0x3C600000)) -#define HASHRESULT ((REG32_PTR_T)(0x3C600020)) -#define HASHDATAIN ((REG32_PTR_T)(0x3C600040)) +#define HASH_BASE 0x3C600000 + +#define HASHCTRL (*(REG32_PTR_T)(HASH_BASE)) +#define HASHRESULT ((REG32_PTR_T)(HASH_BASE + 0x20)) +#define HASHDATAIN ((REG32_PTR_T)(HASH_BASE + 0x40)) #elif CONFIG_CPU==S5L8702 -#define SHA1CONFIG (*((REG32_PTR_T)(0x38000000))) -#define SHA1RESET (*((REG32_PTR_T)(0x38000004))) -#define SHA1RESULT ((REG32_PTR_T)(0x38000020)) -#define SHA1DATAIN ((REG32_PTR_T)(0x38000040)) +#define SHA1_BASE 0x38000000 + +#define SHA1CONFIG (*((REG32_PTR_T)(SHA1_BASE))) +#define SHA1RESET (*((REG32_PTR_T)(SHA1_BASE + 0x04))) +#define SHA1RESULT ((REG32_PTR_T)(SHA1_BASE + 0x20)) +#define SHA1DATAIN ((REG32_PTR_T)(SHA1_BASE + 0x40)) #endif /* Clickwheel controller - S5L8701+ */ #if CONFIG_CPU==S5L8701 || CONFIG_CPU==S5L8702 -#define WHEEL00 (*((REG32_PTR_T)(0x3C200000))) -#define WHEEL04 (*((REG32_PTR_T)(0x3C200004))) -#define WHEEL08 (*((REG32_PTR_T)(0x3C200008))) -#define WHEEL0C (*((REG32_PTR_T)(0x3C20000C))) -#define WHEEL10 (*((REG32_PTR_T)(0x3C200010))) -#define WHEELINT (*((REG32_PTR_T)(0x3C200014))) -#define WHEELRX (*((REG32_PTR_T)(0x3C200018))) -#define WHEELTX (*((REG32_PTR_T)(0x3C20001C))) +#define WHEEL_BASE 0x3C200000 + +#define WHEEL00 (*((REG32_PTR_T)(WHEEL_BASE))) +#define WHEEL04 (*((REG32_PTR_T)(WHEEL_BASE + 0x04))) +#define WHEEL08 (*((REG32_PTR_T)(WHEEL_BASE + 0x08))) +#define WHEEL0C (*((REG32_PTR_T)(WHEEL_BASE + 0x0C))) +#define WHEEL10 (*((REG32_PTR_T)(WHEEL_BASE + 0x10))) +#define WHEELINT (*((REG32_PTR_T)(WHEEL_BASE + 0x14))) +#define WHEELRX (*((REG32_PTR_T)(WHEEL_BASE + 0x18))) +#define WHEELTX (*((REG32_PTR_T)(WHEEL_BASE + 0x1C))) #endif /* Synopsys OTG - S5L8701 only */ @@ -1331,199 +1301,212 @@ #if CONFIG_CPU==S5L8702 /////INTERRUPT CONTROLLERS///// -#define VICIRQSTATUS(v) (*((REG32_PTR_T)(0x38E00000 + 0x1000 * (v)))) -#define VICFIQSTATUS(v) (*((REG32_PTR_T)(0x38E00004 + 0x1000 * (v)))) -#define VICRAWINTR(v) (*((REG32_PTR_T)(0x38E00008 + 0x1000 * (v)))) -#define VICINTSELECT(v) (*((REG32_PTR_T)(0x38E0000C + 0x1000 * (v)))) -#define VICINTENABLE(v) (*((REG32_PTR_T)(0x38E00010 + 0x1000 * (v)))) -#define VICINTENCLEAR(v) (*((REG32_PTR_T)(0x38E00014 + 0x1000 * (v)))) -#define VICSOFTINT(v) (*((REG32_PTR_T)(0x38E00018 + 0x1000 * (v)))) -#define VICSOFTINTCLEAR(v) (*((REG32_PTR_T)(0x38E0001C + 0x1000 * (v)))) -#define VICPROTECTION(v) (*((REG32_PTR_T)(0x38E00020 + 0x1000 * (v)))) -#define VICSWPRIORITYMASK(v) (*((REG32_PTR_T)(0x38E00024 + 0x1000 * (v)))) -#define VICPRIORITYDAISY(v) (*((REG32_PTR_T)(0x38E00028 + 0x1000 * (v)))) -#define VICVECTADDR(v, i) (*((REG32_PTR_T)(0x38E00100 + 0x1000 * (v) + 4 * (i)))) -#define VICVECTPRIORITY(v, i) (*((REG32_PTR_T)(0x38E00200 + 0x1000 * (v) + 4 * (i)))) -#define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v)))) -#define VIC0IRQSTATUS (*((REG32_PTR_T)(0x38E00000))) -#define VIC0FIQSTATUS (*((REG32_PTR_T)(0x38E00004))) -#define VIC0RAWINTR (*((REG32_PTR_T)(0x38E00008))) -#define VIC0INTSELECT (*((REG32_PTR_T)(0x38E0000C))) -#define VIC0INTENABLE (*((REG32_PTR_T)(0x38E00010))) -#define VIC0INTENCLEAR (*((REG32_PTR_T)(0x38E00014))) -#define VIC0SOFTINT (*((REG32_PTR_T)(0x38E00018))) -#define VIC0SOFTINTCLEAR (*((REG32_PTR_T)(0x38E0001C))) -#define VIC0PROTECTION (*((REG32_PTR_T)(0x38E00020))) -#define VIC0SWPRIORITYMASK (*((REG32_PTR_T)(0x38E00024))) -#define VIC0PRIORITYDAISY (*((REG32_PTR_T)(0x38E00028))) -#define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i)))) -#define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100))) -#define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104))) -#define VIC0VECTADDR2 (*((const void* volatile*)(0x38E00108))) -#define VIC0VECTADDR3 (*((const void* volatile*)(0x38E0010C))) -#define VIC0VECTADDR4 (*((const void* volatile*)(0x38E00110))) -#define VIC0VECTADDR5 (*((const void* volatile*)(0x38E00114))) -#define VIC0VECTADDR6 (*((const void* volatile*)(0x38E00118))) -#define VIC0VECTADDR7 (*((const void* volatile*)(0x38E0011C))) -#define VIC0VECTADDR8 (*((const void* volatile*)(0x38E00120))) -#define VIC0VECTADDR9 (*((const void* volatile*)(0x38E00124))) -#define VIC0VECTADDR10 (*((const void* volatile*)(0x38E00128))) -#define VIC0VECTADDR11 (*((const void* volatile*)(0x38E0012C))) -#define VIC0VECTADDR12 (*((const void* volatile*)(0x38E00130))) -#define VIC0VECTADDR13 (*((const void* volatile*)(0x38E00134))) -#define VIC0VECTADDR14 (*((const void* volatile*)(0x38E00138))) -#define VIC0VECTADDR15 (*((const void* volatile*)(0x38E0013C))) -#define VIC0VECTADDR16 (*((const void* volatile*)(0x38E00140))) -#define VIC0VECTADDR17 (*((const void* volatile*)(0x38E00144))) -#define VIC0VECTADDR18 (*((const void* volatile*)(0x38E00148))) -#define VIC0VECTADDR19 (*((const void* volatile*)(0x38E0014C))) -#define VIC0VECTADDR20 (*((const void* volatile*)(0x38E00150))) -#define VIC0VECTADDR21 (*((const void* volatile*)(0x38E00154))) -#define VIC0VECTADDR22 (*((const void* volatile*)(0x38E00158))) -#define VIC0VECTADDR23 (*((const void* volatile*)(0x38E0015C))) -#define VIC0VECTADDR24 (*((const void* volatile*)(0x38E00160))) -#define VIC0VECTADDR25 (*((const void* volatile*)(0x38E00164))) -#define VIC0VECTADDR26 (*((const void* volatile*)(0x38E00168))) -#define VIC0VECTADDR27 (*((const void* volatile*)(0x38E0016C))) -#define VIC0VECTADDR28 (*((const void* volatile*)(0x38E00170))) -#define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174))) -#define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178))) -#define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C))) -#define VIC0VECTPRIORITY(i) (*((REG32_PTR_T)(0x38E00200 + 4 * (i)))) -#define VIC0VECTPRIORITY0 (*((REG32_PTR_T)(0x38E00200))) -#define VIC0VECTPRIORITY1 (*((REG32_PTR_T)(0x38E00204))) -#define VIC0VECTPRIORITY2 (*((REG32_PTR_T)(0x38E00208))) -#define VIC0VECTPRIORITY3 (*((REG32_PTR_T)(0x38E0020C))) -#define VIC0VECTPRIORITY4 (*((REG32_PTR_T)(0x38E00210))) -#define VIC0VECTPRIORITY5 (*((REG32_PTR_T)(0x38E00214))) -#define VIC0VECTPRIORITY6 (*((REG32_PTR_T)(0x38E00218))) -#define VIC0VECTPRIORITY7 (*((REG32_PTR_T)(0x38E0021C))) -#define VIC0VECTPRIORITY8 (*((REG32_PTR_T)(0x38E00220))) -#define VIC0VECTPRIORITY9 (*((REG32_PTR_T)(0x38E00224))) -#define VIC0VECTPRIORITY10 (*((REG32_PTR_T)(0x38E00228))) -#define VIC0VECTPRIORITY11 (*((REG32_PTR_T)(0x38E0022C))) -#define VIC0VECTPRIORITY12 (*((REG32_PTR_T)(0x38E00230))) -#define VIC0VECTPRIORITY13 (*((REG32_PTR_T)(0x38E00234))) -#define VIC0VECTPRIORITY14 (*((REG32_PTR_T)(0x38E00238))) -#define VIC0VECTPRIORITY15 (*((REG32_PTR_T)(0x38E0023C))) -#define VIC0VECTPRIORITY16 (*((REG32_PTR_T)(0x38E00240))) -#define VIC0VECTPRIORITY17 (*((REG32_PTR_T)(0x38E00244))) -#define VIC0VECTPRIORITY18 (*((REG32_PTR_T)(0x38E00248))) -#define VIC0VECTPRIORITY19 (*((REG32_PTR_T)(0x38E0024C))) -#define VIC0VECTPRIORITY20 (*((REG32_PTR_T)(0x38E00250))) -#define VIC0VECTPRIORITY21 (*((REG32_PTR_T)(0x38E00254))) -#define VIC0VECTPRIORITY22 (*((REG32_PTR_T)(0x38E00258))) -#define VIC0VECTPRIORITY23 (*((REG32_PTR_T)(0x38E0025C))) -#define VIC0VECTPRIORITY24 (*((REG32_PTR_T)(0x38E00260))) -#define VIC0VECTPRIORITY25 (*((REG32_PTR_T)(0x38E00264))) -#define VIC0VECTPRIORITY26 (*((REG32_PTR_T)(0x38E00268))) -#define VIC0VECTPRIORITY27 (*((REG32_PTR_T)(0x38E0026C))) -#define VIC0VECTPRIORITY28 (*((REG32_PTR_T)(0x38E00270))) -#define VIC0VECTPRIORITY29 (*((REG32_PTR_T)(0x38E00274))) -#define VIC0VECTPRIORITY30 (*((REG32_PTR_T)(0x38E00278))) -#define VIC0VECTPRIORITY31 (*((REG32_PTR_T)(0x38E0027C))) -#define VIC0ADDRESS (*((void* volatile*)(0x38E00F00))) -#define VIC1IRQSTATUS (*((REG32_PTR_T)(0x38E01000))) -#define VIC1FIQSTATUS (*((REG32_PTR_T)(0x38E01004))) -#define VIC1RAWINTR (*((REG32_PTR_T)(0x38E01008))) -#define VIC1INTSELECT (*((REG32_PTR_T)(0x38E0100C))) -#define VIC1INTENABLE (*((REG32_PTR_T)(0x38E01010))) -#define VIC1INTENCLEAR (*((REG32_PTR_T)(0x38E01014))) -#define VIC1SOFTINT (*((REG32_PTR_T)(0x38E01018))) -#define VIC1SOFTINTCLEAR (*((REG32_PTR_T)(0x38E0101C))) -#define VIC1PROTECTION (*((REG32_PTR_T)(0x38E01020))) -#define VIC1SWPRIORITYMASK (*((REG32_PTR_T)(0x38E01024))) -#define VIC1PRIORITYDAISY (*((REG32_PTR_T)(0x38E01028))) -#define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i)))) -#define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100))) -#define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104))) -#define VIC1VECTADDR2 (*((const void* volatile*)(0x38E01108))) -#define VIC1VECTADDR3 (*((const void* volatile*)(0x38E0110C))) -#define VIC1VECTADDR4 (*((const void* volatile*)(0x38E01110))) -#define VIC1VECTADDR5 (*((const void* volatile*)(0x38E01114))) -#define VIC1VECTADDR6 (*((const void* volatile*)(0x38E01118))) -#define VIC1VECTADDR7 (*((const void* volatile*)(0x38E0111C))) -#define VIC1VECTADDR8 (*((const void* volatile*)(0x38E01120))) -#define VIC1VECTADDR9 (*((const void* volatile*)(0x38E01124))) -#define VIC1VECTADDR10 (*((const void* volatile*)(0x38E01128))) -#define VIC1VECTADDR11 (*((const void* volatile*)(0x38E0112C))) -#define VIC1VECTADDR12 (*((const void* volatile*)(0x38E01130))) -#define VIC1VECTADDR13 (*((const void* volatile*)(0x38E01134))) -#define VIC1VECTADDR14 (*((const void* volatile*)(0x38E01138))) -#define VIC1VECTADDR15 (*((const void* volatile*)(0x38E0113C))) -#define VIC1VECTADDR16 (*((const void* volatile*)(0x38E01140))) -#define VIC1VECTADDR17 (*((const void* volatile*)(0x38E01144))) -#define VIC1VECTADDR18 (*((const void* volatile*)(0x38E01148))) -#define VIC1VECTADDR19 (*((const void* volatile*)(0x38E0114C))) -#define VIC1VECTADDR20 (*((const void* volatile*)(0x38E01150))) -#define VIC1VECTADDR21 (*((const void* volatile*)(0x38E01154))) -#define VIC1VECTADDR22 (*((const void* volatile*)(0x38E01158))) -#define VIC1VECTADDR23 (*((const void* volatile*)(0x38E0115C))) -#define VIC1VECTADDR24 (*((const void* volatile*)(0x38E01160))) -#define VIC1VECTADDR25 (*((const void* volatile*)(0x38E01164))) -#define VIC1VECTADDR26 (*((const void* volatile*)(0x38E01168))) -#define VIC1VECTADDR27 (*((const void* volatile*)(0x38E0116C))) -#define VIC1VECTADDR28 (*((const void* volatile*)(0x38E01170))) -#define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174))) -#define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178))) -#define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C))) -#define VIC1VECTPRIORITY(i) (*((REG32_PTR_T)(0x38E01200 + 4 * (i)))) -#define VIC1VECTPRIORITY0 (*((REG32_PTR_T)(0x38E01200))) -#define VIC1VECTPRIORITY1 (*((REG32_PTR_T)(0x38E01204))) -#define VIC1VECTPRIORITY2 (*((REG32_PTR_T)(0x38E01208))) -#define VIC1VECTPRIORITY3 (*((REG32_PTR_T)(0x38E0120C))) -#define VIC1VECTPRIORITY4 (*((REG32_PTR_T)(0x38E01210))) -#define VIC1VECTPRIORITY5 (*((REG32_PTR_T)(0x38E01214))) -#define VIC1VECTPRIORITY6 (*((REG32_PTR_T)(0x38E01218))) -#define VIC1VECTPRIORITY7 (*((REG32_PTR_T)(0x38E0121C))) -#define VIC1VECTPRIORITY8 (*((REG32_PTR_T)(0x38E01220))) -#define VIC1VECTPRIORITY9 (*((REG32_PTR_T)(0x38E01224))) -#define VIC1VECTPRIORITY10 (*((REG32_PTR_T)(0x38E01228))) -#define VIC1VECTPRIORITY11 (*((REG32_PTR_T)(0x38E0122C))) -#define VIC1VECTPRIORITY12 (*((REG32_PTR_T)(0x38E01230))) -#define VIC1VECTPRIORITY13 (*((REG32_PTR_T)(0x38E01234))) -#define VIC1VECTPRIORITY14 (*((REG32_PTR_T)(0x38E01238))) -#define VIC1VECTPRIORITY15 (*((REG32_PTR_T)(0x38E0123C))) -#define VIC1VECTPRIORITY16 (*((REG32_PTR_T)(0x38E01240))) -#define VIC1VECTPRIORITY17 (*((REG32_PTR_T)(0x38E01244))) -#define VIC1VECTPRIORITY18 (*((REG32_PTR_T)(0x38E01248))) -#define VIC1VECTPRIORITY19 (*((REG32_PTR_T)(0x38E0124C))) -#define VIC1VECTPRIORITY20 (*((REG32_PTR_T)(0x38E01250))) -#define VIC1VECTPRIORITY21 (*((REG32_PTR_T)(0x38E01254))) -#define VIC1VECTPRIORITY22 (*((REG32_PTR_T)(0x38E01258))) -#define VIC1VECTPRIORITY23 (*((REG32_PTR_T)(0x38E0125C))) -#define VIC1VECTPRIORITY24 (*((REG32_PTR_T)(0x38E01260))) -#define VIC1VECTPRIORITY25 (*((REG32_PTR_T)(0x38E01264))) -#define VIC1VECTPRIORITY26 (*((REG32_PTR_T)(0x38E01268))) -#define VIC1VECTPRIORITY27 (*((REG32_PTR_T)(0x38E0126C))) -#define VIC1VECTPRIORITY28 (*((REG32_PTR_T)(0x38E01270))) -#define VIC1VECTPRIORITY29 (*((REG32_PTR_T)(0x38E01274))) -#define VIC1VECTPRIORITY30 (*((REG32_PTR_T)(0x38E01278))) -#define VIC1VECTPRIORITY31 (*((REG32_PTR_T)(0x38E0127C))) -#define VIC1ADDRESS (*((void* volatile*)(0x38E01F00))) +#define VIC_BASE 0x38E00000 +#define VIC_OFFSET 0x1000 + +#define VICBASE(v) (VIC_BASE + VIC_OFFSET * (v)) + +#define VICIRQSTATUS(v) (*((REG32_PTR_T)(VICBASE(v)))) +#define VICFIQSTATUS(v) (*((REG32_PTR_T)(VICBASE(v) + 0x04))) +#define VICRAWINTR(v) (*((REG32_PTR_T)(VICBASE(v) + 0x08))) +#define VICINTSELECT(v) (*((REG32_PTR_T)(VICBASE(v) + 0x0C))) +#define VICINTENABLE(v) (*((REG32_PTR_T)(VICBASE(v) + 0x10))) +#define VICINTENCLEAR(v) (*((REG32_PTR_T)(VICBASE(v) + 0x14))) +#define VICSOFTINT(v) (*((REG32_PTR_T)(VICBASE(v) + 0x18))) +#define VICSOFTINTCLEAR(v) (*((REG32_PTR_T)(VICBASE(v) + 0x1C))) +#define VICPROTECTION(v) (*((REG32_PTR_T)(VICBASE(v) + 0x20))) +#define VICSWPRIORITYMASK(v) (*((REG32_PTR_T)(VICBASE(v) + 0x24))) +#define VICPRIORITYDAISY(v) (*((REG32_PTR_T)(VICBASE(v) + 0x28))) +#define VICVECTADDR(v, i) (*((REG32_PTR_T)(VICBASE(v) + 0x100 + 4 * (i)))) +#define VICVECTPRIORITY(v, i) (*((REG32_PTR_T)(VICBASE(v) + 0x200 + 4 * (i)))) +#define VICADDRESS(v) (*((CONST_VOID_PTR_PTR_T)(VICBASE(v) + 0xF00))) + +#define VIC0IRQSTATUS VICIRQSTATUS(0) +#define VIC0FIQSTATUS VICFIQSTATUS(0) +#define VIC0RAWINTR VICRAWINTR(0) +#define VIC0INTSELECT VICINTSELECT(0) +#define VIC0INTENABLE VICINTENABLE(0) +#define VIC0INTENCLEAR VICINTENCLEAR(0) +#define VIC0SOFTINT VICSOFTINT(0) +#define VIC0SOFTINTCLEAR VICSOFTINTCLEAR(0) +#define VIC0PROTECTION VICPROTECTION(0) +#define VIC0SWPRIORITYMASK VICSWPRIORITYMASK(0) +#define VIC0PRIORITYDAISY VICPRIORITYDAISY(0) + +#define VIC0VECTADDR(i) VICVECTADDR(0, i) +#define VIC0VECTADDR0 VIC0VECTADDR(0) +#define VIC0VECTADDR1 VIC0VECTADDR(1) +#define VIC0VECTADDR2 VIC0VECTADDR(2) +#define VIC0VECTADDR3 VIC0VECTADDR(3) +#define VIC0VECTADDR4 VIC0VECTADDR(4) +#define VIC0VECTADDR5 VIC0VECTADDR(5) +#define VIC0VECTADDR6 VIC0VECTADDR(6) +#define VIC0VECTADDR7 VIC0VECTADDR(7) +#define VIC0VECTADDR8 VIC0VECTADDR(8) +#define VIC0VECTADDR9 VIC0VECTADDR(9) +#define VIC0VECTADDR10 VIC0VECTADDR(10) +#define VIC0VECTADDR11 VIC0VECTADDR(11) +#define VIC0VECTADDR12 VIC0VECTADDR(12) +#define VIC0VECTADDR13 VIC0VECTADDR(13) +#define VIC0VECTADDR14 VIC0VECTADDR(14) +#define VIC0VECTADDR15 VIC0VECTADDR(15) +#define VIC0VECTADDR16 VIC0VECTADDR(16) +#define VIC0VECTADDR17 VIC0VECTADDR(17) +#define VIC0VECTADDR18 VIC0VECTADDR(18) +#define VIC0VECTADDR19 VIC0VECTADDR(19) +#define VIC0VECTADDR20 VIC0VECTADDR(20) +#define VIC0VECTADDR21 VIC0VECTADDR(21) +#define VIC0VECTADDR22 VIC0VECTADDR(22) +#define VIC0VECTADDR23 VIC0VECTADDR(23) +#define VIC0VECTADDR24 VIC0VECTADDR(24) +#define VIC0VECTADDR25 VIC0VECTADDR(25) +#define VIC0VECTADDR26 VIC0VECTADDR(26) +#define VIC0VECTADDR27 VIC0VECTADDR(27) +#define VIC0VECTADDR28 VIC0VECTADDR(28) +#define VIC0VECTADDR29 VIC0VECTADDR(29) +#define VIC0VECTADDR30 VIC0VECTADDR(30) +#define VIC0VECTADDR31 VIC0VECTADDR(31) + +#define VIC0VECTPRIORITY(i) VICVECTPRIORITY(0, i) +#define VIC0VECTPRIORITY0 VIC0VECTPRIORITY(0) +#define VIC0VECTPRIORITY1 VIC0VECTPRIORITY(1) +#define VIC0VECTPRIORITY2 VIC0VECTPRIORITY(2) +#define VIC0VECTPRIORITY3 VIC0VECTPRIORITY(3) +#define VIC0VECTPRIORITY4 VIC0VECTPRIORITY(4) +#define VIC0VECTPRIORITY5 VIC0VECTPRIORITY(5) +#define VIC0VECTPRIORITY6 VIC0VECTPRIORITY(6) +#define VIC0VECTPRIORITY7 VIC0VECTPRIORITY(7) +#define VIC0VECTPRIORITY8 VIC0VECTPRIORITY(8) +#define VIC0VECTPRIORITY9 VIC0VECTPRIORITY(9) +#define VIC0VECTPRIORITY10 VIC0VECTPRIORITY(10) +#define VIC0VECTPRIORITY11 VIC0VECTPRIORITY(11) +#define VIC0VECTPRIORITY12 VIC0VECTPRIORITY(12) +#define VIC0VECTPRIORITY13 VIC0VECTPRIORITY(13) +#define VIC0VECTPRIORITY14 VIC0VECTPRIORITY(14) +#define VIC0VECTPRIORITY15 VIC0VECTPRIORITY(15) +#define VIC0VECTPRIORITY16 VIC0VECTPRIORITY(16) +#define VIC0VECTPRIORITY17 VIC0VECTPRIORITY(17) +#define VIC0VECTPRIORITY18 VIC0VECTPRIORITY(18) +#define VIC0VECTPRIORITY19 VIC0VECTPRIORITY(19) +#define VIC0VECTPRIORITY20 VIC0VECTPRIORITY(20) +#define VIC0VECTPRIORITY21 VIC0VECTPRIORITY(21) +#define VIC0VECTPRIORITY22 VIC0VECTPRIORITY(22) +#define VIC0VECTPRIORITY23 VIC0VECTPRIORITY(23) +#define VIC0VECTPRIORITY24 VIC0VECTPRIORITY(24) +#define VIC0VECTPRIORITY25 VIC0VECTPRIORITY(25) +#define VIC0VECTPRIORITY26 VIC0VECTPRIORITY(26) +#define VIC0VECTPRIORITY27 VIC0VECTPRIORITY(27) +#define VIC0VECTPRIORITY28 VIC0VECTPRIORITY(28) +#define VIC0VECTPRIORITY29 VIC0VECTPRIORITY(29) +#define VIC0VECTPRIORITY30 VIC0VECTPRIORITY(30) +#define VIC0VECTPRIORITY31 VIC0VECTPRIORITY(31) + +#define VIC0ADDRESS VICADDRESS(0) + +#define VIC1IRQSTATUS VICIRQSTATUS(1) +#define VIC1FIQSTATUS VICFIQSTATUS(1) +#define VIC1RAWINTR VICRAWINTR(1) +#define VIC1INTSELECT VICINTSELECT(1) +#define VIC1INTENABLE VICINTENABLE(1) +#define VIC1INTENCLEAR VICINTENCLEAR(1) +#define VIC1SOFTINT VICSOFTINT(1) +#define VIC1SOFTINTCLEAR VICSOFTINTCLEAR(1) +#define VIC1PROTECTION VICPROTECTION(1) +#define VIC1SWPRIORITYMASK VICSWPRIORITYMASK(1) +#define VIC1PRIORITYDAISY VICPRIORITYDAISY(1) + +#define VIC1VECTADDR(i) VICVECTADDR(1, i) +#define VIC1VECTADDR0 VIC1VECTADDR(0) +#define VIC1VECTADDR1 VIC1VECTADDR(1) +#define VIC1VECTADDR2 VIC1VECTADDR(2) +#define VIC1VECTADDR3 VIC1VECTADDR(3) +#define VIC1VECTADDR4 VIC1VECTADDR(4) +#define VIC1VECTADDR5 VIC1VECTADDR(5) +#define VIC1VECTADDR6 VIC1VECTADDR(6) +#define VIC1VECTADDR7 VIC1VECTADDR(7) +#define VIC1VECTADDR8 VIC1VECTADDR(8) +#define VIC1VECTADDR9 VIC1VECTADDR(9) +#define VIC1VECTADDR10 VIC1VECTADDR(10) +#define VIC1VECTADDR11 VIC1VECTADDR(11) +#define VIC1VECTADDR12 VIC1VECTADDR(12) +#define VIC1VECTADDR13 VIC1VECTADDR(13) +#define VIC1VECTADDR14 VIC1VECTADDR(14) +#define VIC1VECTADDR15 VIC1VECTADDR(15) +#define VIC1VECTADDR16 VIC1VECTADDR(16) +#define VIC1VECTADDR17 VIC1VECTADDR(17) +#define VIC1VECTADDR18 VIC1VECTADDR(18) +#define VIC1VECTADDR19 VIC1VECTADDR(19) +#define VIC1VECTADDR20 VIC1VECTADDR(20) +#define VIC1VECTADDR21 VIC1VECTADDR(21) +#define VIC1VECTADDR22 VIC1VECTADDR(22) +#define VIC1VECTADDR23 VIC1VECTADDR(23) +#define VIC1VECTADDR24 VIC1VECTADDR(24) +#define VIC1VECTADDR25 VIC1VECTADDR(25) +#define VIC1VECTADDR26 VIC1VECTADDR(26) +#define VIC1VECTADDR27 VIC1VECTADDR(27) +#define VIC1VECTADDR28 VIC1VECTADDR(28) +#define VIC1VECTADDR29 VIC1VECTADDR(29) +#define VIC1VECTADDR30 VIC1VECTADDR(30) +#define VIC1VECTADDR31 VIC1VECTADDR(31) + +#define VIC1VECTPRIORITY(i) VICVECTPRIORITY(1, i) +#define VIC1VECTPRIORITY0 VIC1VECTPRIORITY(0) +#define VIC1VECTPRIORITY1 VIC1VECTPRIORITY(1) +#define VIC1VECTPRIORITY2 VIC1VECTPRIORITY(2) +#define VIC1VECTPRIORITY3 VIC1VECTPRIORITY(3) +#define VIC1VECTPRIORITY4 VIC1VECTPRIORITY(4) +#define VIC1VECTPRIORITY5 VIC1VECTPRIORITY(5) +#define VIC1VECTPRIORITY6 VIC1VECTPRIORITY(6) +#define VIC1VECTPRIORITY7 VIC1VECTPRIORITY(7) +#define VIC1VECTPRIORITY8 VIC1VECTPRIORITY(8) +#define VIC1VECTPRIORITY9 VIC1VECTPRIORITY(9) +#define VIC1VECTPRIORITY10 VIC1VECTPRIORITY(10) +#define VIC1VECTPRIORITY11 VIC1VECTPRIORITY(11) +#define VIC1VECTPRIORITY12 VIC1VECTPRIORITY(12) +#define VIC1VECTPRIORITY13 VIC1VECTPRIORITY(13) +#define VIC1VECTPRIORITY14 VIC1VECTPRIORITY(14) +#define VIC1VECTPRIORITY15 VIC1VECTPRIORITY(15) +#define VIC1VECTPRIORITY16 VIC1VECTPRIORITY(16) +#define VIC1VECTPRIORITY17 VIC1VECTPRIORITY(17) +#define VIC1VECTPRIORITY18 VIC1VECTPRIORITY(18) +#define VIC1VECTPRIORITY19 VIC1VECTPRIORITY(19) +#define VIC1VECTPRIORITY20 VIC1VECTPRIORITY(20) +#define VIC1VECTPRIORITY21 VIC1VECTPRIORITY(21) +#define VIC1VECTPRIORITY22 VIC1VECTPRIORITY(22) +#define VIC1VECTPRIORITY23 VIC1VECTPRIORITY(23) +#define VIC1VECTPRIORITY24 VIC1VECTPRIORITY(24) +#define VIC1VECTPRIORITY25 VIC1VECTPRIORITY(25) +#define VIC1VECTPRIORITY26 VIC1VECTPRIORITY(26) +#define VIC1VECTPRIORITY27 VIC1VECTPRIORITY(27) +#define VIC1VECTPRIORITY28 VIC1VECTPRIORITY(28) +#define VIC1VECTPRIORITY29 VIC1VECTPRIORITY(29) +#define VIC1VECTPRIORITY30 VIC1VECTPRIORITY(30) +#define VIC1VECTPRIORITY31 VIC1VECTPRIORITY(31) + +#define VIC1ADDRESS VICADDRESS(1) /////INTERRUPTS///// #define IRQ_TIMER32 7 #define IRQ_TIMER 8 #define IRQ_SPI(i) (9+(i)) /* TBC */ -#define IRQ_SPI0 9 -#define IRQ_SPI1 10 -#define IRQ_SPI2 11 +#define IRQ_SPI0 IRQ_SPI(0) +#define IRQ_SPI1 IRQ_SPI(1) +#define IRQ_SPI2 IRQ_SPI(2) #define IRQ_LCD 14 #define IRQ_DMAC(d) (16+(d)) -#define IRQ_DMAC0 16 -#define IRQ_DMAC1 17 +#define IRQ_DMAC0 IRQ_DMAC(0) +#define IRQ_DMAC1 IRQ_DMAC(1) #define IRQ_USB_FUNC 19 #define IRQ_I2C(i) (21+(i)) -#define IRQ_I2C0 21 -#define IRQ_I2C1 22 +#define IRQ_I2C0 IRQ_I2C(0) +#define IRQ_I2C1 IRQ_I2C(1) #define IRQ_WHEEL 23 #define IRQ_UART(i) (24+(i)) -#define IRQ_UART0 24 -#define IRQ_UART1 25 -#define IRQ_UART2 26 -#define IRQ_UART3 27 -#define IRQ_UART4 28 /* obsolete/not implemented on s5l8702 ??? */ +#define IRQ_UART0 IRQ_UART(0) +#define IRQ_UART1 IRQ_UART(1) +#define IRQ_UART2 IRQ_UART(2) +#define IRQ_UART3 IRQ_UART(3) +#define IRQ_UART4 IRQ_UART(4) /* obsolete/not implemented on s5l8702 ??? */ #define IRQ_ATA 29 #define IRQ_SBOOT 36 #define IRQ_AES 39 @@ -1539,4 +1522,4 @@ #define IRQ_EXT6 33 #endif -#endif /* __S5L8700_H__ */ +#endif /* __S5L87XX_H__ */ diff --git a/firmware/target/arm/ipod/button-clickwheel.c b/firmware/target/arm/ipod/button-clickwheel.c index 508b03a9f0..90c08532b7 100644 --- a/firmware/target/arm/ipod/button-clickwheel.c +++ b/firmware/target/arm/ipod/button-clickwheel.c @@ -381,7 +381,7 @@ static void s5l_clickwheel_init(void) PDAT10 &= ~2; #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 clockgate_enable(CLOCKGATE_CWHEEL, true); - PCONE = (PCONE & ~0x00ffff00) | 0x00222200; + PCON14 = (PCON14 & ~0x00ffff00) | 0x00222200; WHEEL00 = 0; /* stop s5l8702 controller */ WHEELINT = 7; WHEEL10 = 1; @@ -420,7 +420,7 @@ bool headphones_inserted(void) #if CONFIG_CPU==S5L8701 return ((PDAT14 & (1 << 5)) != 0); #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 - return ((PDATA & (1 << 6)) != 0); + return ((PDAT10 & (1 << 6)) != 0); #endif } #endif @@ -455,7 +455,7 @@ int button_read_device(void) PWRCONEXT |= 1; #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 WHEEL00 = 0; - PCONE = (PCONE & ~0x00ffff00) | 0x000e0e00; + PCON14 = (PCON14 & ~0x00ffff00) | 0x000e0e00; clockgate_enable(CLOCKGATE_CWHEEL, false); #endif } diff --git a/firmware/target/arm/s5l8702/ipod6g/power-6g.c b/firmware/target/arm/s5l8702/ipod6g/power-6g.c index b609491830..8a5331dc6e 100644 --- a/firmware/target/arm/s5l8702/ipod6g/power-6g.c +++ b/firmware/target/arm/s5l8702/ipod6g/power-6g.c @@ -72,7 +72,7 @@ void power_init(void) * is not present or it is insufficient or limited, * additional required power is drained from battery. */ - PCONB = (PCONB & 0x000000ff) + PCON11 = (PCON11 & 0x000000ff) | (0xe << 8) /* route D+ to ADC2: off */ | (0xe << 12) /* route D- to ADC2: off */ | (0x0 << 16) /* USB related input, POL pin ??? */ @@ -80,7 +80,7 @@ void power_init(void) | (0xe << 24) /* HPWR: 100mA */ | (0xe << 28); /* USB suspend: off */ - PCONC = (PCONC & 0xffff0000) + PCON12 = (PCON12 & 0xffff0000) | (0xe << 0) /* double HPWR limit: off */ | (0xe << 4) /* disable battery charge: off */ | (0xe << 8) /* disable battery charge: off */ diff --git a/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c b/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c index 55247ee736..fabc0f869b 100644 --- a/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c +++ b/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c @@ -678,11 +678,11 @@ static int ata_power_up(void) *((uint32_t volatile*)0x3cf0010c) = 0xff; SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK | SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14; - SDCI_CDIV = SDCI_CDIV_CLKDIV(260); + SDCI_CLKDIV = SDCI_CDIV_CLKDIV(260); *((uint32_t volatile*)0x3cf00200) = 0xb000f; SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT; PASS_RC(mmc_init(), 3, 0); - SDCI_CDIV = SDCI_CDIV_CLKDIV(4); + SDCI_CLKDIV = SDCI_CDIV_CLKDIV(4); sleep(HZ / 100); PASS_RC(ceata_init(8), 3, 1); PASS_RC(ata_identify(identify_info), 3, 2); diff --git a/firmware/target/arm/s5l8702/spi-s5l8702.c b/firmware/target/arm/s5l8702/spi-s5l8702.c index f9712e9b44..4c0a409c67 100644 --- a/firmware/target/arm/s5l8702/spi-s5l8702.c +++ b/firmware/target/arm/s5l8702/spi-s5l8702.c @@ -51,8 +51,8 @@ void spi_init(int port, bool state) PCON6 = (PCON6 & ~0xffff0000) | (val << 16); break; case 2: - PCONE = (PCONE & ~0xff000000) | (val << 24); - PCONF = (PCONF & ~0xff) | (val >> 8); + PCON14 = (PCON14 & ~0xff000000) | (val << 24); + PCON15 = (PCON15 & ~0xff) | (val >> 8); break; } } diff --git a/firmware/target/arm/s5l8702/system-s5l8702.c b/firmware/target/arm/s5l8702/system-s5l8702.c index 814a723f22..bba1ba4207 100644 --- a/firmware/target/arm/s5l8702/system-s5l8702.c +++ b/firmware/target/arm/s5l8702/system-s5l8702.c @@ -157,9 +157,10 @@ void irq_handler(void) asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */ "sub sp, sp, #8 \n"); /* Reserve stack */ - void* dummy = VIC0ADDRESS; - dummy = VIC1ADDRESS; - (void)dummy; + const void* dummy0 = VIC0ADDRESS; + (void)dummy0; + const void* dummy1 = VIC1ADDRESS; + (void)dummy1; uint32_t irqs0 = VIC0IRQSTATUS; uint32_t irqs1 = VIC1IRQSTATUS; for (current_irq = 0; irqs0; current_irq++, irqs0 >>= 1) diff --git a/firmware/target/arm/s5l8702/uart-s5l8702.c b/firmware/target/arm/s5l8702/uart-s5l8702.c index 6db66429ac..6b2866e729 100644 --- a/firmware/target/arm/s5l8702/uart-s5l8702.c +++ b/firmware/target/arm/s5l8702/uart-s5l8702.c @@ -55,7 +55,7 @@ void uart_target_enable_gpio(int uart_id, int port_id) break; case 1: /* configure UART1 GPIO ports, including RTS/CTS signals */ - PCOND = (PCOND & 0xff0000ff) | 0x00222200; + PCON13 = (PCON13 & 0xff0000ff) | 0x00222200; break; case 2: case 3: @@ -74,7 +74,7 @@ void uart_target_disable_gpio(int uart_id, int port_id) PCON0 = (PCON0 & 0xff00ffff) | 0x00ee0000; break; case 1: - PCOND = (PCOND & 0xff0000ff) | 0x00eeee00; + PCON13 = (PCON13 & 0xff0000ff) | 0x00eeee00; break; case 2: case 3: |