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authorBarry Wardell <rockbox@barrywardell.net>2007-02-16 22:13:21 +0000
committerBarry Wardell <rockbox@barrywardell.net>2007-02-16 22:13:21 +0000
commit3a6d4791d70fc9f4adad7a0cbc1b808b7c942652 (patch)
treebf28466309953e530eacbaa0f2c88e0abffa6c9b
parentb045a2425c4f7d2e9c9853c01897b1ba0dd6ae01 (diff)
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No functional changes, just reorganising code:
1) Move ARC OTG USB (used in PP502x) driver code into it's own file, drivers/arcotg_udc.c. Hopefully in the future we will be able to adapt more of the Linux driver and add it to this file. 2) Rename mx31.h to arcotg_udc.h to reflect the file the code came from. It's also a more accurate name for the USB controller. 3) Get rid of one more inl()/outl() in usb-pp.c and use the relevant #define instead. 4) Add dr_controller_stop(). Not used yet. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12340 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/SOURCES2
-rw-r--r--firmware/drivers/arcotg_udc.c135
-rw-r--r--firmware/export/arcotg_udc.h (renamed from firmware/export/mx31.h)174
-rw-r--r--firmware/export/pp5020.h3
-rw-r--r--firmware/target/arm/usb-pp.c103
5 files changed, 217 insertions, 200 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index d4447c22cc..9842689544 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -212,6 +212,8 @@ drivers/tlv320.c
drivers/isp1362.c
#elif CONFIG_USBOTG == USBOTG_M5636
drivers/m5636.c
+#elif CONFIG_USBOTG == USBOTG_ARC
+drivers/arcotg_udc.c
#endif /* CONFIG_USBOTG */
#endif /* !defined(SIMULATOR) && !defined(BOOTLOADER) */
diff --git a/firmware/drivers/arcotg_udc.c b/firmware/drivers/arcotg_udc.c
new file mode 100644
index 0000000000..d39dbc39df
--- /dev/null
+++ b/firmware/drivers/arcotg_udc.c
@@ -0,0 +1,135 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2007 by Barry Wardell
+ *
+ * Based on code from the Linux Target Image Builder from Freescale
+ * available at http://www.bitshrine.org/ and
+ * http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch
+ * Adapted for Rockbox in January 2007
+ * Original file: drivers/usb/gadget/arcotg_udc.c
+ *
+ * USB Device Controller Driver
+ * Driver for ARC OTG USB module in the i.MX31 platform, etc.
+ *
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Based on mpc-udc.h
+ * Author: Li Yang (leoli@freescale.com)
+ * Jiang Bo (Tanya.jiang@freescale.com)
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "arcotg_udc.h"
+#include "logf.h"
+
+static int timeout;
+
+/* @qh_addr is the aligned virt addr of ep QH addr
+ * it is used to set endpointlistaddr Reg */
+/* was static int dr_controller_setup(void *qh_addr) */
+int dr_controller_setup(void)
+{
+#if 0
+ struct arc_usb_config *config;
+
+ config = udc_controller->config;
+
+ /* before here, make sure usb_slave_regs has been initialized */
+ if (!qh_addr)
+ return -EINVAL;
+#endif
+
+ /* Stop and reset the usb controller */
+ UDC_USBCMD &= ~USB_CMD_RUN_STOP;
+
+ UDC_USBCMD |= USB_CMD_CTRL_RESET;
+
+ /* Wait for reset to complete */
+ timeout = 10000000;
+ while ((UDC_USBCMD & USB_CMD_CTRL_RESET) &&
+ --timeout) {
+ continue;
+ }
+ if (timeout == 0) {
+ logf("%s: TIMEOUT", __FUNCTION__);
+ return -ETIMEDOUT;
+ }
+
+ /* Set the controller as device mode and disable setup lockout */
+ UDC_USBMODE |= (USB_MODE_CTRL_MODE_DEVICE | USB_MODE_SETUP_LOCK_OFF);
+
+ /* Clear the setup status */
+ UDC_USBSTS = 0;
+#if 0
+ UDC_ENDPOINTLISTADDR = (unsigned int)qh_addr & USB_EP_LIST_ADDRESS_MASK;
+
+ VDBG("qh_addr=0x%x epla_reg=0x%8x", qh_addr, UOG_ASYNCLISTADDR);
+#endif
+ UDC_PORTSC1 = (UDC_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | PORTSCX_PTS_UTMI;
+#if 0
+ if (config->set_vbus_power)
+ config->set_vbus_power(0);
+#endif
+
+ return 0;
+}
+
+/* just Enable DR irq reg and Set Dr controller Run */
+/* was static void dr_controller_run(struct arcotg_udc *udc) */
+void dr_controller_run(void)
+{
+ /*Enable DR irq reg */
+ UDC_USBINTR = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN |
+ USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN |
+ USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
+#if 0
+ /* Clear stopped bit */
+ udc->stopped = 0;
+#endif
+ /* Set the controller as device mode */
+ UDC_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
+
+ /* Set controller to Run */
+ UDC_USBCMD |= USB_CMD_RUN_STOP;
+
+ return;
+}
+
+/* just Enable DR irq reg and Set Dr controller Run */
+/* was static void dr_controller_stop(struct arcotg_udc *udc) */
+void dr_controller_stop(void)
+{
+#if 0
+ /* if we're in OTG mode, and the Host is currently using the port,
+ * stop now and don't rip the controller out from under the
+ * ehci driver
+ */
+ if (udc->gadget.is_otg) {
+ if (!(UDC_OTGSC & OTGSC_STS_USB_ID)) {
+ logf("Leaving early");
+ return;
+ }
+ }
+#endif
+
+ /* disable all INTR */
+ UDC_USBINTR = 0;
+#if 0
+ /* Set stopped bit */
+ udc->stopped = 1;
+#endif
+ /* Set controller to Stop */
+ UDC_USBCMD &= ~USB_CMD_RUN_STOP;
+}
diff --git a/firmware/export/mx31.h b/firmware/export/arcotg_udc.h
index 5af3bb052a..e3bf93a52e 100644
--- a/firmware/export/mx31.h
+++ b/firmware/export/arcotg_udc.h
@@ -5,12 +5,12 @@
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
- * $Id: $
+ * $Id$
*
* Copyright (C) 2007 by Barry Wardell
*
- * i.MX31 driver based on code from the Linux Target Image Builder from
- * Freescale - http://www.bitshrine.org/ and
+ * ARC OTG USB device driver based on code from the Linux Target Image Builder
+ * from Freescale - http://www.bitshrine.org/ and
* http://www.bitshrine.org/gpp/linux-2.6.16-mx31-usb-2.patch
* Adapted for Rockbox in January 2007
* Original file: drivers/usb/gadget/arcotg_udc.h
@@ -32,119 +32,62 @@
/*
* Freescale USB device/endpoint management registers
*/
-#ifndef __MX31_H
-#define __MX31_H
-
-/* Register addresses - from Freescale i.MX31 reference manual */
-/* The PortalPlayer USB controller usec base address 0xc5000000 */
-#define USB_BASE 0xc5000000
-
-/* OTG */
-#define UOG_ID (*(volatile unsigned int *)(USB_BASE+0x000))
-#define UOG_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x004))
-#define UOG_HWHOST (*(volatile unsigned int *)(USB_BASE+0x008))
-#define UOG_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x010))
-#define UOG_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x014))
-#define UOG_CAPLENGTH (*(volatile unsigned char *)(USB_BASE+0x100))
-#define UOG_HCIVERSION (*(volatile unsigned short *)(USB_BASE+0x102))
-#define UOG_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x104))
-#define UOG_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x108))
-#define UOG_DCIVERSION (*(volatile unsigned short *)(USB_BASE+0x120))
-#define UOG_DCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x124))
-#define UOG_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140))
-#define UOG_USBSTS (*(volatile unsigned int *)(USB_BASE+0x144))
-#define UOG_USBINTR (*(volatile unsigned int *)(USB_BASE+0x148))
-#define UOG_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x14c))
-#define UOG_PERIODICLISTBASE (*(volatile unsigned int *)(USB_BASE+0x154))
-#define UOG_ASYNCLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
-#define UOG_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x160))
-#define UOG_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x164))
-#define UOG_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x170))
-#define UOG_CFGFLAG (*(volatile unsigned int *)(USB_BASE+0x180))
-#define UOG_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184))
-/*#define UOG_PORTSC2 (*(volatile unsigned int *)(USB_BASE+0x188))
-#define UOG_PORTSC3 (*(volatile unsigned int *)(USB_BASE+0x18c))
-#define UOG_PORTSC4 (*(volatile unsigned int *)(USB_BASE+0x190))
-#define UOG_PORTSC5 (*(volatile unsigned int *)(USB_BASE+0x194))
-#define UOG_PORTSC6 (*(volatile unsigned int *)(USB_BASE+0x198))
-#define UOG_PORTSC7 (*(volatile unsigned int *)(USB_BASE+0x19c))
-#define UOG_PORTSC8 (*(volatile unsigned int *)(USB_BASE+0x1a0))*/
-#define UOG_OTGSC (*(volatile unsigned int *)(USB_BASE+0x1a4))
-#define UOG_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8))
-#define UOG_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac))
-#define UOG_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0))
-#define UOG_ENDPTFLUSH (*(volatile unsigned int *)(USB_BASE+0x1b4))
-#define UOG_ENDPTSTAT (*(volatile unsigned int *)(USB_BASE+0x1b8))
-#define UOG_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc))
-#define ENDPTCRTL0 (*(volatile unsigned int *)(USB_BASE+0x1c0))
-#define ENDPTCRTL1 (*(volatile unsigned int *)(USB_BASE+0x1c4))
-#define ENDPTCRTL2 (*(volatile unsigned int *)(USB_BASE+0x1c8))
-#define ENDPTCRTL3 (*(volatile unsigned int *)(USB_BASE+0x1cc))
-#define ENDPTCRTL4 (*(volatile unsigned int *)(USB_BASE+0x1d0))
-#define ENDPTCRTL5 (*(volatile unsigned int *)(USB_BASE+0x1d4))
-#define ENDPTCRTL6 (*(volatile unsigned int *)(USB_BASE+0x1d8))
-#define ENDPTCRTL7 (*(volatile unsigned int *)(USB_BASE+0x1dc))
-/*#define ENDPTCRTL8 (*(volatile unsigned int *)(USB_BASE+0x1e0))
-#define ENDPTCRTL9 (*(volatile unsigned int *)(USB_BASE+0x1e4))
-#define ENDPTCRTL10 (*(volatile unsigned int *)(USB_BASE+0x1e8))
-#define ENDPTCRTL11 (*(volatile unsigned int *)(USB_BASE+0x1ec))
-#define ENDPTCRTL12 (*(volatile unsigned int *)(USB_BASE+0x1f0))
-#define ENDPTCRTL13 (*(volatile unsigned int *)(USB_BASE+0x1f4))
-#define ENDPTCRTL14 (*(volatile unsigned int *)(USB_BASE+0x1f8))
-#define ENDPTCRTL15 (*(volatile unsigned int *)(USB_BASE+0x1fc))*/
-
-/* Host 1 */
-#define UH1_ID (*(volatile unsigned int *)(USB_BASE+0x200))
-#define UH1_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x204))
-#define UH1_HWHOST (*(volatile unsigned int *)(USB_BASE+0x208))
-#define UH1_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x210))
-#define UH1_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x214))
-#define UH1_CAPLENGTH (*(volatile unsigned int *)(USB_BASE+0x300))
-#define UH1_HCIVERSION (*(volatile unsigned int *)(USB_BASE+0x302))
-#define UH1_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x304))
-#define UH1_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x308))
-#define UH1_USBCMD (*(volatile unsigned int *)(USB_BASE+0x340))
-#define UH1_USBSTS (*(volatile unsigned int *)(USB_BASE+0x344))
-#define UH1_USBINTR (*(volatile unsigned int *)(USB_BASE+0x348))
-#define UH1_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x34c))
-#define UH1_PERIODICLISTBASE (*(volatile unsigned int *)(USB_BASE+0x354))
-#define UH1_ASYNCLISTADDR (*(volatile unsigned int *)(USB_BASE+0x358))
-#define UH1_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x360))
-#define UH1_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x364))
-#define UH1_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x384))
-#define UH1_USBMODE (*(volatile unsigned int *)(USB_BASE+0x3a8))
-
-/* Host 2 */
-#define UH2_ID (*(volatile unsigned int *)(USB_BASE+0x400))
-#define UH2_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x404))
-#define UH2_HWHOST (*(volatile unsigned int *)(USB_BASE+0x408))
-#define UH2_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x410))
-#define UH2_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x414))
-#define UH2_CAPLENGTH (*(volatile unsigned int *)(USB_BASE+0x500))
-#define UH2_HCIVERSION (*(volatile unsigned int *)(USB_BASE+0x502))
-#define UH2_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x504))
-#define UH2_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x508))
-#define UH2_USBCMD (*(volatile unsigned int *)(USB_BASE+0x540))
-#define UH2_USBSTS (*(volatile unsigned int *)(USB_BASE+0x544))
-#define UH2_USBINTR (*(volatile unsigned int *)(USB_BASE+0x548))
-#define UH2_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x54c))
-#define UH2_PERIODICLISTBASE (*(volatile unsigned int *)(USB_BASE+0x554))
-#define UH2_ASYNCLISTADDR (*(volatile unsigned int *)(USB_BASE+0x558))
-#define UH2_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x560))
-#define UH2_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x564))
-#define UH2_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x570))
-#define UH2_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x584))
-#define UH2_USBMODE (*(volatile unsigned int *)(USB_BASE+0x5a8))
-
-/* General */
-#define USB_CTRL (*(volatile unsigned int *)(USB_BASE+0x600))
-#define USB_OTG_MIRROR (*(volatile unsigned int *)(USB_BASE+0x604))
-
-/* Maximum values */
+#ifndef __ARCOTG_UDC_H
+#define __ARCOTG_UDC_H
+
+#include "cpu.h"
+
+#define ETIMEDOUT 1
+
#define USB_MAX_ENDPOINTS 8
#define USB_MAX_PIPES (USB_MAX_ENDPOINTS*2)
#define USB_MAX_CTRL_PAYLOAD 64
+/* USB DR device mode registers (Little Endian) */
+/* Identification registers */
+#define UDC_ID (*(volatile unsigned int *)(USB_BASE+0x000))
+#define UDC_HWGENERAL (*(volatile unsigned int *)(USB_BASE+0x004))
+#define UDC_HWHOST (*(volatile unsigned int *)(USB_BASE+0x008))
+#define UDC_HWTXBUF (*(volatile unsigned int *)(USB_BASE+0x010))
+#define UDC_HWRXBUF (*(volatile unsigned int *)(USB_BASE+0x014))
+
+/* Capability registers */
+#define UDC_CAPLENGTH (*(volatile unsigned char *)(USB_BASE+0x100)) /* Capability Register Length */
+#define UDC_HCIVERSION (*(volatile unsigned short *)(USB_BASE+0x102)) /* Host Controller Interface Version */
+#define UDC_HCSPARAMS (*(volatile unsigned int *)(USB_BASE+0x104)) /* Host Controller Structual Parameters */
+#define UDC_HCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x108)) /* Host Controller Capability Parameters */
+#define UDC_DCIVERSION (*(volatile unsigned short *)(USB_BASE+0x120)) /* Device Controller Interface Version */
+#define UDC_DCCPARAMS (*(volatile unsigned int *)(USB_BASE+0x124)) /* Device Controller Capability Parameters */
+
+/* Operation registers */
+#define UDC_USBCMD (*(volatile unsigned int *)(USB_BASE+0x140)) /* USB Command Register */
+#define UDC_USBSTS (*(volatile unsigned int *)(USB_BASE+0x144)) /* USB Status Register */
+#define UDC_USBINTR (*(volatile unsigned int *)(USB_BASE+0x148)) /* USB Interrupt Enable Register */
+#define UDC_FRINDEX (*(volatile unsigned int *)(USB_BASE+0x14c)) /* Frame Index Register */
+#define UDC_DEVICEADDR (*(volatile unsigned int *)(USB_BASE+0x154)) /* Device Address */
+#define UDC_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158)) /* Endpoint List Address Register */
+#define UDC_BURSTSIZE (*(volatile unsigned int *)(USB_BASE+0x160)) /* Master Interface Data Burst Size Register */
+#define UDC_TXFILLTUNING (*(volatile unsigned int *)(USB_BASE+0x164)) /* Transmit FIFO Tuning Controls Register */
+#define UDC_ULPIVIEW (*(volatile unsigned int *)(USB_BASE+0x170))
+#define UDC_CFGFLAG (*(volatile unsigned int *)(USB_BASE+0x180)) /* Configure Flag Register */
+#define UDC_PORTSC1 (*(volatile unsigned int *)(USB_BASE+0x184)) /* Port 1 Status and Control Register */
+#define UDC_OTGSC (*(volatile unsigned int *)(USB_BASE+0x1a4)) /* On-The-Go Status and Control */
+#define UDC_USBMODE (*(volatile unsigned int *)(USB_BASE+0x1a8)) /* USB Mode Register */
+#define UDC_ENDPTSETUPSTAT (*(volatile unsigned int *)(USB_BASE+0x1ac)) /* Endpoint Setup Status Register */
+#define UDC_ENDPTPRIME (*(volatile unsigned int *)(USB_BASE+0x1b0)) /* Endpoint Initialization Register */
+#define UDC_ENDPTFLUSH (*(volatile unsigned int *)(USB_BASE+0x1b4)) /* Endpoint Flush Register */
+#define UDC_ENDPTSTAT (*(volatile unsigned int *)(USB_BASE+0x1b8)) /* Endpoint Status Register */
+#define UDC_ENDPTCOMPLETE (*(volatile unsigned int *)(USB_BASE+0x1bc)) /* Endpoint Complete Register */
+#define UDC_ENDPTCTRL0 (*(volatile unsigned int *)(USB_BASE+0x1c0)) /* Endpoint 0 Control Register */
+#define UDC_ENDPTCTRL1 (*(volatile unsigned int *)(USB_BASE+0x1c4)) /* Endpoint 1 Control Register */
+#define UDC_ENDPTCTRL2 (*(volatile unsigned int *)(USB_BASE+0x1c8)) /* Endpoint 2 Control Register */
+#define UDC_ENDPTCTRL3 (*(volatile unsigned int *)(USB_BASE+0x1cc)) /* Endpoint 3 Control Register */
+#define UDC_ENDPTCTRL4 (*(volatile unsigned int *)(USB_BASE+0x1d0)) /* Endpoint 4 Control Register */
+#define UDC_ENDPTCTRL5 (*(volatile unsigned int *)(USB_BASE+0x1d4)) /* Endpoint 5 Control Register */
+#define UDC_ENDPTCTRL6 (*(volatile unsigned int *)(USB_BASE+0x1d8)) /* Endpoint 6 Control Register */
+#define UDC_ENDPTCTRL7 (*(volatile unsigned int *)(USB_BASE+0x1dc)) /* Endpoint 7 Control Register */
+#define UDC_ENDPTCTRL(x) (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(x))) /* Endpoint X Control Register */
+
/* ep0 transfer state */
#define WAIT_FOR_SETUP 0
#define DATA_STATE_XMIT 1
@@ -369,4 +312,9 @@
#define USB_CTRL_IOENB (0x00000004)
#define USB_CTRL_ULPI_INT0EN (0x00000001)
-#endif /* __MX31_H */
+/* Externally used functions */
+int dr_controller_setup(void);
+void dr_controller_run(void);
+void dr_controller_stop(void);
+
+#endif /* __ARCOTG_UDC_H */
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index 4e0e6eac2a..d30489526a 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -174,6 +174,9 @@
#define IISFIFO_WR (*(volatile unsigned long*)(0x70002840))
#define IISFIFO_RD (*(volatile unsigned long*)(0x70002880))
+/* The PortalPlayer USB controller uses base address 0xc5000000 */
+#define USB_BASE 0xc5000000
+
#define PROC_SLEEP 0x80000000
#define PROC_WAKE 0x0
diff --git a/firmware/target/arm/usb-pp.c b/firmware/target/arm/usb-pp.c
index 983457b924..042fb5bda5 100644
--- a/firmware/target/arm/usb-pp.c
+++ b/firmware/target/arm/usb-pp.c
@@ -40,7 +40,7 @@
#include "hwcompat.h"
#include "usb-target.h"
-#include "mx31.h"
+#include "arcotg_udc.h"
void usb_init_device(void)
{
@@ -56,30 +56,30 @@ void usb_init_device(void)
DEV_INIT |= INIT_USB;
while ((inl(0x70000028) & 0x80) == 0);
- UOG_PORTSC1 |= PORTSCX_PORT_RESET;
- while ((UOG_PORTSC1 & PORTSCX_PORT_RESET) != 0);
+ UDC_PORTSC1 |= PORTSCX_PORT_RESET;
+ while ((UDC_PORTSC1 & PORTSCX_PORT_RESET) != 0);
- UOG_OTGSC |= 0x5F000000;
- if( (UOG_OTGSC & 0x100) == 0) {
- UOG_USBMODE &=~ USB_MODE_CTRL_MODE_HOST;
- UOG_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
+ UDC_OTGSC |= 0x5F000000;
+ if( (UDC_OTGSC & 0x100) == 0) {
+ UDC_USBMODE &=~ USB_MODE_CTRL_MODE_HOST;
+ UDC_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
outl(inl(0x70000028) | 0x4000, 0x70000028);
outl(inl(0x70000028) | 0x2, 0x70000028);
} else {
- UOG_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
+ UDC_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
outl(inl(0x70000028) &~0x4000, 0x70000028);
outl(inl(0x70000028) | 0x2, 0x70000028);
}
- UOG_USBCMD |= USB_CMD_CTRL_RESET;
- while((UOG_USBCMD & USB_CMD_CTRL_RESET) != 0);
+ UDC_USBCMD |= USB_CMD_CTRL_RESET;
+ while((UDC_USBCMD & USB_CMD_CTRL_RESET) != 0);
- r0 = UOG_PORTSC1;
+ r0 = UDC_PORTSC1;
/* Note from IPL source (referring to next 5 lines of code:
THIS NEEDS TO BE CHANGED ONCE THERE IS KERNEL USB */
- outl(inl(0x70000020) | 0x80000000, 0x70000020);
+ DEV_INIT |= INIT_USB;
DEV_EN |= DEV_USB;
while ((inl(0x70000028) & 0x80) == 0);
outl(inl(0x70000028) | 0x2, 0x70000028);
@@ -120,100 +120,29 @@ void usb_enable(bool on)
}
}
-/*------------------------------------------------------------------
- Internal Hardware related function
- ------------------------------------------------------------------*/
-
-/* @qh_addr is the aligned virt addr of ep QH addr
- * it is used to set endpointlistaddr Reg */
-static int dr_controller_setup(void/* *qh_addr, struct device *dev*/)
-{
- int timeout = 0;
-/* struct arc_usb_config *config;
-
- config = udc_controller->config;
-*/
- /* before here, make sure usb_slave_regs has been initialized */
-/* if (!qh_addr)
- return -EINVAL;
-*/
- /* Stop and reset the usb controller */
- UOG_USBCMD &= ~USB_CMD_RUN_STOP;
-
- UOG_USBCMD |= USB_CMD_CTRL_RESET;
-
- /* Wait for reset to complete */
- timeout = 10000000;
- while ((UOG_USBCMD & USB_CMD_CTRL_RESET) &&
- --timeout) {
- continue;
- }
- if (timeout == 0) {
- //logf("%s: TIMEOUT", __FUNCTION__);
- return 1;
- }
-
- /* Set the controller as device mode and disable setup lockout */
- UOG_USBMODE |= (USB_MODE_CTRL_MODE_DEVICE | USB_MODE_SETUP_LOCK_OFF);
-
- /* Clear the setup status */
- UOG_USBSTS = 0;
-
-/* tmp = virt_to_phys(qh_addr);
- tmp &= USB_EP_LIST_ADDRESS_MASK;
- usb_slave_regs->endpointlistaddr = cpu_to_le32(tmp);
-*/
- UOG_PORTSC1 = (UOG_PORTSC1 & ~PORTSCX_PHY_TYPE_SEL) | PORTSCX_PTS_UTMI;
-
-/* if (config->set_vbus_power)
- config->set_vbus_power(0);
-*/
- return 0;
-}
-
-/* just Enable DR irq reg and Set Dr controller Run */
-static void dr_controller_run(void/*struct arcotg_udc *udc*/)
-{
- /*Enable DR irq reg */
- UOG_USBINTR = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN |
- USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN |
- USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
-
- /* Clear stopped bit */
- /*udc->stopped = 0;*/
-
- /* Set the controller as device mode */
- UOG_USBMODE |= USB_MODE_CTRL_MODE_DEVICE;
-
- /* Set controller to Run */
- UOG_USBCMD |= USB_CMD_RUN_STOP;
-
- return;
-}
-
bool usb_detect(void)
{
static bool prev_usbstatus1 = false;
bool usbstatus1,usbstatus2;
- /* UOG_ID should have the bit format:
+ /* UDC_ID should have the bit format:
[31:24] = 0x0
[23:16] = 0x22 (Revision number)
[15:14] = 0x3 (Reserved)
[13:8] = 0x3a (NID - 1's compliment of ID)
[7:6] = 0x0 (Reserved)
[5:0] = 0x05 (ID) */
- if (UOG_ID != 0x22FA05) {
+ if (UDC_ID != 0x22FA05) {
return false;
}
- usbstatus1 = (UOG_OTGSC & 0x800) ? true : false;
+ usbstatus1 = (UDC_OTGSC & 0x800) ? true : false;
if ((usbstatus1 == true) && (prev_usbstatus1 == false)) {
dr_controller_setup();
dr_controller_run();
}
prev_usbstatus1 = usbstatus1;
- usbstatus2 = (UOG_PORTSC1 & PORTSCX_CURRENT_CONNECT_STATUS) ? true : false;
+ usbstatus2 = (UDC_PORTSC1 & PORTSCX_CURRENT_CONNECT_STATUS) ? true : false;
if (usbstatus1 && usbstatus2) {
return true;