x1000: remove the last vestiges of boot option support

There should be no need for any compatibility hacks since this
value was mostly used internally between the SPL and bootloader.
clk_init() was the only user in the main Rockbox binary which
accessed it, but when loaded by the Rockbox bootloader that code
will not be reached since BOOT_FLAG_CLK_INIT is already set.

Change-Id: Idd68b9834172e652b47432bfb1e00c923ea35407

4 files changed, 28 insertions, 57 deletions

diff --git a/firmware/target/mips/ingenic_x1000/boot-x1000.h b/firmware/target/mips/ingenic_x1000/boot-x1000.h
index fa918a3ead..1b7a0db1e9 100644
--- a/firmware/target/mips/ingenic_x1000/boot-x1000.h
+++ b/firmware/target/mips/ingenic_x1000/boot-x1000.h
@@ -28,16 +28,6 @@
 #include <stddef.h>
 
 enum {
-    BOOT_OPTION_ROCKBOX = 0,
-    BOOT_OPTION_OFW_PLAYER,
-    BOOT_OPTION_OFW_RECOVERY,
-};
-
-enum {
-    /* 3 bits to store the boot option selected by the SPL */
-    BOOT_OPTION_MASK  = 0x7,
-    BOOT_OPTION_SHIFT = 0,
-
     /* Set after running clk_init() and setting up system clocks */
     BOOT_FLAG_CLK_INIT = (1 << 31),
 
@@ -88,18 +78,4 @@ static inline void clr_boot_flag(uint32_t bit)
     cpm_scratch_set(REG_CPM_SCRATCH & ~bit);
 }
 
-static inline void set_boot_option(int opt)
-{
-    uint32_t r = REG_CPM_SCRATCH;
-    r &= ~(BOOT_OPTION_MASK << BOOT_OPTION_SHIFT);
-    r |= (opt & BOOT_OPTION_MASK) << BOOT_OPTION_SHIFT;
-    cpm_scratch_set(r);
-}
-
-static inline int get_boot_option(void)
-{
-    uint32_t r = REG_CPM_SCRATCH;
-    return (r >> BOOT_OPTION_SHIFT) & BOOT_OPTION_MASK;
-}
-
 #endif /* __BOOT_X1000_H__ */
diff --git a/firmware/target/mips/ingenic_x1000/clk-x1000.c b/firmware/target/mips/ingenic_x1000/clk-x1000.c
index 4988e7c3bf..e3b0f792bb 100644
--- a/firmware/target/mips/ingenic_x1000/clk-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/clk-x1000.c
@@ -265,39 +265,36 @@ void clk_init(void)
     jz_writef(CPM_APCR, BS(1), PLLM(42 - 1), PLLN(0), PLLOD(0), ENABLE(1));
     while(jz_readf(CPM_APCR, ON) == 0);
 
-#if (defined(FIIO_M3K) || defined(EROS_QN))
+#if defined(FIIO_M3K) || defined(EROS_QN)
     /* TODO: Allow targets to define their clock frequencies in their config,
      * instead of having this be a random special case. */
-    if(get_boot_option() == BOOT_OPTION_ROCKBOX) {
-        clk_set_ccr_div(CLKDIV_CPU(1) |     /* 1008 MHz */
-                        CLKDIV_L2(2) |      /* 504 MHz */
-                        CLKDIV_AHB0(5) |    /* 201.6 MHz */
-                        CLKDIV_AHB2(5) |    /* 201.6 MHz */
-                        CLKDIV_PCLK(10));   /* 100.8 MHz */
-        clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) |
-                        CLKMUX_CPU(SCLK_A) |
-                        CLKMUX_AHB0(SCLK_A) |
-                        CLKMUX_AHB2(SCLK_A));
-
-        /* DDR to 201.6 MHz */
-        clk_set_ddr(X1000_CLK_SCLK_A, 5);
-
-        /* Disable MPLL */
-        jz_writef(CPM_MPCR, ENABLE(0));
-        while(jz_readf(CPM_MPCR, ON));
-    } else {
-#endif
-        clk_set_ccr_div(CLKDIV_CPU(1) |     /* 1008 MHz */
-                        CLKDIV_L2(2) |      /* 504 MHz */
-                        CLKDIV_AHB0(3) |    /* 200 MHz */
-                        CLKDIV_AHB2(3) |    /* 200 MHz */
-                        CLKDIV_PCLK(6));    /* 100 MHz */
-        clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) |
-                        CLKMUX_CPU(SCLK_A) |
-                        CLKMUX_AHB0(MPLL) |
-                        CLKMUX_AHB2(MPLL));
-#if (defined(FIIO_M3K) || defined(EROS_QN))
-    }
+    clk_set_ccr_div(CLKDIV_CPU(1) |     /* 1008 MHz */
+                    CLKDIV_L2(2) |      /* 504 MHz */
+                    CLKDIV_AHB0(5) |    /* 201.6 MHz */
+                    CLKDIV_AHB2(5) |    /* 201.6 MHz */
+                    CLKDIV_PCLK(10));   /* 100.8 MHz */
+    clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) |
+                    CLKMUX_CPU(SCLK_A) |
+                    CLKMUX_AHB0(SCLK_A) |
+                    CLKMUX_AHB2(SCLK_A));
+
+    /* DDR to 201.6 MHz */
+    clk_set_ddr(X1000_CLK_SCLK_A, 5);
+
+    /* Disable MPLL */
+    jz_writef(CPM_MPCR, ENABLE(0));
+    while(jz_readf(CPM_MPCR, ON));
+#else
+    /* Default configuration matching the Ingenic OF */
+    clk_set_ccr_div(CLKDIV_CPU(1) |     /* 1008 MHz */
+                    CLKDIV_L2(2) |      /* 504 MHz */
+                    CLKDIV_AHB0(3) |    /* 200 MHz */
+                    CLKDIV_AHB2(3) |    /* 200 MHz */
+                    CLKDIV_PCLK(6));    /* 100 MHz */
+    clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) |
+                    CLKMUX_CPU(SCLK_A) |
+                    CLKMUX_AHB0(MPLL) |
+                    CLKMUX_AHB2(MPLL));
 #endif
 
     /* mark that clocks have been initialized */
diff --git a/firmware/target/mips/ingenic_x1000/spl-x1000.c b/firmware/target/mips/ingenic_x1000/spl-x1000.c
index 05196e8270..b9ee6cc1c1 100644
--- a/firmware/target/mips/ingenic_x1000/spl-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/spl-x1000.c
@@ -319,7 +319,6 @@ void spl_main(void)
 
     /* set up boot flags */
     init_boot_flags();
-    set_boot_option(BOOT_OPTION_ROCKBOX);
 
     /* early clock and DRAM init */
     clk_init_early();
diff --git a/firmware/target/mips/ingenic_x1000/system-x1000.c b/firmware/target/mips/ingenic_x1000/system-x1000.c
index d43c8e67e4..7542b97a3d 100644
--- a/firmware/target/mips/ingenic_x1000/system-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/system-x1000.c
@@ -72,7 +72,6 @@ void system_early_init(void)
      * This hack should keep everything working as usual. */
     if(jz_readf(CPM_MPCR, ON) == 0) {
         init_boot_flags();
-        set_boot_option(BOOT_OPTION_ROCKBOX);
         set_boot_flag(BOOT_FLAG_CLK_INIT);
     }
 #endif