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authorCástor Muñoz <cmvidal@gmail.com>2016-07-31 03:00:43 +0200
committerCástor Muñoz <cmvidal@gmail.com>2016-08-02 04:57:49 +0200
commit5e305d35c94199241f71a994cf6a691aec49688c (patch)
tree51b52755a57017b3270720e303193e2daac3d3cf
parent0f89b041c0803e7e1cee2c9bcfc08b209d1c88fd (diff)
downloadrockbox-5e305d3.tar.gz
rockbox-5e305d3.tar.bz2
rockbox-5e305d3.zip
Introduce new USB driver for Synopsys DesignWare USB OTG core.
Based on g#844 and g#949, it is intended as a replacement for the current s3c6400x USB driver. The DesignWare USB OTG core is integrated into many SoC's, however HW core version and capabilities (mainly DMA mode, Tx FIFO mode, FIFO size and number of available IN/OUT endpoins) may differ: CPU targets HW ver DMA NPTX FIFO FIFO sz #IN/OUT -------- ------------- ------ --- --------- ------- ------- as3525v2 sansaclipplus 2.60a Yes Dedicated 0x535 4/4 sansaclipv2 sansaclipzip sansafuzev2 s5l8701 ipodnano2g 2.20a Yes Shared 0x500 4/5 s5l8702 ipod6g 2.60a Yes Dedicated 0x820 7/7 ipodnano3g s5l8720 ipodnano4g ? ? ? ? ? Functionality supported by this driver: - Device mode, compatible with USB 1.1/2.0 hosts. - Shared FIFO (USB_DW_SHARED_FIFO) or dedicated FIFOs. - No DMA (USB_DW_ARCH_SLAVE) or internal DMA mode. - Concurrent transfers: control, bulk (usb_storage, usb_serial) and interrupt (usb_hid). Actually this driver is not used by any CPU, it will be enabled for each individual CPU/target in next patches. Change-Id: I74a1e836d18927a31f6977d71115fb442477dd5f
-rw-r--r--firmware/SOURCES2
-rw-r--r--firmware/export/config.h7
-rw-r--r--firmware/export/usb-designware.h287
-rw-r--r--firmware/target/arm/usb-designware.c1381
-rw-r--r--firmware/usbstack/usb_serial.c11
5 files changed, 1687 insertions, 1 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index db3f09ea8e..9aab3c1115 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -766,6 +766,8 @@ target/arm/usb-drv-arc.c
target/arm/as3525/usb-drv-as3525.c
#elif CONFIG_USBOTG == USBOTG_S3C6400X
target/arm/usb-s3c6400x.c
+#elif CONFIG_USBOTG == USBOTG_DESIGNWARE
+target/arm/usb-designware.c
#elif CONFIG_USBOTG == USBOTG_ISP1583
drivers/isp1583.c
#elif CONFIG_USBOTG == USBOTG_RK27XX
diff --git a/firmware/export/config.h b/firmware/export/config.h
index bdbc1c3f44..b769b63c32 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -363,6 +363,7 @@ Lyre prototype 1 */
#define USBOTG_JZ4740 4740 /* Ingenic Jz4740/Jz4732 */
#define USBOTG_AS3525 3525 /* AMS AS3525 */
#define USBOTG_S3C6400X 6400 /* Samsung S3C6400X, also used in the S5L8701/S5L8702/S5L8720 */
+#define USBOTG_DESIGNWARE 6401 /* Synopsys DesignWare OTG, used in S5L8701/S5L8702/S5L8720/AS3252v2 */
#define USBOTG_RK27XX 2700 /* Rockchip rk27xx */
#define USBOTG_TNETV105 105 /* TI TNETV105 */
@@ -908,6 +909,9 @@ Lyre prototype 1 */
#elif CONFIG_USBOTG == USBOTG_S3C6400X /* FIXME */ && CONFIG_CPU != S5L8701
#define USB_STATUS_BY_EVENT
#define USB_DETECT_BY_REQUEST
+#elif CONFIG_USBOTG == USBOTG_DESIGNWARE /* FIXME */ && CONFIG_CPU != S5L8701
+#define USB_STATUS_BY_EVENT
+#define USB_DETECT_BY_REQUEST
#elif CONFIG_USBOTG == USBOTG_RK27XX
#define USB_STATUS_BY_EVENT
#define USB_DETECT_BY_REQUEST
@@ -1147,6 +1151,7 @@ Lyre prototype 1 */
#elif (CONFIG_USBOTG == USBOTG_ARC) || \
(CONFIG_USBOTG == USBOTG_JZ4740) || \
(CONFIG_USBOTG == USBOTG_M66591) || \
+ (CONFIG_USBOTG == USBOTG_DESIGNWARE) || \
(CONFIG_USBOTG == USBOTG_AS3525)
#define USB_HAS_BULK
#define USB_HAS_INTERRUPT
@@ -1169,7 +1174,7 @@ Lyre prototype 1 */
#if defined(HAVE_BOOTLOADER_USB_MODE) || \
defined(CREATIVE_ZVx) || defined(CPU_TCC77X) || defined(CPU_TCC780X) || \
CONFIG_USBOTG == USBOTG_JZ4740 || CONFIG_USBOTG == USBOTG_AS3525 || \
- CONFIG_USBOTG == USBOTG_S3C6400X
+ CONFIG_USBOTG == USBOTG_S3C6400X || CONFIG_USBOTG == USBOTG_DESIGNWARE
#define USB_ENABLE_STORAGE
#endif
diff --git a/firmware/export/usb-designware.h b/firmware/export/usb-designware.h
new file mode 100644
index 0000000000..428733b4f5
--- /dev/null
+++ b/firmware/export/usb-designware.h
@@ -0,0 +1,287 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2014 Michael Sparmann
+ * Copyright (C) 2014 by Marcin Bukat
+ * Copyright (C) 2016 by Cástor Muñoz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef __USB_DESIGNWARE_H__
+#define __USB_DESIGNWARE_H__
+
+#include <inttypes.h>
+#include "config.h"
+
+#ifndef REG32_PTR_T
+#define REG32_PTR_T volatile uint32_t *
+#endif
+
+/* Global registers */
+#define DWC_GOTGCTL (*((REG32_PTR_T)(OTGBASE + 0x00)))
+#define DWC_GOTGINT (*((REG32_PTR_T)(OTGBASE + 0x04)))
+#define DWC_GAHBCFG (*((REG32_PTR_T)(OTGBASE + 0x08)))
+ #define PTXFELVL (1<<8)
+ #define TXFELVL (1<<7)
+ #define DMAEN (1<<5)
+ #define HBSTLEN(x) ((x)<<1)
+ #define HBSTLEN_SINGLE 0
+ #define HBSTLEN_INCR 1
+ #define HBSTLEN_INCR4 3
+ #define HBSTLEN_INCR8 5
+ #define HBSTLEN_INCR16 7
+ #define GINT (1<<0)
+
+#define DWC_GUSBCFG (*((REG32_PTR_T)(OTGBASE + 0x0c)))
+ #define FDMOD (1<<30)
+ #define TRDT(x) ((x)<<10)
+ #define DDRSEL (1<<7)
+ #define PHSEL (1<<6)
+ #define FSINTF (1<<5)
+ #define ULPI_UTMI_SEL (1<<4)
+ #define PHYIF16 (1<<3)
+
+#define DWC_GRSTCTL (*((REG32_PTR_T)(OTGBASE + 0x10)))
+ #define AHBIDL (1<<31)
+ #define TXFNUM(x) ((x)<<6)
+ #define TXFFLSH (1<<5)
+ #define RXFFLSH (1<<4)
+ #define CSRST (1<<0)
+
+#define DWC_GINTSTS (*((REG32_PTR_T)(OTGBASE + 0x14)))
+ #define WKUINT (1<<31)
+ #define SRQINT (1<<30)
+ #define DISCINT (1<<29)
+ #define CIDSCHG (1<<28)
+ #define PTXFE (1<<26)
+ #define HCINT (1<<25)
+ #define HPRTINT (1<<24)
+ #define FETSUSP (1<<22)
+ #define IPXFR (1<<21)
+ #define IISOIXFR (1<<20)
+ #define OEPINT (1<<19)
+ #define IEPINT (1<<18)
+ #define EPMIS (1<<17)
+ #define EOPF (1<<15)
+ #define ISOODPR (1<<14)
+ #define ENUMDNE (1<<13)
+ #define USBRST (1<<12)
+ #define USBSUSP (1<<11)
+ #define ESUSP (1<<10)
+ #define GOUTNAKEFF (1<<7)
+ #define GINAKEFF (1<<6)
+ #define NPTXFE (1<<5)
+ #define RXFLVL (1<<4)
+ #define SOF (1<<3)
+ #define OTGINT (1<<2)
+ #define MMIS (1<<1)
+ #define CMOD (1<<0)
+
+#define DWC_GINTMSK (*((REG32_PTR_T)(OTGBASE + 0x18)))
+#define DWC_GRXSTSR (*((REG32_PTR_T)(OTGBASE + 0x1c)))
+#define DWC_GRXSTSP (*((REG32_PTR_T)(OTGBASE + 0x20)))
+ #define PKTSTS_GLOBALOUTNAK 1
+ #define PKTSTS_OUTRX 2
+ #define PKTSTS_HCHIN 2
+ #define PKTSTS_OUTDONE 3
+ #define PKTSTS_HCHIN_XFER_COMP 3
+ #define PKTSTS_SETUPDONE 4
+ #define PKTSTS_DATATOGGLEERR 5
+ #define PKTSTS_SETUPRX 6
+ #define PKTSTS_HCHHALTED 7
+
+#define DWC_GRXFSIZ (*((REG32_PTR_T)(OTGBASE + 0x24)))
+#ifdef USB_DW_SHARED_FIFO
+#define DWC_GNPTXFSIZ (*((REG32_PTR_T)(OTGBASE + 0x28)))
+#else
+#define DWC_TX0FSIZ (*((REG32_PTR_T)(OTGBASE + 0x28)))
+#endif
+#define DWC_GNPTXSTS (*((REG32_PTR_T)(OTGBASE + 0x2c)))
+#define DWC_GI2CCTL (*((REG32_PTR_T)(OTGBASE + 0x30)))
+/* reserved */
+#define DWC_GCCFG (*((REG32_PTR_T)(OTGBASE + 0x38)))
+ #define NOVBUSSENS (1<<21)
+ #define SOFOUTEN (1<<20)
+ #define VBUSBSEN (1<<19)
+ #define VBUSASEN (1<<18)
+ #define I2CPADEN (1<<17)
+ #define PWRDWN (1<<16)
+
+#define DWC_CID (*((REG32_PTR_T)(OTGBASE + 0x3c)))
+#define DWC_GSNPSID (*((REG32_PTR_T)(OTGBASE + 0x40)))
+#define DWC_GHWCFG1 (*((REG32_PTR_T)(OTGBASE + 0x44)))
+#define DWC_GHWCFG2 (*((REG32_PTR_T)(OTGBASE + 0x48)))
+#define DWC_GHWCFG3 (*((REG32_PTR_T)(OTGBASE + 0x4c)))
+#define DWC_GHWCFG4 (*((REG32_PTR_T)(OTGBASE + 0x50)))
+#define DWC_GLPMCFG (*((REG32_PTR_T)(OTGBASE + 0x54)))
+#define DWC_HPTXFSIZ (*((REG32_PTR_T)(OTGBASE + 0x100)))
+#define DWC_DIEPTXF(x) (*((REG32_PTR_T)(OTGBASE + 0x104 + 4*(x)))) /*0..15*/
+
+/* Host mode registers */
+#define DWC_HCFG (*((REG32_PTR_T)(OTGBASE + 0x400)))
+#define DWC_HFIR (*((REG32_PTR_T)(OTGBASE + 0x404)))
+#define DWC_HFNUM (*((REG32_PTR_T)(OTGBASE + 0x408)))
+/* reserved */
+#define DWC_HPTXSTS (*((REG32_PTR_T)(OTGBASE + 0x410)))
+#define DWC_HAINT (*((REG32_PTR_T)(OTGBASE + 0x414)))
+#define DWC_HAINTMSK (*((REG32_PTR_T)(OTGBASE + 0x418)))
+#define DWC_HPRT (*((REG32_PTR_T)(OTGBASE + 0x440)))
+#define DWC_HCCHAR(x) (*((REG32_PTR_T)(OTGBASE + 0x500 + 0x20*(x))))
+#define DWC_HCSPLT(x) (*((REG32_PTR_T)(OTGBASE + 0x504 + 0x20*(x))))
+#define DWC_HCINT(x) (*((REG32_PTR_T)(OTGBASE + 0x508 + 0x20*(x))))
+#define DWC_HCINTMSK(x) (*((REG32_PTR_T)(OTGBASE + 0x50c + 0x20*(x))))
+#define DWC_HCTSIZ(x) (*((REG32_PTR_T)(OTGBASE + 0x510 + 0x20*(x))))
+#define DWC_HCDMA(x) (*((REG32_PTR_T)(OTGBASE + 0x514 + 0x20*(x))))
+
+/* Device mode registers */
+#define DWC_DCFG (*((REG32_PTR_T)(OTGBASE + 0x800)))
+ #define EPMISCNT(x) ((x)<<18)
+ #define DAD(x) ((x)<<4)
+ #define NZLSOHSK (1<<2)
+
+#define DWC_DCTL (*((REG32_PTR_T)(OTGBASE + 0x804)))
+ #define POPRGDNE (1<<11)
+ #define CGONAK (1<<10)
+ #define SGONAK (1<<9)
+ #define CGINAK (1<<8)
+ #define SGINAK (1<<7)
+ #define TCTL(x) ((x)<<4)
+ #define GONSTS (1<<3)
+ #define GINSTS (1<<2)
+ #define SDIS (1<<1)
+ #define RWUSIG (1<<0)
+
+#define DWC_DSTS (*((REG32_PTR_T)(OTGBASE + 0x808)))
+/* reserved */
+#define DWC_DIEPMSK (*((REG32_PTR_T)(OTGBASE + 0x810)))
+#define DWC_DOEPMSK (*((REG32_PTR_T)(OTGBASE + 0x814)))
+#define DWC_DAINT (*((REG32_PTR_T)(OTGBASE + 0x818)))
+#define DWC_DAINTMSK (*((REG32_PTR_T)(OTGBASE + 0x81c)))
+/* reserved */
+#define DWC_DVBUSDIS (*((REG32_PTR_T)(OTGBASE + 0x828)))
+#define DWC_DVBUSPULSE (*((REG32_PTR_T)(OTGBASE + 0x82c)))
+
+#ifdef USB_DW_SHARED_FIFO
+#define DWC_DTKNQR1 (*((REG32_PTR_T)(OTGBASE + 0x820)))
+#define DWC_DTKNQR2 (*((REG32_PTR_T)(OTGBASE + 0x824)))
+#define DWC_DTKNQR3 (*((REG32_PTR_T)(OTGBASE + 0x830)))
+#define DWC_DTKNQR4 (*((REG32_PTR_T)(OTGBASE + 0x834)))
+
+#else /* !USB_DW_SHARED_FIFO */
+#define DWC_DTHRCTL (*((REG32_PTR_T)(OTGBASE + 0x830)))
+ #define ARPEN (1<<27)
+ #define RXTHRLEN(x) ((x)<<17)
+ #define RXTHREN (1<<16)
+ #define TXTHRLEN(x) ((x)<<2)
+ #define ISOTHREN (1<<1)
+ #define NONISOTHREN (1<<0)
+
+#define DWC_DIEPEMPMSK (*((REG32_PTR_T)(OTGBASE + 0x834)))
+#define DWC_DEACHINT (*((REG32_PTR_T)(OTGBASE + 0x838)))
+#define DWC_DEACHINTMSK (*((REG32_PTR_T)(OTGBASE + 0x83c)))
+#define DWC_DIEPEACHMSK(x) (*((REG32_PTR_T)(OTGBASE + 0x840 + 4*(x))))
+#define DWC_DOEPEACHMSK(x) (*((REG32_PTR_T)(OTGBASE + 0x880 + 4*(x))))
+#endif
+
+#define DWC_DIEPCTL(x) (*((REG32_PTR_T)(OTGBASE + 0x900 + 0x20*(x))))
+#define DWC_DOEPCTL(x) (*((REG32_PTR_T)(OTGBASE + 0xb00 + 0x20*(x))))
+ #define EPENA (1<<31)
+ #define EPDIS (1<<30)
+ #define SD0PID (1<<28)
+ #define SNAK (1<<27)
+ #define CNAK (1<<26)
+ #define DTXFNUM(x) ((x)<<22)
+ #define STALL (1<<21)
+ #define EPTYP(x) ((x)<<18)
+ #define EPTYP_CONTROL 0
+ #define EPTYP_ISOCHRONOUS 1
+ #define EPTYP_BULK 2
+ #define EPTYP_INTERRUPT 3
+ #define NAKSTS (1<<17)
+ #define USBAEP (1<<15)
+ #define NEXTEP(x) ((x)<<11)
+
+#define DWC_DIEPINT(x) (*((REG32_PTR_T)(OTGBASE + 0x908 + 0x20*(x))))
+#define DWC_DOEPINT(x) (*((REG32_PTR_T)(OTGBASE + 0xb08 + 0x20*(x))))
+ #define TXFE (1<<7) /* IN */
+ #define INEPNE (1<<6) /* IN */
+ #define ITEPMIS (1<<5) /* IN */
+ #define ITTXFE (1<<4) /* IN */
+ #define OTEPDIS (1<<4) /* OUT */
+ #define TOC (1<<3) /* control IN */
+ #define STUP (1<<3) /* control OUT */
+ #define AHBERR (1<<2)
+ #define EPDISD (1<<1)
+ #define XFRC (1<<0)
+
+#define DWC_DIEPTSIZ(x) (*((REG32_PTR_T)(OTGBASE + 0x910 + 0x20*(x))))
+#define DWC_DOEPTSIZ(x) (*((REG32_PTR_T)(OTGBASE + 0xb10 + 0x20*(x))))
+ #define MCCNT(x) ((x)<<29) /* IN */
+ #define STUPCNT(x) ((x)<<29) /* control OUT */
+ #define RXDPID(x) ((x)<<29) /* isochronous OUT */
+ #define PKTCNT(x) ((x)<<19)
+ #define XFERSIZE(x) ((x)<<0)
+
+#define DWC_DIEPDMA(x) (*((REG32_PTR_T)(OTGBASE + 0x914 + 0x20*(x))))
+#define DWC_DOEPDMA(x) (*((REG32_PTR_T)(OTGBASE + 0xb14 + 0x20*(x))))
+
+#define DWC_DTXFSTS(x) (*((REG32_PTR_T)(OTGBASE + 0x918 + 0x20*(x))))
+#define DWC_PCGCCTL (*((REG32_PTR_T)(OTGBASE + 0xe00)))
+#define DWC_DFIFO(x) (*((REG32_PTR_T)(OTGBASE + 0x1000 + 0x1000*(x))))
+
+/* Device mode registers by (epnum,epdir), d==0 -> IN */
+#define DWC_EPCTL(n,d) (*((REG32_PTR_T)(OTGBASE + 0x900 + 0x200*(d) + 0x20*(n))))
+#define DWC_EPINT(n,d) (*((REG32_PTR_T)(OTGBASE + 0x908 + 0x200*(d) + 0x20*(n))))
+#define DWC_EPTSIZ(n,d) (*((REG32_PTR_T)(OTGBASE + 0x910 + 0x200*(d) + 0x20*(n))))
+#define DWC_EPDMA(n,d) (*((REG32_PTR_T)(OTGBASE + 0x914 + 0x200*(d) + 0x20*(n))))
+
+
+/* HS PHY/interface configuration */
+#define DWC_PHYTYPE_UTMI_8 (0)
+#define DWC_PHYTYPE_UTMI_16 (PHYIF16)
+#define DWC_PHYTYPE_ULPI_SDR (ULPI_UTMI_SEL)
+#define DWC_PHYTYPE_ULPI_DDR (ULPI_UTMI_SEL|DDRSEL)
+
+/* configure USB OTG capabilities on SoC */
+struct usb_dw_config
+{
+ uint8_t phytype; /* DWC_PHYTYPE_ */
+
+ uint16_t rx_fifosz;
+ uint16_t nptx_fifosz;
+ uint16_t ptx_fifosz;
+#ifdef USB_DW_SHARED_FIFO
+ bool use_ptxfifo_as_plain_buffer;
+#endif
+#ifdef USB_DW_ARCH_SLAVE
+ bool disable_double_buffering;
+#else
+ uint8_t ahb_burst_len; /* HBSTLEN_ */
+#ifndef USB_DW_SHARED_FIFO
+ uint8_t ahb_threshold;
+#endif
+#endif
+};
+
+extern const struct usb_dw_config usb_dw_config;
+
+extern void usb_dw_target_enable_clocks(void);
+extern void usb_dw_target_disable_clocks(void);
+extern void usb_dw_target_enable_irq(void);
+extern void usb_dw_target_disable_irq(void);
+extern void usb_dw_target_clear_irq(void);
+
+#endif /* __USB_DESIGNWARE_H__ */
diff --git a/firmware/target/arm/usb-designware.c b/firmware/target/arm/usb-designware.c
new file mode 100644
index 0000000000..24c6055434
--- /dev/null
+++ b/firmware/target/arm/usb-designware.c
@@ -0,0 +1,1381 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2009-2014 by Michael Sparmann
+ * Copyright © 2010 Amaury Pouly
+ * Copyright (C) 2014 by Marcin Bukat
+ * Copyright (C) 2016 by Cástor Muñoz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <inttypes.h>
+#include <string.h>
+
+#include "config.h"
+#include "cpu.h"
+#include "system.h"
+#include "kernel.h"
+#include "panic.h"
+#include "power.h"
+#include "usb.h"
+#include "usb_drv.h"
+#include "usb_ch9.h"
+#include "usb_core.h"
+
+#include "usb-designware.h"
+
+/* Define LOGF_ENABLE to enable logf output in this file */
+/*#define LOGF_ENABLE*/
+#include "logf.h"
+
+
+/* The ARM940T uses a subset of the ARMv4 functions, not
+ * supporting clean/invalidate cache entries using MVA.
+ */
+#if CONFIG_CPU == S5L8701
+#define DISCARD_DCACHE_RANGE(b,s) commit_discard_dcache()
+#define COMMIT_DCACHE_RANGE(b,s) commit_dcache()
+#else
+#define DISCARD_DCACHE_RANGE(b,s) discard_dcache_range(b,s)
+#define COMMIT_DCACHE_RANGE(b,s) commit_dcache_range(b,s)
+#endif
+
+#ifndef USB_DW_TOUTCAL
+#define USB_DW_TOUTCAL 0
+#endif
+
+#define GET_DTXFNUM(ep) ((DWC_DIEPCTL(ep)>>22) & 0xf)
+
+#define USB_DW_NUM_DIRS 2
+#define USB_DW_DIR_OFF(dir) (((dir) == USB_DW_EPDIR_IN) ? 0 : 16)
+
+enum usb_dw_epdir
+{
+ USB_DW_EPDIR_IN = 0,
+ USB_DW_EPDIR_OUT = 1,
+};
+
+union usb_ep0_buffer
+{
+ struct usb_ctrlrequest setup;
+ uint8_t raw[64];
+};
+
+static union usb_ep0_buffer ep0_buffer USB_DEVBSS_ATTR;
+
+/* Internal EP state/info */
+struct usb_dw_ep
+{
+ struct semaphore complete;
+ uint32_t* req_addr;
+ uint32_t req_size;
+ uint32_t* addr;
+ uint32_t sizeleft;
+ uint32_t size;
+ int8_t status;
+ uint8_t active;
+ uint8_t busy;
+};
+
+static struct usb_dw_ep usb_dw_ep_list[USB_NUM_ENDPOINTS][USB_DW_NUM_DIRS];
+
+static uint32_t usb_endpoints; /* available EPs mask */
+
+/* For SHARED_FIFO mode this is the number of periodic Tx FIFOs
+ (usually 1), otherwise it is the number of dedicated Tx FIFOs
+ (not counting NPTX FIFO that is always dedicated for IN0). */
+static int n_ptxfifos;
+static uint16_t ptxfifo_usage;
+
+static uint32_t hw_maxbytes;
+static uint32_t hw_maxpackets;
+#ifdef USB_DW_SHARED_FIFO
+static uint8_t hw_nptxqdepth;
+static uint32_t epmis_msk;
+static uint32_t ep_periodic_msk;
+#endif
+
+static const char *dw_dir_str[USB_DW_NUM_DIRS] =
+{
+ [USB_DW_EPDIR_IN] = "IN",
+ [USB_DW_EPDIR_OUT] = "OUT",
+};
+
+
+static struct usb_dw_ep *usb_dw_get_ep(int epnum, enum usb_dw_epdir epdir)
+{
+ return &usb_dw_ep_list[epnum][epdir];
+}
+
+static int usb_dw_maxpktsize(int epnum, enum usb_dw_epdir epdir)
+{
+ return epnum ? DWC_EPCTL(epnum, epdir) & 0x3ff : 64;
+}
+
+static int usb_dw_maxxfersize(int epnum, enum usb_dw_epdir epdir)
+{
+ return epnum ? ALIGN_DOWN_P2(MIN(hw_maxbytes,
+ hw_maxpackets*usb_dw_maxpktsize(epnum, epdir)), CACHEALIGN_BITS) : 64;
+}
+
+/* Calculate number of packets (if size == 0 an empty packet will be sent) */
+static int usb_dw_calc_packets(uint32_t size, uint32_t maxpktsize)
+{
+ int packets = (size + maxpktsize - 1) / maxpktsize;
+ if (!packets) packets = 1;
+ return packets;
+}
+
+static int usb_dw_get_stall(int epnum, enum usb_dw_epdir epdir)
+{
+ return !!(DWC_EPCTL(epnum, epdir) & STALL);
+}
+
+static void usb_dw_set_stall(int epnum, enum usb_dw_epdir epdir, int stall)
+{
+ if (stall)
+ {
+ DWC_EPCTL(epnum, epdir) |= STALL;
+ }
+ else
+ {
+ DWC_EPCTL(epnum, epdir) &= ~STALL;
+ DWC_EPCTL(epnum, epdir) |= SD0PID;
+ }
+}
+
+static void usb_dw_set_address(uint8_t address)
+{
+ DWC_DCFG = (DWC_DCFG & ~(0x7f0)) | DAD(address);
+}
+
+static void usb_dw_wait_for_ahb_idle(void)
+{
+ while (!(DWC_GRSTCTL & AHBIDL));
+}
+
+#ifdef USB_DW_SHARED_FIFO
+static unsigned usb_dw_bytes_in_txfifo(int epnum, uint32_t *sentbytes)
+{
+ uint32_t size = usb_dw_get_ep(epnum, USB_DW_EPDIR_IN)->size;
+ if (sentbytes) *sentbytes = size;
+ uint32_t dieptsiz = DWC_DIEPTSIZ(epnum);
+ uint32_t packetsleft = (dieptsiz >> 19) & 0x3ff;
+ if (!packetsleft) return 0;
+ int maxpktsize = usb_dw_maxpktsize(epnum, USB_DW_EPDIR_IN);
+ int packets = usb_dw_calc_packets(size, maxpktsize);
+ uint32_t bytesleft = dieptsiz & 0x7ffff;
+ uint32_t bytespushed = size - bytesleft;
+ uint32_t bytespulled = (packets - packetsleft) * maxpktsize;
+
+ if (sentbytes) *sentbytes = bytespulled;
+ return bytespushed - bytespulled;
+}
+#endif
+
+#ifdef USB_DW_ARCH_SLAVE
+/* Read one packet/token from Rx FIFO */
+static void usb_dw_handle_rxfifo(void)
+{
+ uint32_t rxsts = DWC_GRXSTSP;
+ int pktsts = (rxsts >> 17) & 0xf;
+
+ switch (pktsts)
+ {
+ case PKTSTS_OUTRX:
+ case PKTSTS_SETUPRX:
+ {
+ int ep = rxsts & 0xf;
+ int words = (((rxsts >> 4) & 0x7ff) + 3) >> 2;
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(ep, USB_DW_EPDIR_OUT);
+ if (dw_ep->busy)
+ {
+ while (words--)
+ *dw_ep->addr++ = DWC_DFIFO(0);
+ }
+ else
+ {
+ /* Discard data */
+ while (words--)
+ (void) DWC_DFIFO(0);
+ }
+ break;
+ }
+ case PKTSTS_OUTDONE:
+ case PKTSTS_SETUPDONE:
+ case PKTSTS_GLOBALOUTNAK:
+ default:
+ break;
+ }
+}
+
+#ifdef USB_DW_SHARED_FIFO
+static void usb_dw_try_push(int epnum)
+{
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, USB_DW_EPDIR_IN);
+
+ if (!dw_ep->busy)
+ return;
+
+ if (epmis_msk & (1 << epnum))
+ return;
+
+ uint32_t wordsleft = ((DWC_DIEPTSIZ(epnum) & 0x7ffff) + 3) >> 2;
+ if (!wordsleft) return;
+
+ /* Get fifo space for NPTXFIFO or PTXFIFO */
+ uint32_t fifospace;
+ int dtxfnum = GET_DTXFNUM(epnum);
+ if (dtxfnum)
+ {
+ uint32_t fifosize = DWC_DIEPTXF(dtxfnum - 1) >> 16;
+ fifospace = fifosize - ((usb_dw_bytes_in_txfifo(epnum, NULL) + 3) >> 2);
+ }
+ else
+ {
+ uint32_t gnptxsts = DWC_GNPTXSTS;
+ fifospace = ((gnptxsts >> 16) & 0xff) ? (gnptxsts & 0xffff) : 0;
+ }
+
+ uint32_t maxpktsize = usb_dw_maxpktsize(epnum, USB_DW_EPDIR_IN);
+ uint32_t words = MIN((maxpktsize + 3) >> 2, wordsleft);
+
+ if (fifospace >= words)
+ {
+ wordsleft -= words;
+ while (words--)
+ DWC_DFIFO(epnum) = *dw_ep->addr++;
+ }
+
+ if (wordsleft)
+ DWC_GINTMSK |= (dtxfnum ? PTXFE : NPTXFE);
+}
+
+#else /* !USB_DW_SHARED_FIFO */
+static void usb_dw_handle_dtxfifo(int epnum)
+{
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, USB_DW_EPDIR_IN);
+
+ if (!dw_ep->busy)
+ return;
+
+ uint32_t wordsleft = ((DWC_DIEPTSIZ(epnum) & 0x7ffff) + 3) >> 2;
+
+ while (wordsleft)
+ {
+ uint32_t words = wordsleft;
+ uint32_t fifospace = DWC_DTXFSTS(epnum) & 0xffff;
+
+ if (fifospace < words)
+ {
+ /* We push whole packets to read consistent info on DIEPTSIZ
+ (i.e. when FIFO size is not maxpktsize multiplo). */
+ int maxpktwords = usb_dw_maxpktsize(epnum, USB_DW_EPDIR_IN) >> 2;
+ words = (fifospace / maxpktwords) * maxpktwords;
+ }
+
+ if (!words)
+ break;
+
+ wordsleft -= words;
+ while (words--)
+ DWC_DFIFO(epnum) = *dw_ep->addr++;
+ }
+
+ if (!wordsleft)
+ DWC_DIEPEMPMSK &= ~(1 << GET_DTXFNUM(epnum));
+}
+#endif /* !USB_DW_SHARED_FIFO */
+#endif /* USB_DW_ARCH_SLAVE */
+
+static void usb_dw_flush_fifo(uint32_t fflsh, int fnum)
+{
+#ifdef USB_DW_ARCH_SLAVE
+ /* Rx queue must be emptied before flushing Rx FIFO */
+ if (fflsh & RXFFLSH)
+ while (DWC_GINTSTS & RXFLVL)
+ usb_dw_handle_rxfifo();
+#else
+ /* Wait for any DMA activity to stop */
+ usb_dw_wait_for_ahb_idle();
+#endif
+ DWC_GRSTCTL = TXFNUM(fnum) | fflsh;
+ while (DWC_GRSTCTL & fflsh);
+ udelay(1); /* Wait 3 PHY cycles */
+}
+
+/* These are the conditions that must be met so that the application can
+ * disable an endpoint avoiding race conditions:
+ *
+ * 1) The endpoint must be enabled when EPDIS is written, otherwise the
+ * core will never raise EPDISD interrupt (thus EPDIS remains enabled).
+ *
+ * 2) - Periodic (SHARED_FIFO) or dedicated (!SHARED_FIFO) IN endpoints:
+ * IN NAK must be effective, to ensure that the core is not going
+ * to disable the EP just before EPDIS is written.
+ * - Non-periodic (SHARED_FIFO) IN endpoints: use usb_dw_nptx_unqueue().
+ * - OUT endpoints: GONAK must be effective, this also ensures that the
+ * core is not going to disable the EP.
+ */
+static void usb_dw_disable_ep(int epnum, enum usb_dw_epdir epdir)
+{
+ if (!epnum && (epdir == USB_DW_EPDIR_OUT))
+ return; /* The application cannot disable OUT0 */
+
+ if (DWC_EPCTL(epnum, epdir) & EPENA)
+ {
+ int tmo = 50;
+ DWC_EPCTL(epnum, epdir) |= EPDIS;
+ while (DWC_EPCTL(epnum, epdir) & EPDIS)
+ {
+ if (!tmo--)
+ panicf("%s: %s%d failed!", __func__, dw_dir_str[epdir], epnum);
+ udelay(1);
+ }
+ }
+}
+
+static void usb_dw_gonak_effective(bool enable)
+{
+ if (enable)
+ {
+ if (!(DWC_DCTL & GONSTS))
+ DWC_DCTL |= SGONAK;
+
+ /* Wait for global IN NAK effective */
+ int tmo = 50;
+ while (~DWC_GINTSTS & GOUTNAKEFF)
+ {
+ if (!tmo--) panicf("%s: failed!", __func__);
+#ifdef USB_DW_ARCH_SLAVE
+ /* Pull Rx queue until GLOBALOUTNAK token is received. */
+ if (DWC_GINTSTS & RXFLVL)
+ usb_dw_handle_rxfifo();
+ else
+#endif
+ udelay(1);
+ }
+ }
+ else
+ {
+ if (DWC_DCTL & GONSTS)
+ DWC_DCTL |= CGONAK;
+ }
+}
+
+static void usb_dw_set_innak_effective(int epnum)
+{
+ if (~DWC_DIEPCTL(epnum) & NAKSTS)
+ {
+ /* Wait for IN NAK effective avoiding race conditions, if the
+ * endpoint is disabled by the core (or it was already disabled)
+ * then INEPNE is never raised.
+ */
+ int tmo = 50;
+ DWC_DIEPCTL(epnum) |= SNAK;
+ while ((DWC_DIEPCTL(epnum) & EPENA) && !(DWC_DIEPINT(epnum) & INEPNE))
+ {
+ if (!tmo--) panicf("%s: IN%d failed!", __func__, epnum);
+ udelay(1);
+ }
+ }
+}
+
+#ifdef USB_DW_SHARED_FIFO
+static void usb_dw_ginak_effective(bool enable)
+{
+ if (enable)
+ {
+ if (!(DWC_DCTL & GINSTS))
+ DWC_DCTL |= SGINAK;
+
+ /* Wait for global IN NAK effective */
+ int tmo = 50;
+ while (~DWC_GINTSTS & GINAKEFF)
+ {
+ if (!tmo--) panicf("%s: failed!", __func__);
+ udelay(1);
+ }
+#ifndef USB_DW_ARCH_SLAVE
+ /* Wait for any DMA activity to stop. */
+ usb_dw_wait_for_ahb_idle();
+#endif
+ }
+ else
+ {
+ if (DWC_DCTL & GINSTS)
+ DWC_DCTL |= CGINAK;
+ }
+}
+
+static void usb_dw_nptx_unqueue(int epnum)
+{
+ uint32_t reenable_msk = 0;
+
+ usb_dw_ginak_effective(true);
+
+ /* Disable EPs */
+ for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
+ {
+ if (usb_endpoints & ~ep_periodic_msk & (1 << ep))
+ {
+ /* Disable */
+ if (~DWC_DIEPCTL(ep) & EPENA)
+ continue;
+ DWC_DIEPCTL(ep) |= EPDIS|SNAK;
+
+ /* Adjust */
+ uint32_t packetsleft = (DWC_DIEPTSIZ(ep) >> 19) & 0x3ff;
+ if (!packetsleft) continue;
+
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(ep, USB_DW_EPDIR_IN);
+ uint32_t sentbytes;
+ uint32_t bytesinfifo = usb_dw_bytes_in_txfifo(ep, &sentbytes);
+
+#ifdef USB_DW_ARCH_SLAVE
+ dw_ep->addr -= (bytesinfifo + 3) >> 2;
+#else
+ (void) bytesinfifo;
+ DWC_DIEPDMA(ep) = (uint32_t)(dw_ep->addr) + sentbytes;
+#endif
+ DWC_DIEPTSIZ(ep) = PKTCNT(packetsleft) | (dw_ep->size - sentbytes);
+
+ /* Do not re-enable the EP we are going to unqueue */
+ if (ep == epnum)
+ continue;
+
+ /* Mark EP to be re-enabled later */
+ reenable_msk |= (1 << ep);
+ }
+ }
+
+ /* Flush NPTXFIFO */
+ usb_dw_flush_fifo(TXFFLSH, 0);
+
+ /* Re-enable EPs */
+ for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
+ if (reenable_msk & (1 << ep))
+ DWC_DIEPCTL(ep) |= EPENA|CNAK;
+
+#ifdef USB_DW_ARCH_SLAVE
+ if (reenable_msk)
+ DWC_GINTMSK |= NPTXFE;
+#endif
+
+ usb_dw_ginak_effective(false);
+}
+#endif /* USB_DW_SHARED_FIFO */
+
+static void usb_dw_flush_endpoint(int epnum, enum usb_dw_epdir epdir)
+{
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
+ dw_ep->busy = false;
+ dw_ep->status = -1;
+ semaphore_release(&dw_ep->complete);
+
+ if (DWC_EPCTL(epnum, epdir) & EPENA)
+ {
+ if (epdir == USB_DW_EPDIR_IN)
+ {
+ /* We are shutting down an endpoint that might still have IN
+ * packets in the FIFO. Disable the endpoint, wait for things
+ * to settle, and flush the relevant FIFO.
+ */
+ int dtxfnum = GET_DTXFNUM(epnum);
+
+#ifdef USB_DW_SHARED_FIFO
+ if (!dtxfnum)
+ {
+ usb_dw_nptx_unqueue(epnum);
+ }
+ else
+#endif
+ {
+ /* Wait for IN NAK effective to avoid race conditions
+ while shutting down the endpoint. */
+ usb_dw_set_innak_effective(epnum);
+
+ /* Disable the EP we are going to flush */
+ usb_dw_disable_ep(epnum, epdir);
+
+ /* Flush it all the way down! */
+ usb_dw_flush_fifo(TXFFLSH, dtxfnum);
+
+#if !defined(USB_DW_SHARED_FIFO) && defined(USB_DW_ARCH_SLAVE)
+ DWC_DIEPEMPMSK &= ~(1 << dtxfnum);
+#endif
+ }
+ }
+ else
+ {
+ /* We are waiting for an OUT packet on this endpoint, which
+ * might arrive any moment. Assert a global output NAK to
+ * avoid race conditions while shutting down the endpoint.
+ * Global output NAK also flushes the Rx FIFO.
+ */
+ usb_dw_gonak_effective(true);
+ usb_dw_disable_ep(epnum, epdir);
+ usb_dw_gonak_effective(false);
+ }
+ }
+
+ /* At this point the endpoint is disabled, SNAK it (in case it is not
+ * already done), it is needed for Tx shared FIFOs (to not to raise
+ * unwanted EPMIS interrupts) and recomended for dedicated FIFOs.
+ */
+ DWC_EPCTL(epnum, epdir) |= SNAK;
+
+#ifdef USB_DW_SHARED_FIFO
+ if (epdir == USB_DW_EPDIR_IN)
+ {
+ epmis_msk &= ~(1 << epnum);
+ if (!epmis_msk)
+ DWC_DIEPMSK &= ~ITTXFE;
+ }
+#endif
+
+ /* Clear all channel interrupts to avoid to process
+ pending tokens for the flushed EP. */
+ DWC_EPINT(epnum, epdir) = DWC_EPINT(epnum, epdir);
+}
+
+static void usb_dw_unconfigure_ep(int epnum, enum usb_dw_epdir epdir)
+{
+ uint32_t epctl = 0;
+
+ if (epdir == USB_DW_EPDIR_IN)
+ {
+#ifdef USB_DW_SHARED_FIFO
+#ifndef USB_DW_ARCH_SLAVE
+ int next;
+ for (next = epnum + 1; next < USB_NUM_ENDPOINTS; next++)
+ if (usb_endpoints & (1 << next))
+ break;
+ epctl = NEXTEP(next % USB_NUM_ENDPOINTS);
+#endif
+ ep_periodic_msk &= ~(1 << epnum);
+#endif
+ ptxfifo_usage &= ~(1 << GET_DTXFNUM(epnum));
+ }
+
+ usb_dw_flush_endpoint(epnum, epdir);
+ DWC_EPCTL(epnum, epdir) = epctl;
+}
+
+static int usb_dw_configure_ep(int epnum,
+ enum usb_dw_epdir epdir, int type, int maxpktsize)
+{
+ uint32_t epctl = SD0PID|EPTYP(type)|USBAEP|maxpktsize;
+
+ if (epdir == USB_DW_EPDIR_IN)
+ {
+ /*
+ * If the hardware has dedicated fifos, we must give each
+ * IN EP a unique tx-fifo even if it is non-periodic.
+ */
+#ifdef USB_DW_SHARED_FIFO
+#ifndef USB_DW_ARCH_SLAVE
+ epctl |= DWC_DIEPCTL(epnum) & NEXTEP(0xf);
+#endif
+ if (type == USB_ENDPOINT_XFER_INT)
+#endif
+ {
+ int fnum;
+ for (fnum = 1; fnum <= n_ptxfifos; fnum++)
+ if (~ptxfifo_usage & (1 << fnum))
+ break;
+ if (fnum > n_ptxfifos)
+ return -1; /* no available fifos */
+ ptxfifo_usage |= (1 << fnum);
+ epctl |= DTXFNUM(fnum);
+#ifdef USB_DW_SHARED_FIFO
+ ep_periodic_msk |= (1 << epnum);
+#endif
+ }
+ }
+
+ DWC_EPCTL(epnum, epdir) = epctl;
+ return 0; /* ok */
+}
+
+static void usb_dw_reset_endpoints(void)
+{
+ /* Initial state for all endpoints, setting OUT EPs as not busy
+ * will discard all pending data (if any) on the flush stage.
+ */
+ for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
+ {
+ for (int dir = 0; dir < USB_DW_NUM_DIRS; dir++)
+ {
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(ep, dir);
+ dw_ep->active = !ep;
+ dw_ep->busy = false;
+ dw_ep->status = -1;
+ semaphore_release(&dw_ep->complete);
+ }
+ }
+
+#if CONFIG_CPU == S5L8701
+ /*
+ * Workaround for spurious -EPROTO when receiving bulk data on Nano2G.
+ *
+ * The Rx FIFO and Rx queue are currupted by the received (corrupted)
+ * data, must be flushed, otherwise the core can not set GONAK effective.
+ */
+ usb_dw_flush_fifo(RXFFLSH, 0);
+#endif
+
+ /* Flush and initialize EPs, includes disabling USBAEP on all EPs
+ * except EP0 (USB HW core keeps EP0 active on all configurations).
+ */
+ for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
+ {
+ if (usb_endpoints & (1 << (ep + 16)))
+ usb_dw_unconfigure_ep(ep, USB_DW_EPDIR_OUT);
+ if (usb_endpoints & (1 << ep))
+ usb_dw_unconfigure_ep(ep, USB_DW_EPDIR_IN);
+ }
+
+ ptxfifo_usage = 0;
+#ifdef USB_DW_SHARED_FIFO
+ ep_periodic_msk = 0;
+#endif
+}
+
+static void usb_dw_start_xfer(int epnum,
+ enum usb_dw_epdir epdir, const void* buf, int size)
+{
+ if ((uint32_t)buf & ((epdir == USB_DW_EPDIR_IN) ? 3 : CACHEALIGN_SIZE-1))
+ logf("%s: %s%d %p unaligned", __func__, dw_dir_str[epdir], epnum, buf);
+
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
+
+ dw_ep->busy = true;
+ dw_ep->status = -1;
+ dw_ep->sizeleft = size;
+ size = MIN(size, usb_dw_maxxfersize(epnum, epdir));
+ dw_ep->size = size;
+
+ int packets = usb_dw_calc_packets(size, usb_dw_maxpktsize(epnum, epdir));
+ uint32_t eptsiz = PKTCNT(packets) | size;
+ uint32_t nak;
+
+ /* Set up data source */
+ dw_ep->addr = (uint32_t*)buf;
+#ifndef USB_DW_ARCH_SLAVE
+ DWC_EPDMA(epnum, epdir) = (uint32_t)buf;
+#endif
+
+ if (epdir == USB_DW_EPDIR_IN)
+ {
+#ifndef USB_DW_ARCH_SLAVE
+ COMMIT_DCACHE_RANGE(buf, size);
+#endif
+#ifdef USB_DW_SHARED_FIFO
+ eptsiz |= MCCNT((ep_periodic_msk >> epnum) & 1);
+#endif
+ nak = CNAK;
+ }
+ else
+ {
+#ifndef USB_DW_ARCH_SLAVE
+ DISCARD_DCACHE_RANGE(buf, size);
+#endif
+ eptsiz |= STUPCNT(!epnum);
+ nak = epnum ? CNAK : SNAK;
+ }
+
+ DWC_EPTSIZ(epnum, epdir) = eptsiz;
+
+ /* Enable the endpoint */
+ DWC_EPCTL(epnum, epdir) |= EPENA | nak;
+
+#ifdef USB_DW_ARCH_SLAVE
+ /* Enable interrupts to start pushing data into the FIFO */
+ if ((epdir == USB_DW_EPDIR_IN) && size)
+#ifdef USB_DW_SHARED_FIFO
+ DWC_GINTMSK |= ((ep_periodic_msk & (1 << epnum)) ? PTXFE : NPTXFE);
+#else
+ DWC_DIEPEMPMSK |= (1 << GET_DTXFNUM(epnum));
+#endif
+#endif
+}
+
+static void usb_dw_ep0_wait_setup(void)
+{
+ usb_dw_start_xfer(0, USB_DW_EPDIR_OUT, ep0_buffer.raw, 64);
+}
+
+static void usb_dw_handle_setup_received(void)
+{
+ static struct usb_ctrlrequest usb_ctrlsetup;
+
+ usb_dw_flush_endpoint(0, USB_DW_EPDIR_IN);
+
+ memcpy(&usb_ctrlsetup, ep0_buffer.raw, sizeof(usb_ctrlsetup));
+
+ if (((usb_ctrlsetup.bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE)
+ && ((usb_ctrlsetup.bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
+ && (usb_ctrlsetup.bRequest == USB_REQ_SET_ADDRESS))
+ usb_dw_set_address(usb_ctrlsetup.wValue);
+
+ usb_core_control_request(&usb_ctrlsetup);
+}
+
+static void usb_dw_abort_endpoint(int epnum, enum usb_dw_epdir epdir)
+{
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
+ if (dw_ep->busy)
+ {
+ usb_dw_flush_endpoint(epnum, epdir);
+ usb_core_transfer_complete(epnum, (epdir == USB_DW_EPDIR_OUT) ?
+ USB_DIR_OUT : USB_DIR_IN, -1, 0);
+ }
+}
+
+static void usb_dw_handle_xfer_complete(int epnum, enum usb_dw_epdir epdir)
+{
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
+
+ if (!dw_ep->busy)
+ return;
+
+ uint32_t bytesleft = DWC_EPTSIZ(epnum, epdir) & 0x7ffff;
+
+ if (!epnum && (epdir == USB_DW_EPDIR_OUT)) /* OUT0 */
+ {
+ int recvbytes = 64 - bytesleft;
+ dw_ep->sizeleft = dw_ep->req_size - recvbytes;
+ if (dw_ep->req_addr)
+ memcpy(dw_ep->req_addr, ep0_buffer.raw, dw_ep->req_size);
+ }
+ else
+ {
+ dw_ep->sizeleft -= (dw_ep->size - bytesleft);
+ if (!bytesleft && dw_ep->sizeleft)
+ {
+#ifndef USB_DW_ARCH_SLAVE
+ dw_ep->addr += (dw_ep->size >> 2); /* words */
+#endif
+ usb_dw_start_xfer(epnum, epdir, dw_ep->addr, dw_ep->sizeleft);
+ return;
+ }
+
+ if (epdir == USB_DW_EPDIR_IN)
+ {
+ /* SNAK the disabled EP, otherwise IN tokens for this
+ EP could raise unwanted EPMIS interrupts. Useful for
+ usbserial when there is no data to send. */
+ DWC_DIEPCTL(epnum) |= SNAK;
+
+#ifdef USB_DW_SHARED_FIFO
+ /* See usb-s5l8701.c */
+ if (usb_dw_config.use_ptxfifo_as_plain_buffer)
+ {
+ int dtxfnum = GET_DTXFNUM(epnum);
+ if (dtxfnum)
+ usb_dw_flush_fifo(TXFFLSH, dtxfnum);
+ }
+#endif
+ }
+ }
+
+ dw_ep->busy = false;
+ dw_ep->status = 0;
+ semaphore_release(&dw_ep->complete);
+
+ int transfered = dw_ep->req_size - dw_ep->sizeleft;
+ usb_core_transfer_complete(epnum, (epdir == USB_DW_EPDIR_OUT) ?
+ USB_DIR_OUT : USB_DIR_IN, dw_ep->status, transfered);
+}
+
+#ifdef USB_DW_SHARED_FIFO
+static int usb_dw_get_epmis(void)
+{
+ unsigned epmis;
+ uint32_t gnptxsts = DWC_GNPTXSTS;
+
+ if (((gnptxsts >> 16) & 0xff) >= hw_nptxqdepth)
+ return -1; /* empty queue */
+
+ /* Get the EP on the top of the queue, 0 < idx < number of available
+ IN endpoints */
+ int idx = (gnptxsts >> 27) & 0xf;
+ for (epmis = 0; epmis < USB_NUM_ENDPOINTS; epmis++)
+ if ((usb_endpoints & (1 << epmis)) && !idx--)
+ break;
+
+ /* The maximum EP mismatch counter is configured, so we verify all NPTX
+ queue entries, 4 bits per entry, first entry at DTKQNR1[11:8] */
+ uint32_t volatile *dtknqr = &DWC_DTKNQR1;
+ for (int i = 2; i < hw_nptxqdepth + 2; i++)
+ if (((*(dtknqr+(i>>3)) >> ((i & 0x7)*4)) & 0xf) == epmis)
+ return -1;
+
+ return epmis;
+}
+
+static void usb_dw_handle_token_mismatch(void)
+{
+ usb_dw_ginak_effective(true);
+ int epmis = usb_dw_get_epmis();
+ if (epmis >= 0)
+ {
+ /* The EP is disabled, unqueued, and reconfigured to re-reenable it
+ later when a token is received, (or it will be cancelled by
+ timeout if it was a blocking request). */
+ usb_dw_nptx_unqueue(epmis);
+
+ epmis_msk |= (1 << epmis);
+ if (epmis_msk)
+ DWC_DIEPMSK |= ITTXFE;
+
+ /* Be sure the status is clear */
+ DWC_DIEPINT(epmis) = ITTXFE;
+
+ /* Must disable NAK to allow to get ITTXFE interrupts for this EP */
+ DWC_DIEPCTL(epmis) |= CNAK;
+ }
+ usb_dw_ginak_effective(false);
+}
+#endif /* USB_DW_SHARED_FIFO */
+
+static void usb_dw_irq(void)
+{
+ int ep;
+ uint32_t daint;
+
+#ifdef USB_DW_ARCH_SLAVE
+ /* Handle one packet at a time, the IRQ will re-trigger if there's
+ something left. */
+ if (DWC_GINTSTS & RXFLVL)
+ {
+ usb_dw_handle_rxfifo();
+ }
+#endif
+
+#ifdef USB_DW_SHARED_FIFO
+ if (DWC_GINTSTS & EPMIS)
+ {
+ usb_dw_handle_token_mismatch();
+ DWC_GINTSTS = EPMIS;
+ }
+
+#ifdef USB_DW_ARCH_SLAVE
+ uint32_t gintsts = DWC_GINTSTS & DWC_GINTMSK;
+ if (gintsts & PTXFE)
+ {
+ /* First disable the IRQ, it will be re-enabled later if there
+ is anything left to be done. */
+ DWC_GINTMSK &= ~PTXFE;
+ /* Check all periodic endpoints for anything to be transmitted */
+ for (ep = 1; ep < USB_NUM_ENDPOINTS; ep++)
+ if (usb_endpoints & ep_periodic_msk & (1 << ep))
+ usb_dw_try_push(ep);
+ }
+
+ if (gintsts & NPTXFE)
+ {
+ /* First disable the IRQ, it will be re-enabled later if there
+ is anything left to be done. */
+ DWC_GINTMSK &= ~NPTXFE;
+ /* Check all non-periodic endpoints for anything to be transmitted */
+ for (ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
+ if (usb_endpoints & ~ep_periodic_msk & (1 << ep))
+ usb_dw_try_push(ep);
+ }
+#endif /* USB_DW_ARCH_SLAVE */
+#endif /* USB_DW_SHARED_FIFO */
+
+ daint = DWC_DAINT;
+
+ /* IN */
+ for (ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
+ {
+ if (daint & (1 << ep))
+ {
+ uint32_t epints = DWC_DIEPINT(ep);
+
+ if (epints & TOC)
+ {
+ usb_dw_abort_endpoint(ep, USB_DW_EPDIR_IN);
+ }
+
+#ifdef USB_DW_SHARED_FIFO
+ if (epints & ITTXFE)
+ {
+ if (epmis_msk & (1 << ep))
+ {
+ DWC_DIEPCTL(ep) |= EPENA;
+ epmis_msk &= ~(1 << ep);
+ if (!epmis_msk)
+ DWC_DIEPMSK &= ~ITTXFE;
+ }
+ }
+
+#elif defined(USB_DW_ARCH_SLAVE)
+ if (epints & TXFE)
+ {
+ usb_dw_handle_dtxfifo(ep);
+ }
+#endif
+
+ /* Clear XFRC here, if this is a 'multi-transfer' request then
+ a new transfer is going to be launched, this ensures it will
+ not miss a single interrupt. */
+ DWC_DIEPINT(ep) = epints;
+
+ if (epints & XFRC)
+ {
+ usb_dw_handle_xfer_complete(ep, USB_DW_EPDIR_IN);
+ }
+ }
+ }
+
+ /* OUT */
+ for (ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
+ {
+ if (daint & (1 << (ep + 16)))
+ {
+ uint32_t epints = DWC_DOEPINT(ep);
+
+ if (!ep)
+ {
+ if (epints & STUP)
+ {
+ usb_dw_handle_setup_received();
+ }
+ else if (epints & XFRC)
+ {
+ usb_dw_handle_xfer_complete(0, USB_DW_EPDIR_OUT);
+ }
+ usb_dw_ep0_wait_setup();
+ /* Clear interrupt after the current EP0 packet is handled */
+ DWC_DOEPINT(0) = epints;
+ }
+ else
+ {
+ DWC_DOEPINT(ep) = epints;
+ if (epints & XFRC)
+ {
+ usb_dw_handle_xfer_complete(ep, USB_DW_EPDIR_OUT);
+ }
+ }
+ }
+ }
+
+ if (DWC_GINTSTS & USBRST)
+ {
+ DWC_GINTSTS = USBRST;
+ usb_dw_set_address(0);
+ usb_dw_reset_endpoints();
+ usb_dw_ep0_wait_setup();
+ usb_core_bus_reset();
+ }
+
+ if (DWC_GINTSTS & ENUMDNE)
+ {
+ DWC_GINTSTS = ENUMDNE;
+ /* Nothing to do? */
+ }
+}
+
+static void usb_dw_check_hw(void)
+{
+ uint32_t ghwcfg2 = DWC_GHWCFG2;
+ uint32_t ghwcfg3 = DWC_GHWCFG3;
+ uint32_t ghwcfg4 = DWC_GHWCFG4;
+ const struct usb_dw_config *c = &usb_dw_config;
+ int hw_numeps;
+ int hw_maxtxfifos; /* periodic or dedicated */
+ char *err;
+
+ hw_numeps = ((ghwcfg2 >> 10) & 0xf) + 1;
+
+ if (hw_numeps < USB_NUM_ENDPOINTS)
+ {
+ err = "USB_NUM_ENDPOINTS too big";
+ goto panic;
+ }
+ /* HWCFG registers are not checked to detect the PHY, if an option
+ is not supported then the related bits should be Read-Only. */
+ DWC_GUSBCFG = c->phytype;
+ if (DWC_GUSBCFG != c->phytype)
+ {
+ err = "PHY type not supported";
+ goto panic;
+ }
+#ifndef USB_DW_ARCH_SLAVE
+ if (((ghwcfg2 >> 3) & 3) != 2)
+ {
+ err = "internal DMA not supported";
+ goto panic;
+ }
+#endif
+#ifdef USB_DW_SHARED_FIFO
+ if ((ghwcfg4 >> 25) & 1)
+ {
+ err = "shared TxFIFO not supported";
+ goto panic;
+ }
+ hw_maxtxfifos = ghwcfg4 & 0xf;
+ hw_nptxqdepth = (1 << (((ghwcfg2 >> 22) & 3) + 1));
+#else
+ if (!((ghwcfg4 >> 25) & 1))
+ {
+ err = "dedicated TxFIFO not supported";
+ goto panic;
+ }
+ hw_maxtxfifos = (ghwcfg4 >> 26) & 0xf;
+#endif
+ hw_maxbytes = (1 << (((ghwcfg3 >> 0) & 0xf) + 11)) - 1;
+ hw_maxpackets = (1 << (((ghwcfg3 >> 4) & 0x7) + 4)) - 1;
+ uint16_t hw_fifomem = ghwcfg3 >> 16;
+
+ /* Configure FIFOs, sizes are 32-bit words, we will need at least
+ one periodic or dedicated Tx FIFO (really the periodic Tx FIFO
+ is not needed if !USB_ENABLE_HID). */
+ if (c->rx_fifosz + c->nptx_fifosz + c->ptx_fifosz > hw_fifomem)
+ {
+ err = "insufficient FIFO memory";
+ goto panic;
+ }
+ n_ptxfifos = (hw_fifomem - c->rx_fifosz - c->nptx_fifosz) / c->ptx_fifosz;
+ if (n_ptxfifos > hw_maxtxfifos) n_ptxfifos = hw_maxtxfifos;
+
+ logf("%s():", __func__);
+ logf(" HW version: %4lx, num EPs: %d", DWC_GSNPSID & 0xffff, hw_numeps);
+ logf(" FIFO mem=%d rx=%d nptx=%d ptx=%dx%d", hw_fifomem,
+ c->rx_fifosz, c->nptx_fifosz, n_ptxfifos, c->ptx_fifosz);
+
+ return;
+
+panic:
+ panicf("%s: %s", __func__, err);
+}
+
+static void usb_dw_init(void)
+{
+ static bool initialized = false;
+ const struct usb_dw_config *c = &usb_dw_config;
+
+ if (!initialized)
+ {
+ for (int ep = 0; ep < USB_NUM_ENDPOINTS; ep++)
+ for (int dir = 0; dir < USB_DW_NUM_DIRS; dir++)
+ semaphore_init(&usb_dw_get_ep(ep, dir)->complete, 1, 0);
+ initialized = true;
+ }
+
+ /* Disable IRQ during setup */
+ usb_dw_target_disable_irq();
+
+ /* Enable OTG clocks */
+ usb_dw_target_enable_clocks();
+
+ /* Enable PHY clocks */
+ DWC_PCGCCTL = 0;
+
+ usb_dw_check_hw();
+
+ /* Configure PHY type (must be done before reset) */
+#ifndef USB_DW_TURNAROUND
+ /*
+ * Turnaround time (in PHY clocks) = 4*AHB clocks + 1*PHY clock,
+ * worst cases are:
+ * 16-bit UTMI+: PHY=30MHz, AHB=30Mhz -> 5
+ * 8-bit UTMI+: PHY=60MHz, AHB=30MHz -> 9
+ */
+ int USB_DW_TURNAROUND = (c->phytype == DWC_PHYTYPE_UTMI_16) ? 5 : 9;
+#endif
+ uint32_t gusbcfg = c->phytype|TRDT(USB_DW_TURNAROUND)|USB_DW_TOUTCAL;
+ DWC_GUSBCFG = gusbcfg;
+
+ /* Reset the whole USB core */
+ udelay(100);
+ usb_dw_wait_for_ahb_idle();
+ DWC_GRSTCTL = CSRST;
+ while (DWC_GRSTCTL & CSRST);
+ usb_dw_wait_for_ahb_idle();
+
+ /* Configure FIFOs */
+ DWC_GRXFSIZ = c->rx_fifosz;
+#ifdef USB_DW_SHARED_FIFO
+ DWC_GNPTXFSIZ = (c->nptx_fifosz << 16) | c->rx_fifosz;
+#else
+ DWC_TX0FSIZ = (c->nptx_fifosz << 16) | c->rx_fifosz;
+#endif
+ for (int i = 0; i < n_ptxfifos; i++)
+ DWC_DIEPTXF(i) = (c->ptx_fifosz << 16) |
+ (c->nptx_fifosz + c->rx_fifosz + c->ptx_fifosz*i);
+ /*
+ * According to p428 of the design guide, we need to ensure that
+ * fifos are flushed before continuing.
+ */
+ usb_dw_flush_fifo(TXFFLSH|RXFFLSH, 0x10);
+
+ /* Configure the core */
+ DWC_GUSBCFG = gusbcfg;
+
+ uint32_t gahbcfg = GINT;
+#ifdef USB_DW_ARCH_SLAVE
+#ifdef USB_DW_SHARED_FIFO
+ if (c->use_ptxfifo_as_plain_buffer)
+ gahbcfg |= PTXFELVL;
+#endif
+ if (c->disable_double_buffering)
+ gahbcfg |= TXFELVL;
+#else
+ gahbcfg |= HBSTLEN(c->ahb_burst_len)|DMAEN;
+#endif
+ DWC_GAHBCFG = gahbcfg;
+
+ DWC_DCFG = NZLSOHSK;
+#ifdef USB_DW_SHARED_FIFO
+ /* Set EP mismatch counter to the maximum */
+ DWC_DCFG |= EPMISCNT(0x1f);
+#endif
+
+#if !defined(USB_DW_ARCH_SLAVE) && !defined(USB_DW_SHARED_FIFO)
+ if (c->ahb_threshold)
+ DWC_DTHRCTL = ARPEN|RXTHRLEN(c->ahb_threshold)|RXTHREN;
+#endif
+
+ /* Set up interrupts */
+ DWC_DOEPMSK = STUP|XFRC;
+ DWC_DIEPMSK = TOC|XFRC;
+
+ /* Unmask all available endpoints */
+ DWC_DAINTMSK = 0xffffffff;
+ usb_endpoints = DWC_DAINTMSK;
+
+ uint32_t gintmsk = USBRST|ENUMDNE|IEPINT|OEPINT;
+#ifdef USB_DW_ARCH_SLAVE
+ gintmsk |= RXFLVL;
+#endif
+#ifdef USB_DW_SHARED_FIFO
+ gintmsk |= EPMIS;
+#endif
+ DWC_GINTMSK = gintmsk;
+
+ usb_dw_reset_endpoints();
+
+ /* Soft disconnect */
+ DWC_DCTL = SDIS;
+
+ usb_dw_target_clear_irq();
+ usb_dw_target_enable_irq();
+
+ /* Soft reconnect */
+ udelay(3000);
+ DWC_DCTL &= ~SDIS;
+}
+
+static void usb_dw_exit(void)
+{
+ /* Soft disconnect */
+ DWC_DCTL = SDIS;
+ udelay(10);
+
+ DWC_PCGCCTL = 1; /* Stop Phy clock */
+
+ /* Disable IRQs */
+ usb_dw_target_disable_irq();
+
+ /* Disable clocks */
+ usb_dw_target_disable_clocks();
+}
+
+
+/*
+ * API functions
+ */
+
+/* Cancel transfers on configured EPs */
+void usb_drv_cancel_all_transfers()
+{
+ usb_dw_target_disable_irq();
+ for (int ep = 1; ep < USB_NUM_ENDPOINTS; ep++)
+ for (int dir = 0; dir < USB_DW_NUM_DIRS; dir++)
+ if (usb_endpoints & (1 << (ep + USB_DW_DIR_OFF(dir))))
+ if (usb_dw_get_ep(ep, dir)->active)
+ {
+ //usb_dw_flush_endpoint(ep, dir);
+ usb_dw_abort_endpoint(ep, dir);
+ DWC_EPCTL(ep, dir) |= SD0PID;
+ }
+ usb_dw_target_enable_irq();
+}
+
+bool usb_drv_stalled(int endpoint, bool in)
+{
+ return usb_dw_get_stall(EP_NUM(endpoint),
+ in ? USB_DW_EPDIR_IN : USB_DW_EPDIR_OUT);
+}
+
+void usb_drv_stall(int endpoint, bool stall, bool in)
+{
+ usb_dw_target_disable_irq();
+ usb_dw_set_stall(EP_NUM(endpoint),
+ in ? USB_DW_EPDIR_IN : USB_DW_EPDIR_OUT, stall);
+ usb_dw_target_enable_irq();
+}
+
+void usb_drv_set_address(int address)
+{
+#if 1
+ /* Ignored intentionally, because the controller requires us to set the
+ new address before sending the response for some reason. So we'll
+ already set it when the control request arrives, before passing that
+ into the USB core, which will then call this dummy function. */
+ (void)address;
+#else
+ usb_dw_target_disable_irq();
+ usb_dw_set_address(address);
+ usb_dw_target_enable_irq();
+#endif
+}
+
+int usb_drv_port_speed(void)
+{
+ return ((DWC_DSTS & 0x6) == 0);
+}
+
+void usb_drv_set_test_mode(int mode)
+{
+ (void)mode;
+ /* Ignore this for now */
+}
+
+void usb_attach(void)
+{
+}
+
+void usb_drv_init(void)
+{
+ usb_dw_init();
+}
+
+void usb_drv_exit(void)
+{
+ usb_dw_exit();
+}
+
+void INT_USB_FUNC(void)
+{
+ usb_dw_irq();
+}
+
+int usb_drv_request_endpoint(int type, int dir)
+{
+ int request_ep = -1;
+ enum usb_dw_epdir epdir = (EP_DIR(dir) == DIR_IN) ?
+ USB_DW_EPDIR_IN : USB_DW_EPDIR_OUT;
+
+ usb_dw_target_disable_irq();
+ for (int ep = 1; ep < USB_NUM_ENDPOINTS; ep++)
+ {
+ if (usb_endpoints & (1 << (ep + USB_DW_DIR_OFF(epdir))))
+ {
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(ep, epdir);
+ if (!dw_ep->active)
+ {
+ if (usb_dw_configure_ep(ep, epdir, type,
+ usb_drv_port_speed() ? 512 : 64) >= 0)
+ {
+ dw_ep->active = true;
+ request_ep = ep | dir;
+ }
+ break;
+ }
+ }
+ }
+ usb_dw_target_enable_irq();
+ return request_ep;
+}
+
+void usb_drv_release_endpoint(int endpoint)
+{
+ int epnum = EP_NUM(endpoint);
+ if (!epnum) return;
+ enum usb_dw_epdir epdir = (EP_DIR(endpoint) == DIR_IN) ?
+ USB_DW_EPDIR_IN : USB_DW_EPDIR_OUT;
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, epdir);
+
+ usb_dw_target_disable_irq();
+ if (dw_ep->active)
+ {
+ usb_dw_unconfigure_ep(epnum, epdir);
+ dw_ep->active = false;
+ }
+ usb_dw_target_enable_irq();
+}
+
+int usb_drv_recv(int endpoint, void* ptr, int length)
+{
+ int epnum = EP_NUM(endpoint);
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, USB_DW_EPDIR_OUT);
+
+ usb_dw_target_disable_irq();
+ if (dw_ep->active)
+ {
+ dw_ep->req_addr = ptr;
+ dw_ep->req_size = length;
+ /* OUT0 is always launched waiting for SETUP packet,
+ it is CNAKed to receive app data */
+ if (epnum == 0)
+ DWC_DOEPCTL(0) |= CNAK;
+ else
+ usb_dw_start_xfer(epnum, USB_DW_EPDIR_OUT, ptr, length);
+ }
+ usb_dw_target_enable_irq();
+ return 0;
+}
+
+int usb_drv_send_nonblocking(int endpoint, void *ptr, int length)
+{
+ int epnum = EP_NUM(endpoint);
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, USB_DW_EPDIR_IN);
+
+ usb_dw_target_disable_irq();
+ if (dw_ep->active)
+ {
+ dw_ep->req_addr = ptr;
+ dw_ep->req_size = length;
+ usb_dw_start_xfer(epnum, USB_DW_EPDIR_IN, ptr, length);
+ }
+ usb_dw_target_enable_irq();
+ return 0;
+}
+
+int usb_drv_send(int endpoint, void *ptr, int length)
+{
+ int epnum = EP_NUM(endpoint);
+ struct usb_dw_ep* dw_ep = usb_dw_get_ep(epnum, USB_DW_EPDIR_IN);
+
+ semaphore_wait(&dw_ep->complete, 0);
+
+ usb_drv_send_nonblocking(endpoint, ptr, length);
+
+ if (semaphore_wait(&dw_ep->complete, HZ) == OBJ_WAIT_TIMEDOUT)
+ {
+ usb_dw_target_disable_irq();
+ usb_dw_abort_endpoint(epnum, USB_DW_EPDIR_IN);
+ usb_dw_target_enable_irq();
+ }
+
+ return dw_ep->status;
+}
diff --git a/firmware/usbstack/usb_serial.c b/firmware/usbstack/usb_serial.c
index 4a80433435..e3ef4f5814 100644
--- a/firmware/usbstack/usb_serial.c
+++ b/firmware/usbstack/usb_serial.c
@@ -19,6 +19,7 @@
*
****************************************************************************/
#include "string.h"
+#include "config.h"
#include "system.h"
#include "usb_core.h"
#include "usb_drv.h"
@@ -60,6 +61,11 @@ static unsigned char send_buffer[BUFFER_SIZE]
USB_DEVBSS_ATTR __attribute__((aligned(32)));
static unsigned char receive_buffer[32]
USB_DEVBSS_ATTR __attribute__((aligned(32)));
+#if CONFIG_USBOTG == USBOTG_DESIGNWARE
+/* Aligned transit buffer */
+static unsigned char transit_buffer[32]
+ USB_DEVBSS_ATTR __attribute__((aligned(4)));
+#endif
static void sendout(void);
@@ -163,8 +169,13 @@ static void sendout(void)
if(buffer_transitlength > 0)
{
buffer_length -= buffer_transitlength;
+#if CONFIG_USBOTG == USBOTG_DESIGNWARE
+ memcpy(transit_buffer,&send_buffer[buffer_start],buffer_transitlength);
+ usb_drv_send_nonblocking(ep_in,transit_buffer,buffer_transitlength);
+#else
usb_drv_send_nonblocking(ep_in, &send_buffer[buffer_start],
buffer_transitlength);
+#endif
}
}