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authorJens Arnold <amiconn@rockbox.org>2006-05-07 20:20:27 +0000
committerJens Arnold <amiconn@rockbox.org>2006-05-07 20:20:27 +0000
commit61b8604a9cd46af54282731b2833f7f22d8a7e18 (patch)
tree9d3eaafc0995ccd718d3dbe1b4a82bf672c9b608
parent595a2040204a5f2de2ca3249e215de25983d6711 (diff)
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Ondio: (Hopefully) fix the occasional freezes during playback: Use DMA channel 0 for MMC transfer. As it has higher priority than channel 3 (used for playback), the risk of serial receive overruns is minimised.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9885 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/drivers/ata_mmc.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/firmware/drivers/ata_mmc.c b/firmware/drivers/ata_mmc.c
index f398846387..b2e79c419a 100644
--- a/firmware/drivers/ata_mmc.c
+++ b/firmware/drivers/ata_mmc.c
@@ -583,12 +583,12 @@ static int receive_block(unsigned char *inbuf, int size, long timeout)
SCR1 = 0; /* disable serial */
SSR1 = 0; /* clear all flags */
- /* setup DMA channel 2 */
- CHCR2 = 0; /* disable */
- SAR2 = RDR1_ADDR;
- DAR2 = (unsigned long) inbuf;
- DTCR2 = size;
- CHCR2 = 0x4601; /* fixed source address, RXI1, enable */
+ /* setup DMA channel 0 */
+ CHCR0 = 0; /* disable */
+ SAR0 = RDR1_ADDR;
+ DAR0 = (unsigned long) inbuf;
+ DTCR0 = size;
+ CHCR0 = 0x4601; /* fixed source address, RXI1, enable */
DMAOR = 0x0001;
SCR1 = (SCI_RE|SCI_RIE); /* kick off DMA */
@@ -600,7 +600,7 @@ static int receive_block(unsigned char *inbuf, int size, long timeout)
bg_copy_swap();
yield(); /* be nice */
- while (!(CHCR2 & 0x0002)); /* wait for end of DMA */
+ while (!(CHCR0 & 0x0002)); /* wait for end of DMA */
while (!(SSR1 & SCI_ORER)); /* wait for the trailing bytes */
SCR1 = 0;
serial_mode = SER_DISABLED;
@@ -625,19 +625,19 @@ static int send_block(int size, unsigned char start_token, long timeout)
SCR1 = 0; /* disable serial */
SSR1 = 0; /* clear all flags */
- /* setup DMA channel 2 */
- CHCR2 = 0; /* disable */
- SAR2 = (unsigned long)(curbuf + 1);
- DAR2 = TDR1_ADDR;
- DTCR2 = size + 3; /* start token + block + dummy crc */
- CHCR2 = 0x1701; /* fixed dest. address, TXI1, enable */
+ /* setup DMA channel 0 */
+ CHCR0 = 0; /* disable */
+ SAR0 = (unsigned long)(curbuf + 1);
+ DAR0 = TDR1_ADDR;
+ DTCR0 = size + 3; /* start token + block + dummy crc */
+ CHCR0 = 0x1701; /* fixed dest. address, TXI1, enable */
DMAOR = 0x0001;
SCR1 = (SCI_TE|SCI_TIE); /* kick off DMA */
bg_copy_swap();
yield(); /* be nice */
- while (!(CHCR2 & 0x0002)); /* wait for end of DMA */
+ while (!(CHCR0 & 0x0002)); /* wait for end of DMA */
while (!(SSR1 & SCI_TEND)); /* wait for end of transfer */
SCR1 = 0;
serial_mode = SER_DISABLED;