diff options
| author | Karl Kurbjun <kkurbjun@gmail.com> | 2007-09-20 04:46:41 +0000 |
|---|---|---|
| committer | Karl Kurbjun <kkurbjun@gmail.com> | 2007-09-20 04:46:41 +0000 |
| commit | 7b97fe21c0f2c9b6742ad50439020023f385fe6c (patch) | |
| tree | 2c1a7312c3373b32e7dbc8a03d76c83dc9c12ce0 | |
| parent | a80c0e8b83eb52a322c2b33e49875159c6d6a12a (diff) | |
| download | rockbox-7b97fe21c0f2c9b6742ad50439020023f385fe6c.tar.gz rockbox-7b97fe21c0f2c9b6742ad50439020023f385fe6c.zip | |
Beginning of an M:Robe 500i port. Currently only in the bootloader stage. Needs another piece of code to start the boot process - will be in the wiki.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14763 a1c6a512-1295-4272-9138-f99709370657
34 files changed, 2651 insertions, 93 deletions
diff --git a/bootloader/SOURCES b/bootloader/SOURCES index 2de38930ea..2b499c1944 100644 --- a/bootloader/SOURCES +++ b/bootloader/SOURCES @@ -17,6 +17,8 @@ tpj1022.c iaudio_x5.c #elif defined(IRIVER_H300_SERIES) iriver_h300.c +#elif defined(MROBE_500) +mrobe500.c #else main.c #endif diff --git a/bootloader/mrobe500.c b/bootloader/mrobe500.c new file mode 100755 index 0000000000..02726dde5a --- /dev/null +++ b/bootloader/mrobe500.c @@ -0,0 +1,135 @@ +/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: $
+ *
+ * Copyright (C) 2007 by Karl Kurbjun
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+ #include "inttypes.h"
+#include "string.h"
+#include "cpu.h"
+#include "system.h"
+#include "lcd.h"
+#include "kernel.h"
+#include "thread.h"
+#include "ata.h"
+#include "fat.h"
+#include "disk.h"
+#include "font.h"
+#include "adc.h"
+#include "backlight.h"
+#include "backlight-target.h"
+#include "button.h"
+#include "panic.h"
+#include "power.h"
+#include "file.h"
+#include "common.h"
+#include "rbunicode.h"
+#include "usb.h"
+
+void main(void)
+{
+ unsigned char* loadbuffer;
+ int buffer_size;
+ int rc;
+ int(*kernel_entry)(void);
+
+ power_init();
+ system_init();
+ kernel_init();
+ adc_init();
+ button_init();
+ backlight_init();
+
+ lcd_init();
+ font_init();
+
+ lcd_setfont(FONT_SYSFIXED);
+
+ /* Show debug messages if button is pressed */
+// if(button_read_device())
+ verbose = true;
+
+ printf("Rockbox boot loader");
+ printf("Version %s", APPSVERSION);
+
+ usb_init();
+
+ #if 0
+ /* Enter USB mode without USB thread */
+ if(usb_detect())
+ {
+ const char msg[] = "Bootloader USB mode";
+ reset_screen();
+ lcd_putsxy( (LCD_WIDTH - (SYSFONT_WIDTH * strlen(msg))) / 2,
+ (LCD_HEIGHT - SYSFONT_HEIGHT) / 2, msg);
+ lcd_update();
+
+ ide_power_enable(true);
+ ata_enable(false);
+ sleep(HZ/20);
+ usb_enable(true);
+
+ while (usb_detect())
+ {
+ ata_spin(); /* Prevent the drive from spinning down */
+ sleep(HZ);
+ }
+
+ usb_enable(false);
+
+ reset_screen();
+ lcd_update();
+ }
+ #endif
+
+ printf("ATA");
+ while(true)
+ {
+ }
+#if 0
+ rc = ata_init();
+ if(rc)
+ {
+ reset_screen();
+ error(EATA, rc);
+ }
+
+ printf("disk");
+ disk_init();
+
+ printf("mount");
+ rc = disk_mount_all();
+ if (rc<=0)
+ {
+ error(EDISK,rc);
+ }
+
+ printf("Loading firmware");
+
+ loadbuffer = (unsigned char*) 0x00900000;
+ buffer_size = (unsigned char*)0x00100000 - loadbuffer;
+
+ rc = load_firmware(loadbuffer, BOOTFILE, buffer_size);
+ if(rc < 0)
+ error(EBOOTFILE, rc);
+
+ if (rc == EOK)
+ {
+ kernel_entry = (void*) loadbuffer;
+ rc = kernel_entry();
+ }
+#endif
+}
diff --git a/firmware/SOURCES b/firmware/SOURCES index 31b887c262..0f5da2fe6c 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES @@ -588,6 +588,24 @@ target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c #endif /* SIMULATOR */ #endif /* GIGABEAT_F */ +#ifdef MROBE_500 +#ifndef SIMULATOR +target/arm/olympus/mrobe-500/adc-mr500.c +target/arm/olympus/mrobe-500/ata-mr500.c +target/arm/olympus/mrobe-500/backlight-mr500.c +target/arm/olympus/mrobe-500/button-mr500.c +target/arm/olympus/mrobe-500/kernel-mr500.c +target/arm/olympus/mrobe-500/lcd-mr500.c +target/arm/olympus/mrobe-500/power-mr500.c +target/arm/olympus/mrobe-500/system-mr500.c +target/arm/olympus/mrobe-500/timer-mr500.c +target/arm/olympus/mrobe-500/usb-mr500.c +#ifndef BOOTLOADER + +#endif +#endif /* SIMULATOR */ +#endif /* MROBE_500 */ + #ifdef ELIO_TPJ1022 #ifndef SIMULATOR target/arm/ata-as-arm.S diff --git a/firmware/app.lds b/firmware/app.lds index 8b0bed31d2..998ac40791 100644 --- a/firmware/app.lds +++ b/firmware/app.lds @@ -28,9 +28,13 @@ INPUT(target/sh/crt0.o) #define STUBOFFSET 0 #endif -#if CONFIG_CPU!=S3C2440 +#if CONFIG_CPU==S3C2440 +#include "s3c2440.h" +#define DRAMSIZE (MEMORYSIZE * 0x100000) - 0x100 - PLUGINSIZE - STUBOFFSET - CODECSIZE - LCD_BUFFER_SIZE - TTB_SIZE +#else #define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE #endif + #if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300) #define DRAMORIG 0x31000000 + STUBOFFSET #define IRAMORIG 0x10000000 @@ -48,12 +52,14 @@ INPUT(target/sh/crt0.o) #define IRAMORIG 0x400000 #define IRAMSIZE 0x7000 #elif CONFIG_CPU==S3C2440 -#include "s3c2440.h" -#define DRAMORIG (0x100 + STUBOFFSET) -#define DRAMSIZE (MEMORYSIZE * 0x100000) - 0x100 - STUBOFFSET - LCD_BUFFER_SIZE - TTB_SIZE - PLUGINSIZE - CODECSIZE +#define DRAMORIG 0x00000100 + STUBOFFSET #define IRAMORIG DRAMORIG -#define IRAMSIZE 4K +#define IRAMSIZE 0x1000 #define IRAM DRAM +#elif CONFIG_CPU==DM320 +#define DRAMORIG 0x00900000 + STUBOFFSET +#define IRAMORIG 0x00000000 +#define IRAMSIZE 0x4000 #else #define DRAMORIG 0x09000000 + STUBOFFSET #define IRAMORIG 0x0f000000 @@ -79,7 +85,7 @@ MEMORY SECTIONS { -#ifndef CPU_ARM +#if !defined(CPU_ARM) .vectors : { loadaddress = .; @@ -136,7 +142,7 @@ SECTIONS *(.eh_frame) } -#ifdef CPU_ARM +#if defined(CPU_ARM) .vectors 0x0 : { _vectorsstart = .; diff --git a/firmware/boot.lds b/firmware/boot.lds index 7f7bb9b12f..0e2ccc1b90 100644 --- a/firmware/boot.lds +++ b/firmware/boot.lds @@ -57,6 +57,12 @@ INPUT(target/sh/crt0.o) #define IRAMSIZE 4K #define FLASHORIG 0x0000000 #define FLASHSIZE 1M +#elif CONFIG_CPU == DM320 +#define DRAMORIG 0x00900000 +#define IRAMORIG 0x00000000 +#define IRAMSIZE 16K +#define FLASHORIG 0x00100000 +#define FLASHSIZE 8M #elif CONFIG_CPU == PP5002 #define DRAMORIG 0x28000000 #define IRAMORIG 0x40000000 @@ -121,33 +127,94 @@ SECTIONS } #elif (CONFIG_CPU==S3C2440) { - . = DRAMORIG + 0x1000000; - .text : { - *(.init.text) - *(.text*) - } - .data : { - *(.icode) - *(.irodata) - *(.idata) - *(.data*) - _dataend = . ; - } - .stack : - { - *(.stack) - _stackbegin = .; - stackbegin = .; - . += 0x2000; - _stackend = .; - stackend = .; - } - .bss : { - _edata = .; - *(.bss*); - *(.ibss); - _end = .; - } + . = DRAMORIG + 0x1000000; + + .text : { + *(.init.text) + *(.text*) + } + + .data : { + *(.icode) + *(.irodata) + *(.idata) + *(.data*) + . = ALIGN(0x4); + _dataend = . ; + } + + .stack : + { + *(.stack) + _stackbegin = .; + stackbegin = .; + . += 0x2000; + _stackend = .; + stackend = .; + } + .bss : { + _edata = .; + *(.bss*); + *(.ibss); + _end = .; + } +} +#elif (CONFIG_CPU==DM320) +{ + . = DRAMORIG + 0x1000000; + + .vectors 0x0 : + { + _vectorsstart = .; + *(.vectors); + _vectorsend = .; + } AT> DRAM + _vectorscopy = LOADADDR(.vectors); + + .text : { + *(.init.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + . = ALIGN(0x4); + } > DRAM + + .rodata : + { + *(.rodata) /* problems without this, dunno why */ + *(.rodata*) + *(.rodata.str1.1) + *(.rodata.str1.4) + . = ALIGN(0x4); + + /* Pseudo-allocate the copies of the data sections */ + _datacopy = .; + } > DRAM + + .data : { + *(.icode) + *(.irodata) + *(.idata) + *(.data*) + . = ALIGN(0x4); + _dataend = . ; + } >DRAM + + .stack : + { + *(.stack) + _stackbegin = .; + stackbegin = .; + . += 0x2000; + _stackend = .; + stackend = .; + } >DRAM + .bss : { + _edata = .; + *(.bss*); + *(.ibss); + _end = .; + }>DRAM } #else { @@ -172,10 +239,10 @@ SECTIONS *(.idata) *(.data*) . = ALIGN(0x4); - _dataend = .; + _dataend = .; . = ALIGN(0x10); /* Maintain proper alignment for .text section */ } > IRAM - + /* TRICK ALERT! Newer versions of the linker don't allow output sections to overlap even if one of them is empty, so advance the location pointer "by hand" */ diff --git a/firmware/export/config-mrobe500.h b/firmware/export/config-mrobe500.h new file mode 100644 index 0000000000..3e74db68b4 --- /dev/null +++ b/firmware/export/config-mrobe500.h @@ -0,0 +1,129 @@ +/* + * This config file is for toshiba Gigabeat F + */ +#define TARGET_TREE /* this target is using the target tree system */ + +#define CONFIG_SDRAM_START 0x00900000 + +#define OLYMPUS_MROBE_500 1 + +/* For Rolo and boot loader */ +#define MODEL_NUMBER 19 + +/* define this if you have a bitmap LCD display */ +#define HAVE_LCD_BITMAP + +/* define this if you have a colour LCD */ +#define HAVE_LCD_COLOR + +/* define this if you have access to the quickscreen */ +#define HAVE_QUICKSCREEN + +/* define this if you have access to the pitchscreen */ +#define HAVE_PITCHSCREEN + +/* define this if you would like tagcache to build on this target */ +#define HAVE_TAGCACHE + +/* define this if the target has volume keys which can be used in the lists */ +#define HAVE_VOLUME_IN_LIST + +/* LCD dimensions */ +#define LCD_WIDTH 480 +#define LCD_HEIGHT 640 +#define LCD_DEPTH 16 /* 65k colours */ +#define LCD_PIXELFORMAT RGB565 /* rgb565 */ + +/* Define this if your LCD can be enabled/disabled */ +//#define HAVE_LCD_ENABLE + +#define CONFIG_KEYPAD MROBE500_PAD + +/* Define this if you do software codec */ +#define CONFIG_CODEC SWCODEC + +/* define this if you have a real-time clock */ +//#define CONFIG_RTC RTC_S3C2440 + +/* Define this for LCD backlight available */ +#define HAVE_BACKLIGHT + +#define HAVE_BACKLIGHT_BRIGHTNESS + +/* Main LCD backlight brightness range and defaults */ +#define MIN_BRIGHTNESS_SETTING 0 /* 0.5 mA */ +#define MAX_DIM_BRIGHTNESS_SETTING 15 /* highest 'dimness' */ +#define MAX_BRIGHTNESS_SETTING 63 /* 32 mA */ +#define DEFAULT_BRIGHTNESS_SETTING 39 /* 20 mA */ +#define DEFAULT_DIMNESS_SETTING 9 /* 5 mA */ + +/* Define this if you have a software controlled poweroff */ +#define HAVE_SW_POWEROFF + +/* The number of bytes reserved for loadable codecs */ +#define CODEC_SIZE 0x80000 + +/* The number of bytes reserved for loadable plugins */ +#define PLUGIN_BUFFER_SIZE 0x80000 + +/* Define this if you have the WM8975 audio codec */ +//#define HAVE_WM8751 + +/* Define this if you want to use the adaptive bass capibility of the 8751 */ +/* #define USE_ADAPTIVE_BASS */ + +#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | \ + SAMPR_CAP_11) + +#define BATTERY_CAPACITY_DEFAULT 1100 /* default battery capacity */ +#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */ +#define BATTERY_CAPACITY_MAX 2500 /* max. capacity selectable */ +#define BATTERY_CAPACITY_INC 100 /* capacity increment */ +#define BATTERY_TYPES_COUNT 1 /* only one type */ + +/* Hardware controlled charging with monitoring */ +#define CONFIG_CHARGING CHARGING_MONITOR + +#ifndef SIMULATOR + +/* Define this if you have a Motorola SCF5249 */ +#define CONFIG_CPU DM320 + +/* Define this if you want to use coldfire's i2c interface */ +//#define CONFIG_I2C I2C_S3C2440 + +/* define this if the hardware can be powered off while charging */ +#define HAVE_POWEROFF_WHILE_CHARGING + +/* The size of the flash ROM */ +#define FLASH_SIZE 0x400000 + +/* Define this to the CPU frequency */ +#define CPU_FREQ 16934400 + +/* Define this if you have ATA power-off control */ +#define HAVE_ATA_POWER_OFF + +/* Virtual LED (icon) */ +#define CONFIG_LED LED_VIRTUAL + +#define CONFIG_LCD LCD_MROBE500 + +/* define this if the backlight can be set to a brightness */ +#define HAVE_BACKLIGHT_SET_FADING +#define __BACKLIGHT_INIT + +/* Offset ( in the firmware file's header ) to the file CRC */ +#define FIRMWARE_OFFSET_FILE_CRC 0 + +/* Offset ( in the firmware file's header ) to the real data */ +#define FIRMWARE_OFFSET_FILE_DATA 8 + +/* Define this if you have adjustable CPU frequency */ +/* #define HAVE_ADJUSTABLE_CPU_FREQ */ + +#define BOOTFILE_EXT "mrobe500" +#define BOOTFILE "rockbox." BOOTFILE_EXT +#define BOOTDIR "/.rockbox" + +#endif diff --git a/firmware/export/config.h b/firmware/export/config.h index a18bf14a97..4a4185fdc3 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h @@ -48,6 +48,7 @@ #define PNX0101 101 #define S3C2440 2440 #define TMS320DSC25 25 +#define DM320 320 /* CONFIG_KEYPAD */ #define PLAYER_PAD 1 @@ -66,6 +67,7 @@ #define SANSA_C200_PAD 14 #define ELIO_TPJ1022_PAD 15 #define ARCHOS_AV300_PAD 16 +#define MROBE500_PAD 17 /* CONFIG_REMOTE_KEYPAD */ #define H100_REMOTE 1 @@ -97,6 +99,7 @@ #define LCD_TPJ1022 15 /* as used by Tatung Elio TPJ-1022 */ #define LCD_DSC25 16 /* as used by Archos AV300 */ #define LCD_C200 17 /* as used by Sandisk Sansa c200 */ +#define LCD_MROBE500 18 /* as used by Olympus M:Robe 500i */ /* LCD_PIXELFORMAT */ #define HORIZONTAL_PACKING 1 @@ -197,6 +200,8 @@ #include "config-c200.h" #elif defined(ELIO_TPJ1022) #include "config-tpj1022.h" +#elif defined(MROBE_500) +#include "config-mrobe500.h" #else /* no known platform */ #endif @@ -294,7 +299,7 @@ /* define for all cpus from ARM family */ #if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \ - || (CONFIG_CPU == TMS320DSC25) + || (CONFIG_CPU == TMS320DSC25) || (CONFIG_CPU == DM320) #define CPU_ARM #endif diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h index eb1c57b646..ff9fbeec3a 100644 --- a/firmware/export/cpu.h +++ b/firmware/export/cpu.h @@ -42,3 +42,6 @@ #if CONFIG_CPU == S3C2440 #include "s3c2440.h" #endif +#if CONFIG_CPU == DM320 +#include "dm320.h" +#endif diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h new file mode 100644 index 0000000000..5e164cff57 --- /dev/null +++ b/firmware/export/dm320.h @@ -0,0 +1,704 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +/** All register offset definitions for the TI DM320 + * Taken from: http://svn.neurostechnology.com/filedetails.php?repname=neuros-bsp&path=%2Ftrunk%2Fkernels%2Flinux-2.6.15%2Finclude%2Fasm-arm%2Farch-ntosd-dm320%2Fio_registers.h&rev=0&sc=0 + */ + +#ifndef __DM320_H__ +#define __DM320_H__ + +#define FRAME ((short *) (0x4470000)) + +#define PHY_IO_BASE 0x00030000 + +/* Timer 0-3 */ +#define IO_TIMER0_TMMD 0x0000 +#define IO_TIMER0_TMRSV0 0x0002 +#define IO_TIMER0_TMPRSCL 0x0004 +#define IO_TIMER0_TMDIV 0x0006 +#define IO_TIMER0_TMTRG 0x0008 +#define IO_TIMER0_TMCNT 0x000A + +#define IO_TIMER1_TMMD 0x0080 +#define IO_TIMER1_TMRSV0 0x0082 +#define IO_TIMER1_TMPRSCL 0x0084 +#define IO_TIMER1_TMDIV 0x0086 +#define IO_TIMER1_TMTRG 0x0088 +#define IO_TIMER1_TMCNT 0x008A + +#define IO_TIMER2_TMMD 0x0100 +#define IO_TIMER2_TMVDCLR 0x0102 +#define IO_TIMER2_TMPRSCL 0x0104 +#define IO_TIMER2_TMDIV 0x0106 +#define IO_TIMER2_TMTRG 0x0108 +#define IO_TIMER2_TMCNT 0x010A + +#define IO_TIMER3_TMMD 0x0180 +#define IO_TIMER3_TMVDCLR 0x0182 +#define IO_TIMER3_TMPRSCL 0x0184 +#define IO_TIMER3_TMDIV 0x0186 +#define IO_TIMER3_TMTRG 0x0188 +#define IO_TIMER3_TMCNT 0x018A + +/* Serial 0/1 */ +#define IO_SERIAL0_TX_DATA 0x0200 +#define IO_SERIAL0_RX_DATA 0x0202 +#define IO_SERIAL0_TX_ENABLE 0x0204 +#define IO_SERIAL0_MODE 0x0206 +#define IO_SERIAL0_DMA_TRIGGER 0x0208 +#define IO_SERIAL0_DMA_MODE 0x020A +#define IO_SERIAL0_DMA_SDRAM_LOW 0x020C +#define IO_SERIAL0_DMA_SDRAM_HI 0x020E +#define IO_SERIAL0_DMA_STATUS 0x0210 + +#define IO_SERIAL1_TX_DATA 0x0280 +#define IO_SERIAL1_RX_DATA 0x0282 +#define IO_SERIAL1_TX_ENABLE 0x0284 +#define IO_SERIAL1_MODE 0x0286 + +/* UART 0/1 */ +#define IO_UART0_DTRR 0x0300 +#define IO_UART0_BRSR 0x0302 +#define IO_UART0_MSR 0x0304 +#define IO_UART0_RFCR 0x0306 +#define IO_UART0_TFCR 0x0308 +#define IO_UART0_LCR 0x030A +#define IO_UART0_SR 0x030C + +#define IO_UART1_DTRR 0x0380 +#define IO_UART1_BRSR 0x0382 +#define IO_UART1_MSR 0x0384 +#define IO_UART1_RFCR 0x0386 +#define IO_UART1_TFCR 0x0388 +#define IO_UART1_LCR 0x038A +#define IO_UART1_SR 0x038C + +/* Watchdog Timer */ +#define IO_WATCHDOG_MODE 0x0400 +#define IO_WATCHDOG_RESET 0x0402 +#define IO_WATCHDOG_PRESCALAR 0x0404 +#define IO_WATCHDOG_DIVISOR 0x0406 +#define IO_WATCHDOG_EXT_RESET 0x0408 + +/* MMC/SD Controller */ +#define IO_MMC_CONTROL 0x0480 +#define IO_MMC_MEM_CLK_CONTROL 0x0482 +#define IO_MMC_STATUS0 0x0484 +#define IO_MMC_STATUS1 0x0486 +#define IO_MMC_INT_ENABLE 0x0488 +#define IO_MMC_RESPONSE_TIMEOUT 0x048A +#define IO_MMC_READ_TIMEOUT 0x048C +#define IO_MMC_BLOCK_LENGTH 0x048E +#define IO_MMC_NR_BLOCKS 0x0490 +#define IO_MMC_NR_BLOCKS_COUNT 0x0492 +#define IO_MMC_RX_DATA 0x0494 +#define IO_MMC_TX_DATA 0x0496 +#define IO_MMC_COMMAND 0x0498 +#define IO_MMC_ARG_LOW 0x049A +#define IO_MMC_ARG_HI 0x049C +#define IO_MMC_RESPONSE0 0x049E +#define IO_MMC_RESPONSE1 0x04A0 +#define IO_MMC_RESPONSE2 0x04A2 +#define IO_MMC_RESPONSE3 0x04A4 +#define IO_MMC_RESPONSE4 0x04A6 +#define IO_MMC_RESPONSE5 0x04A8 +#define IO_MMC_RESPONSE6 0x04AA +#define IO_MMC_RESPONSE7 0x04AC +#define IO_MMC_SPI_DATA 0x04AE +#define IO_MMC_SPI_ERR 0x04B0 +#define IO_MMC_COMMAND_INDEX 0x04B2 +#define IO_MMC_CLK_START_PHASE 0x04B4 +#define IO_MMC_RESPONSE_TOUT_CNT 0x04B6 +#define IO_MMC_READ_TOUT_CNT 0x04B8 +#define IO_MMC_BLOCK_LENGTH_CNT 0x04BA + +#define IO_MMC_SD_DMA_TRIGGER 0x04BC +#define IO_MMC_SD_DMA_MODE 0x04BE +#define IO_MMC_SD_DMA_ADDR_LOW 0x04C0 +#define IO_MMC_SD_DMA_ADDR_HI 0x04C2 +#define IO_MMC_SD_DMA_STATUS0 0x04C4 +#define IO_MMC_SD_DMA_STATUS1 0x04C6 +#define IO_MMC_SD_DMA_TIMEOUT 0x04C8 + +#define IO_SDIO_CONTROL 0x04CA +#define IO_SDIO_STATUS0 0x04CC +#define IO_SDIO_INT_ENABLE 0x04CE +#define IO_SDIO_INT_STATUS 0x04D0 + +/* Interrupt Controller */ +#define IO_INTC_FIQ0 0x0500 +#define IO_INTC_FIQ1 0x0502 +#define IO_INTC_FIQ2 0x0504 +#define IO_INTC_IRQ0 0x0508 +#define IO_INTC_IRQ1 0x050A +#define IO_INTC_IRQ2 0x050C +#define IO_INTC_FIQENTRY0 0x0510 +#define IO_INTC_FIQENTRY1 0x0512 +#define IO_INTC_FIQ_LOCK_ADDR0 0x0514 +#define IO_INTC_FIQ_LOCK_ADDR1 0x0516 +#define IO_INTC_IRQENTRY0 0x0518 +#define IO_INTC_IRQENTRY1 0x051A +#define IO_INTC_IRQ_LOCK_ADDR0 0x051C +#define IO_INTC_IRQ_LOCK_ADDR1 0x051E +#define IO_INTC_FISEL0 0x0520 +#define IO_INTC_FISEL1 0x0522 +#define IO_INTC_FISEL2 0x0524 +#define IO_INTC_EINT0 0x0528 +#define IO_INTC_EINT1 0x052A +#define IO_INTC_EINT2 0x052C +#define IO_INTC_RAW 0x0530 +#define IO_INTC_ENTRY_TBA0 0x0538 +#define IO_INTC_ENTRY_TBA1 0x053A +#define IO_INTC_PRIORITY0 0x0540 +#define IO_INTC_PRIORITY1 0x0542 +#define IO_INTC_PRIORITY2 0x0544 +#define IO_INTC_PRIORITY3 0x0546 +#define IO_INTC_PRIORITY4 0x0548 +#define IO_INTC_PRIORITY5 0x054A +#define IO_INTC_PRIORITY6 0x054C +#define IO_INTC_PRIORITY7 0x054E +#define IO_INTC_PRIORITY8 0x0550 +#define IO_INTC_PRIORITY9 0x0552 +#define IO_INTC_PRIORITY10 0x0554 +#define IO_INTC_PRIORITY11 0x0556 +#define IO_INTC_PRIORITY12 0x0558 +#define IO_INTC_PRIORITY13 0x055A +#define IO_INTC_PRIORITY14 0x055C +#define IO_INTC_PRIORITY15 0x055E +#define IO_INTC_PRIORITY16 0x0560 +#define IO_INTC_PRIORITY17 0x0562 +#define IO_INTC_PRIORITY18 0x0564 +#define IO_INTC_PRIORITY19 0x0566 +#define IO_INTC_PRIORITY20 0x0568 +#define IO_INTC_PRIORITY21 0x056A +#define IO_INTC_PRIORITY22 0x056C + +/* GIO Controller */ +#define IO_GIO_DIR0 0x0580 +#define IO_GIO_DIR1 0x0582 +#define IO_GIO_DIR2 0x0584 +#define IO_GIO_INV0 0x0586 +#define IO_GIO_INV1 0x0588 +#define IO_GIO_INV2 0x058A +#define IO_GIO_BITSET0 0x058C +#define IO_GIO_BITSET1 0x058E +#define IO_GIO_BITSET2 0x0590 +#define IO_GIO_BITCLR0 0x0592 +#define IO_GIO_BITCLR1 0x0594 +#define IO_GIO_BITCLR2 0x0596 +#define IO_GIO_IRQPORT 0x0598 +#define IO_GIO_IRQEDGE 0x059A +#define IO_GIO_CHAT0 0x059C +#define IO_GIO_CHAT1 0x059E +#define IO_GIO_CHAT2 0x05A0 +#define IO_GIO_NCHAT 0x05A2 +#define IO_GIO_FSEL0 0x05A4 +#define IO_GIO_FSEL1 0x05A6 +#define IO_GIO_FSEL2 0x05A8 +#define IO_GIO_FSEL3 0x05AA +#define IO_GIO_FSEL4 0x05AC +#define IO_GIO_CARD_SET 0x05AE +#define IO_GIO_CARD_ST 0x05B0 + +/* DSP Controller */ +#define IO_DSPC_HPIB_CONTROL 0x0600 +#define IO_DSPC_HPIB_STATUS 0x0602 + +/* OSD Controller */ +#define IO_OSD_MODE 0x0680 +#define IO_OSD_VIDWINMD 0x0682 +#define IO_OSD_OSDWINMD0 0x0684 +#define IO_OSD_OSDWINMD1 0x0686 +#define IO_OSD_ATRMD 0x0688 +#define IO_OSD_RECTCUR 0x0688 +#define IO_OSD_RESERVED 0x068A +#define IO_OSD_VIDWIN0OFST 0x068C +#define IO_OSD_VIDWIN1OFST 0x068E +#define IO_OSD_OSDWIN0OFST 0x0690 +#define IO_OSD_OSDWIN1OFST 0x0692 +#define IO_OSD_VIDWINADH 0x0694 +#define IO_OSD_VIDWIN0ADL 0x0696 +#define IO_OSD_VIDWIN1ADL 0x0698 +#define IO_OSD_OSDWINADH 0x069A +#define IO_OSD_OSDWIN0ADL 0x069C +#define IO_OSD_OSDWIN1ADL 0x069E +#define IO_OSD_BASEPX 0x06A0 +#define IO_OSD_BASEPY 0x06A2 +#define IO_OSD_VIDWIN0XP 0x06A4 +#define IO_OSD_VIDWIN0YP 0x06A6 +#define IO_OSD_VIDWIN0XL 0x06A8 +#define IO_OSD_VIDWIN0YL 0x06AA +#define IO_OSD_VIDWIN1XP 0x06AC +#define IO_OSD_VIDWIN1YP 0x06AE +#define IO_OSD_VIDWIN1XL 0x06B0 +#define IO_OSD_VIDWIN1YL 0x06B2 + +#define IO_OSD_OSDWIN0XP 0x06B4 +#define IO_OSD_OSDWIN0YP 0x06B6 +#define IO_OSD_OSDWIN0XL 0x06B8 +#define IO_OSD_OSDWIN0YL 0x06BA +#define IO_OSD_OSDWIN1XP 0x06BC +#define IO_OSD_OSDWIN1YP 0x06BE +#define IO_OSD_OSDWIN1XL 0x06C0 +#define IO_OSD_OSDWIN1YL 0x06C2 +#define IO_OSD_CURXP 0x06C4 +#define IO_OSD_CURYP 0x06C6 +#define IO_OSD_CURXL 0x06C8 +#define IO_OSD_CURYL 0x06CA + +#define IO_OSD_W0BMP01 0x06D0 +#define IO_OSD_W0BMP23 0x06D2 +#define IO_OSD_W0BMP45 0x06D4 +#define IO_OSD_W0BMP67 0x06D6 +#define IO_OSD_W0BMP89 0x06D8 +#define IO_OSD_W0BMPAB 0x06DA +#define IO_OSD_W0BMPCD 0x06DC +#define IO_OSD_W0BMPEF 0x06DE + +#define IO_OSD_W1BMP01 0x06E0 +#define IO_OSD_W1BMP23 0x06E2 +#define IO_OSD_W1BMP45 0x06E4 +#define IO_OSD_W1BMP67 0x06E6 +#define IO_OSD_W1BMP89 0x06E8 +#define IO_OSD_W1BMPAB 0x06EA +#define IO_OSD_W1BMPCD 0x06EC +#define IO_OSD_W1BMPEF 0x06EE + +#define IO_OSD_MISCCTL 0x06F4 +#define IO_OSD_CLUTRAMYCB 0x06F6 +#define IO_OSD_CLUTRAMCR 0x06F8 + +#define IO_OSD_PPWIN0ADH 0x06FC +#define IO_OSD_PPWIN0ADL 0x06FE + + +/* CCD Controller */ +#define IO_CCD_SYNCEN 0x0700 +#define IO_CCD_MODESET 0x0702 +#define IO_CCD_HDWIDTH 0x0704 +#define IO_CCD_VDWIDTH 0x0706 +#define IO_CCD_PPLN 0x0708 +#define IO_CCD_LPFR 0x070A +#define IO_CCD_SPH 0x070C +#define IO_CCD_NPH 0x070E +#define IO_CCD_SLV0 0x0710 +#define IO_CCD_SLV1 0x0712 +#define IO_CCD_NLV 0x0714 +#define IO_CCD_CULH 0x0716 +#define IO_CCD_CULV 0x0718 +#define IO_CCD_HSIZE 0x071A +#define IO_CCD_SDOFST 0x071C +#define IO_CCD_STADRH 0x071E +#define IO_CCD_STADRL 0x0720 +#define IO_CCD_CLAMP 0x0722 +#define IO_CCD_DCSUB 0x0724 +#define IO_CCD_COLPTN 0x0726 +#define IO_CCD_BLKCMP0 0x0728 +#define IO_CCD_BLKCMP1 0x072A +#define IO_CCD_MEDFILT 0x072C +#define IO_CCD_RYEGAN 0x072E /* this is kept on the odd chance that some code is using the misspelled reg */ +#define IO_CCD_RYEGAIN 0x072E +#define IO_CCD_GRCYGAIN 0x0730 +#define IO_CCD_GBGGAIN 0x0732 +#define IO_CCD_BMGGAIN 0x0734 +#define IO_CCD_OFFSET 0x0736 +#define IO_CCD_OUTCLP 0x0738 +#define IO_CCD_VDINT0 0x073A +#define IO_CCD_VDINT1 0x073C +#define IO_CCD_RSV0 0x073E +#define IO_CCD_GAMMAWD 0x0740 +#define IO_CCD_REC656IF 0x0742 +#define IO_CCD_CCDFG 0x0744 +#define IO_CCD_FMTCFG 0x0746 +#define IO_CCD_FMTSPH 0x0748 +#define IO_CCD_FMTLNH 0x074A +#define IO_CCD_FMTSLV 0x074C +#define IO_CCD_FMTSNV 0x074E +#define IO_CCD_FMTOFST 0x0750 +#define IO_CCD_FMTRLEN 0x0752 +#define IO_CCD_FMTHCNT 0x0754 +#define IO_CCD_FMTPTNA 0x0756 +#define IO_CCD_FMTPTNB 0x0758 + +/* NTSC/PAL Encoder */ +#define IO_VID_ENC_VMOD 0x0800 +#define IO_VID_ENC_VDCTL 0x0802 +#define IO_VID_ENC_VDPRO 0x0804 +#define IO_VID_ENC_SYNCCTL 0x0806 +#define IO_VID_ENC_HSPLS 0x0808 +#define IO_VID_ENC_VSPLS 0x080A +#define IO_VID_ENC_HINT 0x080C +#define IO_VID_ENC_HSTART 0x080E +#define IO_VID_ENC_HVALID 0x0810 +#define IO_VID_ENC_VINT 0x0812 +#define IO_VID_ENC_VSTART 0x0814 +#define IO_VID_ENC_VVALID 0x0816 +#define IO_VID_ENC_HSDLY 0x0818 +#define IO_VID_ENC_VSDLY 0x081A +#define IO_VID_ENC_YCCTL 0x081C +#define IO_VID_ENC_RGBCTL 0x081E +#define IO_VID_ENC_RGBCLP 0x0820 +#define IO_VID_ENC_LNECTL 0x0822 +#define IO_VID_ENC_CULLLNE 0x0824 +#define IO_VID_ENC_LCDOUT 0x0826 +#define IO_VID_ENC_BRTS 0x0828 +#define IO_VID_ENC_BRTW 0x082A +#define IO_VID_ENC_ACCTL 0x082C +#define IO_VID_ENC_PWMP 0x082E +#define IO_VID_ENC_PWMW 0x0830 +#define IO_VID_ENC_DCLKCTL 0x0832 +#define IO_VID_ENC_DCLKPTN0 0x0834 +#define IO_VID_ENC_DCLKPTN1 0x0836 +#define IO_VID_ENC_DCLKPTN2 0x0838 +#define IO_VID_ENC_DCLKPTN3 0x083A +#define IO_VID_ENC_DCLKPTN0A 0x083C +#define IO_VID_ENC_DCLKPTN1A 0x083E +#define IO_VID_ENC_DCLKPTN2A 0x0840 +#define IO_VID_ENC_DCLKPTN3A 0x0842 +#define IO_VID_ENC_DCLKHS 0x0844 +#define IO_VID_ENC_DCLKHSA 0x0846 +#define IO_VID_ENC_DCLKHR 0x0848 +#define IO_VID_ENC_DCLKVS 0x084A +#define IO_VID_ENC_DCLKVR 0x084C +#define IO_VID_ENC_CAPCTL 0x084E +#define IO_VID_ENC_CAPDO 0x0850 +#define IO_VID_ENC_CAPDE 0x0852 +#define IO_VID_ENC_ATR0 0x0854 + +/* Clock Controller */ +#define IO_CLK_PLLA 0x0880 +#define IO_CLK_PLLB 0x0882 +#define IO_CLK_SEL0 0x0884 +#define IO_CLK_SEL1 0x0886 +#define IO_CLK_SEL2 0x0888 +#define IO_CLK_DIV0 0x088A +#define IO_CLK_DIV1 0x088C +#define IO_CLK_DIV2 0x088E +#define IO_CLK_DIV3 0x0890 +#define IO_CLK_DIV4 0x0892 +#define IO_CLK_BYP 0x0894 +#define IO_CLK_INV 0x0896 +#define IO_CLK_MOD0 0x0898 +#define IO_CLK_MOD1 0x089A +#define IO_CLK_MOD2 0x089C +#define IO_CLK_LPCTL0 0x089E +#define IO_CLK_LPCTL1 0x08A0 +#define IO_CLK_OSEL 0x08A2 +#define IO_CLK_00DIV 0x08A4 +#define IO_CLK_O1DIV 0x08A6 +#define IO_CLK_02DIV 0x08A8 +#define IO_CLK_PWM0C 0x08AA +#define IO_CLK_PWM0H 0x08AC +#define IO_CLK_PWM1C 0x08AE +#define IO_CLK_PWM1H 0x08B0 + +/* Bus Controller */ +#define IO_BUSC_ECR 0x0900 +#define IO_BUSC_EBYTER 0x0902 +#define IO_BUSC_EBITR 0x0904 +#define IO_BUSC_REVR 0x0906 + +/* SDRAM Controller */ +#define IO_SDRAM_SDBUFD0L 0x0980 +#define IO_SDRAM_SDBUFD0H 0x0982 +#define IO_SDRAM_SDBUFD1L 0x0984 +#define IO_SDRAM_SDBUFD1H 0x0986 +#define IO_SDRAM_SDBUFD2L 0x0988 +#define IO_SDRAM_SDBUFD2H 0x098A +#define IO_SDRAM_SDBUFD3L 0x098C +#define IO_SDRAM_SDBUFD3H 0x098E +#define IO_SDRAM_SDBUFD4L 0x0990 +#define IO_SDRAM_SDBUFD4H 0x0992 +#define IO_SDRAM_SDBUFD5L 0x0994 +#define IO_SDRAM_SDBUFD5H 0x0996 +#define IO_SDRAM_SDBUFD6L 0x0998 +#define IO_SDRAM_SDBUFD6H 0x099A +#define IO_SDRAM_SDBUFD7L 0x099C +#define IO_SDRAM_SDBUFD7H 0x099E +#define IO_SDRAM_SDBUFAD1 0x09A0 +#define IO_SDRAM_SDBUFAD2 0x09A2 +#define IO_SDRAM_SDBUFCTL 0x09A4 +#define IO_SDRAM_SDMODE 0x09A6 +#define IO_SDRAM_REFCTL 0x09A8 +#define IO_SDRAM_SDPRTY1 0x09AA +#define IO_SDRAM_SDPRTY2 0x09AC +#define IO_SDRAM_SDPRTY3 0x09AE +#define IO_SDRAM_SDPRTY4 0x09B0 +#define IO_SDRAM_SDPRTY5 0x09B2 +#define IO_SDRAM_SDPRTY6 0x09B4 +#define IO_SDRAM_SDPRTY7 0x09B6 +#define IO_SDRAM_SDPRTY8 0x09B8 +#define IO_SDRAM_SDPRTY9 0x09BA +#define IO_SDRAM_SDPRTY10 0x09BC +#define IO_SDRAM_SDPRTY11 0x09BE +#define IO_SDRAM_SDPRTY12 0x09C0 +#define IO_SDRAM_RSV 0x09C2 +#define IO_SDRAM_SDPRTYON 0x09C4 +#define IO_SDRAM_SDDMASEL 0x09C6 + +/* EMIF Controller */ +#define IO_EMIF_CS0CTRL1 0x0A00 +#define IO_EMIF_CS0CTRL2 0x0A02 +#define IO_EMIF_CS0CTRL3 0x0A04 +#define IO_EMIF_CS1CTRL1A 0x0A06 +#define IO_EMIF_CS1CTRL1B 0x0A08 +#define IO_EMIF_CS1CTRL2 0x0A0A +#define IO_EMIF_CS2CTRL1 0x0A0C +#define IO_EMIF_CS2CTRL2 0x0A0E +#define IO_EMIF_CS3CTRL1 0x0A10 +#define IO_EMIF_CS3CTRL2 0x0A12 +#define IO_EMIF_CS4CTRL1 0x0A14 +#define IO_EMIF_CS4CTRL2 0x0A16 +#define IO_EMIF_BUSCTRL 0x0A18 +#define IO_EMIF_BUSRLS 0x0A1A +#define IO_EMIF_CFCTRL1 0x0A1C +#define IO_EMIF_CFCTRL2 0x0A1E +#define IO_EMIF_SMCTRL 0x0A20 +#define IO_EMIF_BUSINTEN 0x0A22 +#define IO_EMIF_BUSSTS 0x0A24 +#define IO_EMIF_BUSWAITMD 0x0A26 +#define IO_EMIF_ECC1CP 0x0A28 +#define IO_EMIF_ECC1LP 0x0A2A +#define IO_EMIF_ECC2CP 0x0A2C +#define IO_EMIF_ECC2LP 0x0A2E +#define IO_EMIF_ECC3CP 0x0A30 +#define IO_EMIF_ECC3LP 0x0A32 +#define IO_EMIF_ECC4CP 0x0A34 +#define IO_EMIF_ECC4LP 0x0A36 +#define IO_EMIF_ECC5CP 0x0A38 +#define IO_EMIF_ECC5LP 0x0A3A +#define IO_EMIF_ECC6CP 0x0A3C +#define IO_EMIF_ECC6LP 0x0A3E +#define IO_EMIF_ECC7CP 0x0A40 +#define IO_EMIF_ECC7LP 0x0A42 +#define IO_EMIF_ECC8CP 0x0A44 +#define IO_EMIF_ECC8LP 0x0A46 +#define IO_EMIF_ECCCLR 0x0A48 +#define IO_EMIF_PAGESZ 0x0A4A +#define IO_EMIF_PRIORCTL 0x0A4C +#define IO_EMIF_MGDSPDEST 0x0A4E +#define IO_EMIF_MGDSPADDH 0x0A50 +#define IO_EMIF_MGDSPADDL 0x0A52 +#define IO_EMIF_AHBADDH 0x0A54 +#define IO_EMIF_AHBADDL 0x0A56 +#define IO_EMIF_MTCADDH 0x0A58 +#define IO_EMIF_MTCADDL 0x0A5A +#define IO_EMIF_DMASIZE 0x0A5C +#define IO_EMIF_DMAMTCSEL 0x0A5E +#define IO_EMIF_DMACTL 0x0A60 + +/* Preivew Engine */ +#define IO_PREV_ENG_PVEN 0x0A80 +#define IO_PREV_ENG_PVSET1 0x0A82 +#define IO_PREV_ENG_RADRH 0x0A84 +#define IO_PREV_ENG_RADRL 0x0A86 +#define IO_PREV_ENG_WADRH 0x0A88 +#define IO_PREV_ENG_WADRL 0x0A8A +#define IO_PREV_ENG_HSTART 0x0A8C +#define IO_PREV_ENG_HSIZE 0x0A8E +#define IO_PREV_ENG_VSTART 0x0A90 +#define IO_PREV_ENG_VSIZE 0x0A92 +#define IO_PREV_ENG_PVSET2 0x0A94 +#define IO_PREV_ENG_NFILT 0x0A96 +#define IO_PREV_ENG_DGAIN 0x0A98 +#define IO_PREV_ENG_WBGAIN0 0x0A9A +#define IO_PREV_ENG_WBGAIN1 0x0A9C +#define IO_PREV_ENG_SMTH 0x0A9E +#define IO_PREV_ENG_HRSZ 0x0AA0 +#define IO_PREV_ENG_VRSZ 0x0AA2 +#define IO_PREV_ENG_BLOFST0 0x0AA4 +#define IO_PREV_ENG_BLOFST1 0x0AA6 +#define IO_PREV_ENG_MTXGAIN0 0x0AA8 +#define IO_PREV_ENG_MTXGAIN1 0x0AAA +#define IO_PREV_ENG_MTXGAIN2 0x0AAC +#define IO_PREV_ENG_MTXGAIN3 0x0AAE +#define IO_PREV_ENG_MTXGAIN4 0x0AB0 +#define IO_PREV_ENG_MTXGAIN5 0x0AB2 +#define IO_PREV_ENG_MTXGAIN6 0x0AB4 +#define IO_PREV_ENG_MTXGAIN7 0x0AB6 +#define IO_PREV_ENG_MTXGAIN8 0x0AB8 +#define IO_PREV_ENG_MTXOFST0 0x0ABA +#define IO_PREV_ENG_MTXOFST1 0x0ABC +#define IO_PREV_ENG_MTXOFST2 0x0ABE +#define IO_PREV_ENG_GAMTBYP 0x0AC0 +#define IO_PREV_ENG_CSC0 0x0AC2 +#define IO_PREV_ENG_CSC1 0x0AC4 +#define IO_PREV_ENG_CSC2 0x0AC6 +#define IO_PREV_ENG_CSC3 0x0AC8 +#define IO_PREV_ENG_CSC4 0x0ACA +#define IO_PREV_ENG_YOFST 0x0ACC +#define IO_PREV_ENG_COFST 0x0ACE +#define IO_PREV_ENG_CNTBRT 0x0AD0 +#define IO_PREV_ENG_CSUP0 0x0AD2 +#define IO_PREV_ENG_CSUP1 0x0AD4 +#define IO_PREV_ENG_SETUPY 0x0AD4 +#define IO_PREV_ENG_SETUPC 0x0AD8 +#define IO_PREV_ENG_TABLE_ADDR 0x0ADA +#define IO_PREV_ENG_TABLE_DATA 0x0ADC +#define IO_PREV_ENG_HG_CTL 0x0ADE +#define IO_PREV_ENG_HG_R0_HSTART 0x0AE0 +#define IO_PREV_ENG_HG_R0_HSIZE 0x0AE2 +#define IO_PREV_ENG_HG_R0_VSTART 0x0AE4 +#define IO_PREV_ENG_HR_R0_VSIZE 0x0AE6 +#define IO_PREV_ENG_HG_R1_HSTART 0x0AE8 +#define IO_PREV_ENG_HG_R1_HSIZE 0x0AEA +#define IO_PREV_ENG_HG_R1_VSTART 0x0AEC +#define IO_PREV_ENG_HG_R1_VSIZE 0x0AEE +#define IO_PREV_ENG_HG_R2_HSTART 0x0AF0 +#define IO_PREV_ENG_HG_R2_HSIZE 0x0AF2 +#define IO_PREV_ENG_HG_R2_VSTART 0x0AF4 +#define IO_PREV_ENG_HG_R2_VSIZE 0x0AF6 +#define IO_PREV_ENG_HG_R3_HSTART 0x0AF8 +#define IO_PREV_ENG_HG_R3_HSIZE 0x0AFA +#define IO_PREV_ENG_HG_R3_VSTART 0x0AFC +#define IO_PREV_ENG_HG_R3_VSIZE 0x0AFE +#define IO_PREV_ENG_HG_ADDR 0x0B00 +#define IO_PREV_ENG_HG_DATA 0x0B02 + +/* H3A Hardware */ +#define IO_H3A_H3ACTRL 0x0B80 +#define IO_H3A_AFCTRL 0x0B82 +#define IO_H3A_AFPAX1 0x0B84 +#define IO_H3A_AFPAX2 0x0B86 +#define IO_H3A_AFPAX3 0x0B88 +#define IO_H3A_AFPAX4 0x0B8A +#define IO_H3A_AFIRSH 0x0B8C +#define IO_H3A_AFPAX5 0x0B8E +#define IO_H3A_AFSDRA1 0x0B90 +#define IO_H3A_AFSDRA2 0x0B92 +#define IO_H3A_AFSDRFLG 0x0B94 +#define IO_H3A_AFCOEFF10 0x0B96 +#define IO_H3A_AFCOEFF11 0x0B98 +#define IO_H3A_AFCOEFF12 0x0B9A +#define IO_H3A_AFCOEFF13 0x0B9C +#define IO_H3A_AFCOEFF14 0x0B9E +#define IO_H3A_AFCOEFF15 0x0BA0 +#define IO_H3A_AFCOEFF16 0x0BA2 +#define IO_H3A_AFCOEFF17 0x0BA4 +#define IO_H3A_AFCOEFF18 0x0BA6 +#define IO_H3A_AFCOEFF19 0x0BA8 +#define IO_H3A_AFCOEFF110 0x0BAA +#define IO_H3A_AFCOEFF20 0x0BAC +#define IO_H3A_AFCOEFF21 0x0BAE +#define IO_H3A_AFCOEFF22 0x0BB0 +#define IO_H3A_AFCOEFF23 0x0BB2 +#define IO_H3A_AFCOEFF24 0x0BB4 +#define IO_H3A_AFCOEFF25 0x0BB6 +#define IO_H3A_AFCOEFF26 0x0BB8 +#define IO_H3A_AFCOEFF27 0x0BBA +#define IO_H3A_AFCOEFF28 0x0BBC +#define IO_H3A_AFCOEFF29 0x0BBE +#define IO_H3A_AFCOEFF210 0x0BC0 +#define IO_H3A_AEWCTRL 0x0BC2 +#define IO_H3A_AEWWIN1 0x0BC4 +#define IO_H3A_AEWWIN2 0x0BC6 +#define IO_H3A_AEWWIN3 0x0BC8 +#define IO_H3A_AEWWIN4 0x0BCA +#define IO_H3A_AEWWIN5 0x0BCC +#define IO_H3A_AEWSDRA1 0x0BCE +#define IO_H3A_AEWSDRA2 0x0BD0 +#define IO_H3A_AEWSDRFLG 0x0BD2 + +/* Reserved 0x0C00 - 0x0CCFF */ + +/* Memory Stick Controller : */ +#define IO_MEM_STICK_MODE 0x0C80 +#define IO_MEM_STICK_CMD 0x0C82 +#define IO_MEM_STICK_DATA 0x0C84 +#define IO_MEM_STICK_STATUS 0x0C86 +#define IO_MEM_STICK_SYS 0x0C88 +#define IO_MEM_STICK_ENDIAN 0x0C8A +#define IO_MEM_STICK_INT_STATUS 0x0C8C +#define IO_MEM_STICK_DMA_TRG 0x0C8E +#define IO_MEM_STICK_DMA_MODE 0x0C90 +#define IO_MEM_STICK_SDRAM_ADDL 0x0C92 +#define IO_MEM_STICK_SDRAM_ADDH 0x0C94 +#define IO_MEM_STICK_DMA_STATUS 0x0C96 + +/* ATM : WBB Need to find these Register values */ +#define IO_ATM_ 0x0D00 + +/* I2C */ +#define IO_I2C_TXDATA 0x0D80 +#define IO_I2C_RXDATA 0x0D82 +#define IO_I2C_SCS 0x0D84 + +/* Taken from linux/include/asm-arm/arch-itdm320/irqs.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2004 Ingenient Technologies + */ + +/* + * Interrupt numbers + */ +#define IRQ_TIMER0 0 +#define IRQ_TIMER1 1 +#define IRQ_TIMER2 2 +#define IRQ_TIMER3 3 +#define IRQ_CCD_VD0 4 +#define IRQ_CCD_VD1 5 +#define IRQ_CCD_WEN 6 +#define IRQ_VENC 7 +#define IRQ_SERIAL0 8 +#define IRQ_SERIAL1 9 +#define IRQ_EXT_HOST 10 +#define IRQ_DSPHINT 11 +#define IRQ_UART0 12 +#define IRQ_UART1 13 +#define IRQ_USB_DMA 14 +#define IRQ_USB_CORE 15 +#define IRQ_VLYNQ 16 +#define IRQ_MTC0 17 +#define IRQ_MTC1 18 +#define IRQ_SD_MMC 19 +#define IRQ_SDIO_MS 20 +#define IRQ_GIO0 21 +#define IRQ_GIO1 22 +#define IRQ_GIO2 23 +#define IRQ_GIO3 24 +#define IRQ_GIO4 25 +#define IRQ_GIO5 26 +#define IRQ_GIO6 27 +#define IRQ_GIO7 28 +#define IRQ_GIO8 29 +#define IRQ_GIO9 30 +#define IRQ_GIO10 31 +#define IRQ_GIO11 32 +#define IRQ_GIO12 33 +#define IRQ_GIO13 34 +#define IRQ_GIO14 35 +#define IRQ_GIO15 36 +#define IRQ_PREVIEW0 37 +#define IRQ_PREVIEW1 38 +#define IRQ_WATCHDOG 39 +#define IRQ_I2C 40 +#define IRQ_CLKC 41 + +/* Embedded Debugging Interrupts */ +#define IRQ_ICE 42 +#define IRQ_ARMCOM_RX 43 +#define IRQ_ARMCOM_TX 44 + +#define IRQ_RESERVED 45 + +#define NR_IRQS 46 + +#endif diff --git a/firmware/export/timer.h b/firmware/export/timer.h index 920419d1f9..f4df8d51d4 100644 --- a/firmware/export/timer.h +++ b/firmware/export/timer.h @@ -31,7 +31,7 @@ #define TIMER_FREQ (CPU_FREQ/2) #elif CONFIG_CPU == PNX0101 #define TIMER_FREQ 3000000 -#elif CONFIG_CPU == S3C2440 +#elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320 #include "timer-target.h" #elif defined(SIMULATOR) #define TIMER_FREQ 1000000 diff --git a/firmware/sound.c b/firmware/sound.c index dd70b42230..8b68a5569b 100644 --- a/firmware/sound.c +++ b/firmware/sound.c @@ -465,7 +465,7 @@ void sound_set_volume(int value) || defined(HAVE_WM8721) || defined(HAVE_TLV320) || defined(HAVE_WM8751) \ || defined(HAVE_AS3514) current_volume = value * 10; /* tenth of dB */ - set_prescaled_volume(); + set_prescaled_volume(); #elif CONFIG_CPU == PNX0101 int tmp = (60 - value * 4) & 0xff; CODECVOL = tmp | (tmp << 8); diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/crt0.S index e7a0a38f36..56876ca9b1 100644 --- a/firmware/target/arm/crt0.S +++ b/firmware/target/arm/crt0.S @@ -33,9 +33,8 @@ start: msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */ -#ifndef BOOTLOADER - -#ifndef DEBUG +#if !defined(BOOTLOADER) || (CONFIG_CPU == DM320) +#if !defined(DEBUG) /* Copy exception handler code to address 0 */ ldr r2, =_vectorsstart ldr r3, =_vectorsend @@ -52,8 +51,11 @@ start: ldr r0, =fiq_handler str r0, [r1, #28] #endif - -#ifndef STUB +#endif + +#if !defined(BOOTLOADER) + +#if !defined(STUB) /* Zero out IBSS */ ldr r2, =_iedata ldr r3, =_iend @@ -98,6 +100,159 @@ start: /* Code for ARM bootloader targets other than iPod go here */ #if CONFIG_CPU == S3C2440 + /* Proper initialization pulled from 0x5070 */ + + /* BWSCON + * Reserved 0 + * Bank 0: + * Bus width 10 (16 bit) + * Bank 1: + * Buswidth 00 (8 bit) + * Disable wait 0 + * Not using UB/LB 0 + * Bank 2: + * Buswidth 10 (32 bit) + * Disable wait 0 + * Not using UB/LB 0 + * Bank 3: + * Buswidth 10 (32 bit) + * Disable wait 0 + * Use UB/LB 1 + * Bank 4: + * Buswidth 10 (32 bit) + * Disable wait 0 + * Use UB/LB 1 + * Bank 5: + * Buswidth 00 (8 bit) + * Disable wait 0 + * Not using UB/LB 0 + * Bank 6: + * Buswidth 10 (32 bit) + * Disable wait 0 + * Not using UB/LB 0 + * Bank 7: + * Buswidth 00 (8 bit) + * Disable wait 0 + * Not using UB/LB 0 + */ + ldr r2,=0x01055102 + mov r1, #0x48000000 + str r2, [r1] + + /* BANKCON0 + * Pagemode: normal (1 data) 00 + * Pagemode access cycle: 2 clocks 00 + * Address hold: 2 clocks 10 + * Chip selection hold time: 1 clock 10 + * Access cycle: 8 clocks 101 + * Chip select setup time: 1 clock 01 + * Address setup time: 0 clock 00 + */ + ldr r2,=0x00000D60 + str r2, [r1, #4] + + + /* BANKCON1 + * Pagemode: normal (1 data) 00 + * Pagemode access cycle: 2 clocks 00 + * Address hold: 0 clocks 00 + * Chip selection hold time: 0 clock 00 + * Access cycle: 1 clocks 000 + * Chip select setup time: 0 clocks 00 + * Address setup time: 0 clocks 00 + */ + ldr r2,=0x00000000 + str r2, [r1, #8] + + /* BANKCON2 + * Pagemode: normal (1 data) 00 + * Pagemode access cycle: 2 clocks 00 + * Address hold: 2 clocks 10 + * Chip selection hold time: 2 clocks 10 + * Access cycle: 14 clocks 111 + * Chip select setup time: 4 clocks 11 + * Address setup time: 0 clocks 00 + */ + ldr r2,=0x00001FA0 + str r2, [r1, #0xC] + + /* BANKCON3 */ + ldr r2,=0x00001D80 + str r2, [r1, #0x10] + /* BANKCON4 */ + str r2, [r1, #0x14] + + /* BANKCON5 */ + ldr r2,=0x00000000 + str r2, [r1, #0x18] + + /* BANKCON6/7 + * SCAN: 9 bit 01 + * Trcd: 3 clocks 01 + * Tcah: 0 clock 00 + * Tcoh: 0 clock 00 + * Tacc: 1 clock 000 + * Tcos: 0 clock 00 + * Tacs: 0 clock 00 + * MT: Sync DRAM 11 + */ + ldr r2,=0x00018005 + str r2, [r1, #0x1C] + /* BANKCON7 */ + str r2, [r1, #0x20] + + /* REFRESH */ + ldr r2,=0x00980501 + str r2, [r1, #0x24] + + /* BANKSIZE + * BK76MAP: 32M/32M 000 + * Reserved: 0 0 (was 1) + * SCLK_EN: always 1 (was 0) + * SCKE_EN: disable 0 + * Reserved: 0 0 + * BURST_EN: enabled 1 + */ + ldr r2,=0x00000090 + str r2, [r1, #0x28] + + /* MRSRB6 */ + ldr r2,=0x00000030 + str r2, [r1, #0x2C] + /* MRSRB7 */ + str r2, [r1, #0x30] + +#if 0 + /* This next part I am not sure of the purpose */ + + /* GPACON */ + mov r2,#0x01FFFCFF + str r2,=0x56000000 + + /* GPADAT */ + mov r2,#0x01FFFEFF + str r2,=0x56000004 + + /* MRSRB6 */ + mov r2,#0x00000000 + str r2,=0x4800002C + + /* GPADAT */ + ldr r2,=0x01FFFFFF + mov r1, #0x56000000 + str r2, [r1, #4] + + /* MRSRB6 */ + mov r2,#0x00000030 + str r2,=0x4800002C + + /* GPACON */ + mov r2,#0x01FFFFFF + str r2,=0x56000000 + + /* End of the unknown */ +#endif + /* get the high part of our execute address */ ldr r2, =0xffffff00 and r4, pc, r2 @@ -118,6 +273,28 @@ start: start_loc: bl main + +#else + /* get the high part of our execute address */ + ldr r2, =0xffffff00 + and r4, pc, r2 + + /* Copy bootloader to safe area - 0x01900000 */ + mov r5, #0x00900000 + add r5, r5, #0x01000000 + ldr r6, = _dataend + sub r0, r6, r5 /* length of loader */ + add r0, r4, r0 /* r0 points to start of loader */ +1: + cmp r5, r6 + ldrcc r2, [r4], #4 + strcc r2, [r5], #4 + bcc 1b + + ldr pc, =start_loc /* jump to the relocated start_loc: */ + +start_loc: + bl main #endif #else /* BOOTLOADER */ diff --git a/firmware/target/arm/memswap128-arm.S b/firmware/target/arm/memswap128-arm.S index f5276ef353..f672def1ec 100644 --- a/firmware/target/arm/memswap128-arm.S +++ b/firmware/target/arm/memswap128-arm.S @@ -1,44 +1,44 @@ -/***************************************************************************
- * __________ __ ___.
- * Open \______ \ ____ ____ | | _\_ |__ _______ ___
- * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
- * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
- * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
- * \/ \/ \/ \/ \/
- * $Id$
- *
- * Copyright (C) 2007 by Michael Sevakis
- *
- * All files in this archive are subject to the GNU General Public License.
- * See the file COPYING in the source tree root for full license agreement.
- *
- * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
- * KIND, either express or implied.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * void memswap128(void *buf1, void *buf2, size_t len)
- */
- .section .icode, "ax", %progbits
- .align 2
- .global memswap128
- .type memswap128, %function
-memswap128:
- @ r0 = buf1
- @ r1 = buf2
- @ r2 = len
- movs r2, r2, lsr #4 @ bytes => lines, len == 0?
- moveq pc, lr @ not at least a line? leave
- stmdb sp!, { r4-r10, lr } @ save registers and return address
-.loop: @
- ldmia r0, { r3-r6 } @ read four longwords from buf1
- ldmia r1, { r7-r10 } @ read four longwords from buf2
- stmia r0!, { r7-r10 } @ write buf2 data to buf1, buf1 += 16
- stmia r1!, { r3-r6 } @ write buf1 data to buf2, buf2 += 16
- subs r2, r2, #1 @ len -= 1, len > 0 ?
- bhi .loop @ yes? keep exchanging
- ldmia sp!, { r4-r10, pc } @ restore registers and return
-.end:
- .size memswap128, .end-memswap128
-
+/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2007 by Michael Sevakis + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +/**************************************************************************** + * void memswap128(void *buf1, void *buf2, size_t len) + */ + .section .icode, "ax", %progbits + .align 2 + .global memswap128 + .type memswap128, %function +memswap128: + @ r0 = buf1 + @ r1 = buf2 + @ r2 = len + movs r2, r2, lsr #4 @ bytes => lines, len == 0? + moveq pc, lr @ not at least a line? leave + stmdb sp!, { r4-r10, lr } @ save registers and return address +.loop: @ + ldmia r0, { r3-r6 } @ read four longwords from buf1 + ldmia r1, { r7-r10 } @ read four longwords from buf2 + stmia r0!, { r7-r10 } @ write buf2 data to buf1, buf1 += 16 + stmia r1!, { r3-r6 } @ write buf1 data to buf2, buf2 += 16 + subs r2, r2, #1 @ len -= 1, len > 0 ? + bhi .loop @ yes? keep exchanging + ldmia sp!, { r4-r10, pc } @ restore registers and return +.end: + .size memswap128, .end-memswap128 + diff --git a/firmware/target/arm/olympus/mrobe-500/adc-mr500.c b/firmware/target/arm/olympus/mrobe-500/adc-mr500.c new file mode 100644 index 0000000000..4fb2aa3677 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/adc-mr500.c @@ -0,0 +1,46 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "cpu.h" +#include "adc-target.h" +#include "kernel.h" + +/* prototypes */ +static void adc_tick(void); + +void adc_init(void) +{ + /* attach the adc reading to the tick */ + tick_add_task(adc_tick); +} + +/* Called to get the recent ADC reading */ +inline unsigned short adc_read(int channel) +{ + return (short)channel; +} + +/* add this to the tick so that the ADC converts are done in the background */ +static void adc_tick(void) +{ +} + + + + diff --git a/firmware/target/arm/olympus/mrobe-500/adc-target.h b/firmware/target/arm/olympus/mrobe-500/adc-target.h new file mode 100644 index 0000000000..fbf38ee13d --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/adc-target.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#ifndef _ADC_TARGET_H_ +#define _ADC_TARGET_H_ + +/* only two channels used by the Gigabeat */ +#define NUM_ADC_CHANNELS 2 + +#define ADC_BATTERY 0 +#define ADC_HPREMOTE 1 +#define ADC_UNKNOWN_3 2 +#define ADC_UNKNOWN_4 3 +#define ADC_UNKNOWN_5 4 +#define ADC_UNKNOWN_6 5 +#define ADC_UNKNOWN_7 6 +#define ADC_UNKNOWN_8 7 + +#define ADC_UNREG_POWER ADC_BATTERY /* For compatibility */ +#define ADC_READ_ERROR 0xFFFF + +#endif diff --git a/firmware/target/arm/olympus/mrobe-500/ata-mr500.c b/firmware/target/arm/olympus/mrobe-500/ata-mr500.c new file mode 100644 index 0000000000..b4028d5ead --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/ata-mr500.c @@ -0,0 +1,130 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "config.h" +#include "cpu.h" +#include "kernel.h" +#include "thread.h" +#include "system.h" +#include "power.h" +#include "panic.h" +#include "pcf50606.h" +#include "ata-target.h" +#include "backlight-target.h" + +/* ARESET on C7C68300 and RESET on ATA interface (Active Low) */ +#define ATA_RESET_ENABLE return +#define ATA_RESET_DISABLE return + +/* ATA_EN on C7C68300 */ +#define USB_ATA_ENABLE return +#define USB_ATA_DISABLE return + +void ata_reset(void) +{ + ATA_RESET_ENABLE; + sleep(1); /* > 25us */ + ATA_RESET_DISABLE; + sleep(1); /* > 2ms */ +} + +/* This function is called before enabling the USB bus */ +void ata_enable(bool on) +{ + if(on) + USB_ATA_DISABLE; + else + USB_ATA_ENABLE; +} + +bool ata_is_coldstart(void) +{ + return false; +} + +void ata_device_init(void) +{ + /* ATA reset */ + ATA_RESET_DISABLE; /* Set the pin to disable an active low reset */ +} + +#if !defined(BOOTLOADER) +void copy_read_sectors(unsigned char* buf, int wordcount) +{ + __buttonlight_trigger(); + + /* Unaligned transfer - slow copy */ + if ( (unsigned long)buf & 1) + { /* not 16-bit aligned, copy byte by byte */ + unsigned short tmp = 0; + unsigned char* bufend = buf + wordcount*2; + do + { + tmp = ATA_DATA; + *buf++ = tmp & 0xff; /* I assume big endian */ + *buf++ = tmp >> 8; /* and don't use the SWAB16 macro */ + } while (buf < bufend); /* tail loop is faster */ + return; + } + /* This should never happen, but worth watching for */ + if(wordcount > (1 << 18)) + panicf("atd-meg-fx.c: copy_read_sectors: too many sectors per read!"); + +//#define GIGABEAT_DEBUG_ATA +#ifdef GIGABEAT_DEBUG_ATA + static int line = 0; + static char str[256]; + snprintf(str, sizeof(str), "ODD DMA to %08x, %d", buf, wordcount); + lcd_puts(10, line, str); + line = (line+1) % 32; + lcd_update(); +#endif + /* Reset the channel */ + DMASKTRIG0 |= 4; + /* Wait for DMA controller to be ready */ + while(DMASKTRIG0 & 0x2) + ; + while(DSTAT0 & (1 << 20)) + ; + /* Source is ATA_DATA, on AHB Bus, Fixed */ + DISRC0 = (int) 0x18000000; + DISRCC0 = 0x1; + /* Dest mapped to physical address, on AHB bus, increment */ + DIDST0 = (int) buf; + if(DIDST0 < 0x30000000) + DIDST0 += 0x30000000; + DIDSTC0 = 0; + + /* DACK/DREQ Sync to AHB, Whole service, No reload, 16-bit transfers */ + DCON0 = ((1 << 30) | (1<<27) | (1<<22) | (1<<20)) | wordcount; + + /* Activate the channel */ + DMASKTRIG0 = 0x2; + + invalidate_dcache_range((void *)buf, wordcount*2); + + /* Start DMA */ + DMASKTRIG0 |= 0x1; + + /* Wait for transfer to complete */ + while((DSTAT0 & 0x000fffff)) + priority_yield(); + /* Dump cache for the buffer */ +} +#endif diff --git a/firmware/target/arm/olympus/mrobe-500/ata-target.h b/firmware/target/arm/olympus/mrobe-500/ata-target.h new file mode 100644 index 0000000000..87d8a9b535 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/ata-target.h @@ -0,0 +1,71 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#ifndef ATA_TARGET_H +#define ATA_TARGET_H + +/* Plain C read & write loops */ +#define PREFER_C_READING +#define PREFER_C_WRITING +#if !defined(BOOTLOADER) +//#define ATA_OPTIMIZED_READING +//void copy_read_sectors(unsigned char* buf, int wordcount); +#endif + +#define ATA_IOBASE 0x50000000 +#define ATA_DATA (*((volatile unsigned short*)(ATA_IOBASE+0xa0))) +#define ATA_ERROR (*((volatile unsigned char*)(ATA_IOBASE + 0xa2))) +#define ATA_NSECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0x24))) +#define ATA_SECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0x26))) +#define ATA_LCYL (*((volatile unsigned char*)(ATA_IOBASE + 0x28))) +#define ATA_HCYL (*((volatile unsigned char*)(ATA_IOBASE + 0x2A))) +#define ATA_SELECT (*((volatile unsigned char*)(ATA_IOBASE + 0x2C))) +#define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0x2E))) +#define ATA_CONTROL (*((volatile unsigned char*)(ATA_IOBASE + 0x9C))) + +#define STATUS_BSY 0x80 +#define STATUS_RDY 0x40 +#define STATUS_DF 0x20 +#define STATUS_DRQ 0x08 +#define STATUS_ERR 0x01 +#define ERROR_ABRT 0x04 + +#define WRITE_PATTERN1 0xa5 +#define WRITE_PATTERN2 0x5a +#define WRITE_PATTERN3 0xaa +#define WRITE_PATTERN4 0x55 + +#define READ_PATTERN1 0xa5 +#define READ_PATTERN2 0x5a +#define READ_PATTERN3 0xaa +#define READ_PATTERN4 0x55 + +#define READ_PATTERN1_MASK 0xff +#define READ_PATTERN2_MASK 0xff +#define READ_PATTERN3_MASK 0xff +#define READ_PATTERN4_MASK 0xff + +#define SET_REG(reg,val) reg = (val) +#define SET_16BITREG(reg,val) reg = (val) + +void ata_reset(void); +void ata_device_init(void); +bool ata_is_coldstart(void); + +#endif diff --git a/firmware/target/arm/olympus/mrobe-500/backlight-mr500.c b/firmware/target/arm/olympus/mrobe-500/backlight-mr500.c new file mode 100644 index 0000000000..6a335d357c --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/backlight-mr500.c @@ -0,0 +1,50 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "config.h" +#include "cpu.h" +#include "system.h" +#include "backlight-target.h" +#include "backlight.h" +#include "lcd.h" +#include "power.h" + +void __backlight_on(void) +{ +} + +void __backlight_off(void) +{ +} + +/* Assumes that the backlight has been initialized */ +void __backlight_set_brightness(int brightness) +{ + (void) brightness; +} + +void __backlight_dim(bool dim_now) +{ + (void) dim_now; +} + +bool __backlight_init(void) +{ + return true; +} diff --git a/firmware/target/arm/olympus/mrobe-500/backlight-target.h b/firmware/target/arm/olympus/mrobe-500/backlight-target.h new file mode 100644 index 0000000000..d28cfbbdf1 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/backlight-target.h @@ -0,0 +1,31 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#ifndef BACKLIGHT_TARGET_H +#define BACKLIGHT_TARGET_H + +bool __backlight_init(void); +void __backlight_on(void); +void __backlight_off(void); +void __backlight_set_brightness(int brightness); + +/* true: backlight fades off - false: backlight fades on */ +void __backlight_dim(bool dim); + +#endif diff --git a/firmware/target/arm/olympus/mrobe-500/button-mr500.c b/firmware/target/arm/olympus/mrobe-500/button-mr500.c new file mode 100644 index 0000000000..9cafab5c14 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/button-mr500.c @@ -0,0 +1,56 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "config.h" +#include "cpu.h" +#include "system.h" +#include "button.h" +#include "kernel.h" +#include "backlight.h" +#include "adc.h" +#include "system.h" +#include "backlight-target.h" + +static int const remote_buttons[] = +{ + BUTTON_NONE, /* Headphones connected - remote disconnected */ + BUTTON_RC_PLAY, + BUTTON_RC_DSP, + BUTTON_RC_REW, + BUTTON_RC_FF, + BUTTON_RC_VOL_UP, + BUTTON_RC_VOL_DOWN, + BUTTON_NONE, /* Remote control attached - no buttons pressed */ + BUTTON_NONE, /* Nothing in the headphone socket */ +}; + +void button_init_device(void) +{ + /* Power, Remote Play & Hold switch */ +} + +inline bool button_hold(void) +{ + return false; +} + +int button_read_device(void) +{ + return 0; +} diff --git a/firmware/target/arm/olympus/mrobe-500/button-target.h b/firmware/target/arm/olympus/mrobe-500/button-target.h new file mode 100644 index 0000000000..6637c5bf2b --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/button-target.h @@ -0,0 +1,99 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#ifndef _BUTTON_TARGET_H_ +#define _BUTTON_TARGET_H_ + +#include <stdbool.h> +#include "config.h" + +#define HAS_BUTTON_HOLD + +bool button_hold(void); +void button_init_device(void); +int button_read_device(void); + +/* Toshiba Gigabeat specific button codes */ + +#define BUTTON_POWER 0x00000001 +#define BUTTON_MENU 0x00000002 + +#define BUTTON_LEFT 0x00000004 +#define BUTTON_RIGHT 0x00000008 +#define BUTTON_UP 0x00000010 +#define BUTTON_DOWN 0x00000020 + +#define BUTTON_VOL_UP 0x00000040 +#define BUTTON_VOL_DOWN 0x00000080 + +#define BUTTON_SELECT 0x00000100 +#define BUTTON_A 0x00000200 + +/* Remote control buttons */ + +#define BUTTON_RC_VOL_UP 0x00000400 +#define BUTTON_RC_VOL_DOWN 0x00000800 +#define BUTTON_RC_FF 0x00001000 +#define BUTTON_RC_REW 0x00002000 + +#define BUTTON_RC_PLAY 0x00004000 +#define BUTTON_RC_DSP 0x00008000 + +/* Toshiba Gigabeat specific remote button ADC values */ +/* The remote control uses ADC 1 to emulate button pushes + Reading (approx) Button HP plugged in? Remote plugged in? + 0 N/A Yes No + 125 Play/Pause Cant tell Yes + 241 Speaker+ Cant tell Yes + 369 Rewind Cant tell Yes + 492 Fast Fwd Cant tell Yes + 616 Vol + Cant tell Yes + 742 Vol - Cant tell Yes + 864 None Cant tell Yes + 1023 N/A No No +*/ + +/* + Notes: + + Buttons on the remote are translated into equivalent button presses just + as if you were pressing them on the Gigabeat itself. + + We cannot tell if the hold is asserted on the remote. The Hold function on + the remote is to block the output of the buttons changing. + + Only one button can be sensed at a time. If another is pressed, the button + with the lowest reading is dominant. So, if Rewind and Vol + are pressed + at the same time, Rewind value is the one that is read. +*/ + + + + +#define BUTTON_MAIN (BUTTON_POWER|BUTTON_MENU|BUTTON_LEFT|BUTTON_RIGHT\ + |BUTTON_UP|BUTTON_DOWN|BUTTON_VOL_UP|BUTTON_VOL_DOWN\ + |BUTTON_SELECT|BUTTON_A) + +#define BUTTON_REMOTE (BUTTON_RC_VOL_UP|BUTTON_RC_VOL_DOWN|BUTTON_RC_FF\ + |BUTTON_RC_REW|BUTTON_RC_PLAY|BUTTON_RC_DSP) + +#define POWEROFF_BUTTON BUTTON_POWER +#define POWEROFF_COUNT 10 + +#endif /* _BUTTON_TARGET_H_ */ diff --git a/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c b/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c new file mode 100644 index 0000000000..27bb0475e4 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c @@ -0,0 +1,48 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "config.h" +#include "system.h" +#include "kernel.h" +#include "timer.h" +#include "thread.h" + +extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void); + +void tick_start(unsigned int interval_in_ms) +{ + (void)interval_in_ms; +} + +void TIMER4(void) +{ + int i; + + /* Run through the list of tick tasks */ + for(i = 0; i < MAX_NUM_TICK_TASKS; i++) + { + if(tick_funcs[i]) + { + tick_funcs[i](); + } + } + + current_tick++; + +} diff --git a/firmware/target/arm/olympus/mrobe-500/lcd-mr500.c b/firmware/target/arm/olympus/mrobe-500/lcd-mr500.c new file mode 100644 index 0000000000..5e41b829e1 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/lcd-mr500.c @@ -0,0 +1,206 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * Some of this is based on the Cowon A2 Firmware release: + * http://www.cowonglobal.com/download/gnu/cowon_pmp_a2_src_1.59_GPL.tar.gz + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "config.h" +#include "cpu.h" +#include "string.h" +#include "lcd.h" +#include "kernel.h" +#include "memory.h" +#include "system-target.h" + +static volatile bool lcd_on = true; +volatile bool lcd_poweroff = false; +/* +** These are imported from lcd-16bit.c +*/ +extern unsigned fg_pattern; +extern unsigned bg_pattern; + +bool lcd_enabled(void) +{ + return lcd_on; +} + +/* LCD init - based on code from ingenient-bsp/bootloader/board/dm320/splash.c + * and code by Catalin Patulea from the M:Robe 500i linux port + */ +void lcd_init_device(void) +{ + unsigned int addr; + + /* Clear the Frame */ + memset16(FRAME, 0x0000, LCD_WIDTH*LCD_HEIGHT); + + outw(0x00ff, IO_OSD_MODE); + outw(0x0002, IO_OSD_VIDWINMD); + outw(0x2001, IO_OSD_OSDWINMD0); + outw(0x0002, IO_OSD_OSDWINMD1); + outw(0x0000, IO_OSD_ATRMD); + outw(0x0000, IO_OSD_RECTCUR); + + outw((480*2) / 32, IO_OSD_OSDWIN0OFST); + addr = ((int)FRAME-CONFIG_SDRAM_START) / 32; + outw(addr >> 16, IO_OSD_OSDWINADH); + outw(addr & 0xFFFF, IO_OSD_OSDWIN0ADL); + + outw(80, IO_OSD_BASEPX); + outw(2, IO_OSD_BASEPY); + + outw(0, IO_OSD_OSDWIN0XP); + outw(0, IO_OSD_OSDWIN0YP); + outw(480, IO_OSD_OSDWIN0XL); + outw(640, IO_OSD_OSDWIN0YL); +} + +/* Update a fraction of the display. */ +void lcd_update_rect(int x, int y, int width, int height) +{ + fb_data *dst, *src; + + if (!lcd_on) + return; + + if (x + width > LCD_WIDTH) + width = LCD_WIDTH - x; /* Clip right */ + if (x < 0) + width += x, x = 0; /* Clip left */ + if (width <= 0) + return; /* nothing left to do */ + + if (y + height > LCD_HEIGHT) + height = LCD_HEIGHT - y; /* Clip bottom */ + if (y < 0) + height += y, y = 0; /* Clip top */ + if (height <= 0) + return; /* nothing left to do */ + + dst = (fb_data *)FRAME + LCD_WIDTH*y + x; + src = &lcd_framebuffer[y][x]; + + /* Copy part of the Rockbox framebuffer to the second framebuffer */ + if (width < LCD_WIDTH) + { + int y; + /* Not full width - do line-by-line */ + for(y=0;y<height;y++) + { + memcpy(dst, src, width*sizeof(fb_data)); + dst+=LCD_WIDTH; + src+=LCD_WIDTH; + } + } + else + { + /* Full width - copy as one line */ + memcpy(dst, src, LCD_WIDTH*height*sizeof(fb_data)); + } +} + +void lcd_enable(bool state) +{ + (void)state; +} + +/* Update the display. + This must be called after all other LCD functions that change the display. */ +void lcd_update(void) +{ + if (!lcd_on) + return; + + memcpy((fb_data *)FRAME, &lcd_framebuffer[0][0], + LCD_WIDTH*LCD_HEIGHT*sizeof(fb_data)); +} + +/* Line write helper function for lcd_yuv_blit. Write two lines of yuv420. */ +extern void lcd_write_yuv420_lines(fb_data *dst, + unsigned char chroma_buf[LCD_HEIGHT/2*3], + unsigned char const * const src[3], + int width, + int stride); +/* Performance function to blit a YUV bitmap directly to the LCD */ +/* For the Gigabeat - show it rotated */ +/* So the LCD_WIDTH is now the height */ +void lcd_yuv_blit(unsigned char * const src[3], + int src_x, int src_y, int stride, + int x, int y, int width, int height) +{ + /* Caches for chroma data so it only need be recaculated every other + line */ + unsigned char chroma_buf[LCD_HEIGHT/2*3]; /* 480 bytes */ + unsigned char const * yuv_src[3]; + off_t z; + + if (!lcd_on) + return; + + /* Sorry, but width and height must be >= 2 or else */ + width &= ~1; + height >>= 1; + + fb_data *dst = (fb_data*)FRAME + x * LCD_WIDTH + (LCD_WIDTH - y) - 1; + + z = stride*src_y; + yuv_src[0] = src[0] + z + src_x; + yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1); + yuv_src[2] = src[2] + (yuv_src[1] - src[1]); + + do + { + lcd_write_yuv420_lines(dst, chroma_buf, yuv_src, width, + stride); + yuv_src[0] += stride << 1; /* Skip down two luma lines */ + yuv_src[1] += stride >> 1; /* Skip down one chroma line */ + yuv_src[2] += stride >> 1; + dst -= 2; + } + while (--height > 0); +} + +void lcd_set_contrast(int val) { + (void) val; + // TODO: +} + +void lcd_set_invert_display(bool yesno) { + (void) yesno; + // TODO: +} + +void lcd_blit(const fb_data* data, int bx, int y, int bwidth, + int height, int stride) +{ + (void) data; + (void) bx; + (void) y; + (void) bwidth; + (void) height; + (void) stride; + //TODO: +} + +void lcd_set_flip(bool yesno) { + (void) yesno; + // TODO: +} + diff --git a/firmware/target/arm/olympus/mrobe-500/lcd-target.h b/firmware/target/arm/olympus/mrobe-500/lcd-target.h new file mode 100644 index 0000000000..bac1bef237 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/lcd-target.h @@ -0,0 +1,21 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +extern void lcd_enable(bool state); + diff --git a/firmware/target/arm/olympus/mrobe-500/power-mr500.c b/firmware/target/arm/olympus/mrobe-500/power-mr500.c new file mode 100644 index 0000000000..28fe6a297a --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/power-mr500.c @@ -0,0 +1,93 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "config.h" +#include "cpu.h" +#include <stdbool.h> +#include "kernel.h" +#include "system.h" +#include "power.h" +#include "pcf50606.h" +#include "backlight.h" +#include "backlight-target.h" + +#ifndef SIMULATOR + +void power_init(void) +{ + /* Initialize IDE power pin */ + ide_power_enable(true); + /* Charger detect */ +} + +bool charger_inserted(void) +{ + return false; +} + +/* Returns true if the unit is charging the batteries. */ +bool charging_state(void) { + return false; +} + +void ide_power_enable(bool on) +{ + if (on) + return; + else + return; +} + +bool ide_powered(void) +{ + return true; +} + +void power_off(void) +{ + /* turn off backlight and wait for 1 second */ + __backlight_off(); + sleep(HZ); + /* set SLEEP bit to on in CLKCON to turn off */ +// CLKCON |=(1<<3); +} + +#else /* SIMULATOR */ + +bool charger_inserted(void) +{ + return false; +} + +void charger_enable(bool on) +{ + (void)on; +} + +void power_off(void) +{ +} + +void ide_power_enable(bool on) +{ + (void)on; +} + +#endif /* SIMULATOR */ + diff --git a/firmware/target/arm/olympus/mrobe-500/system-mr500.c b/firmware/target/arm/olympus/mrobe-500/system-mr500.c new file mode 100644 index 0000000000..c93c9f6260 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/system-mr500.c @@ -0,0 +1,181 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "kernel.h" +#include "system.h" +#include "panic.h" + +#define default_interrupt(name) \ + extern __attribute__((weak,alias("UIRQ"))) void name (void) + +default_interrupt(TIMER0); +default_interrupt(TIMER1); +default_interrupt(TIMER2); +default_interrupt(TIMER3); +default_interrupt(CCD_VD0); +default_interrupt(CCD_VD1); +default_interrupt(CCD_WEN); +default_interrupt(VENC); +default_interrupt(SERIAL0); +default_interrupt(SERIAL1); +default_interrupt(EXT_HOST); +default_interrupt(DSPHINT); +default_interrupt(UART0); +default_interrupt(UART1); +default_interrupt(USB_DMA); +default_interrupt(USB_CORE); +default_interrupt(VLYNQ); +default_interrupt(MTC0); +default_interrupt(MTC1); +default_interrupt(SD_MMC); +default_interrupt(SDIO_MS); +default_interrupt(GIO0); +default_interrupt(GIO1); +default_interrupt(GIO2); +default_interrupt(GIO3); +default_interrupt(GIO4); +default_interrupt(GIO5); +default_interrupt(GIO6); +default_interrupt(GIO7); +default_interrupt(GIO8); +default_interrupt(GIO9); +default_interrupt(GIO10); +default_interrupt(GIO11); +default_interrupt(GIO12); +default_interrupt(GIO13); +default_interrupt(GIO14); +default_interrupt(GIO15); +default_interrupt(PREVIEW0); +default_interrupt(PREVIEW1); +default_interrupt(WATCHDOG); +default_interrupt(I2C); +default_interrupt(CLKC); +default_interrupt(ICE); +default_interrupt(ARMCOM_RX); +default_interrupt(ARMCOM_TX); +default_interrupt(RESERVED); + +static void (* const irqvector[])(void) = +{ + TIMER0,TIMER1,TIMER2,TIMER3,CCD_VD0,CCD_VD1, + CCD_WEN,VENC,SERIAL0,SERIAL1,EXT_HOST,DSPHINT, + UART0,UART1,USB_DMA,USB_CORE,VLYNQ,MTC0,MTC1, + SD_MMC,SDIO_MS,GIO0,GIO1,GIO2,GIO3,GIO4,GIO5, + GIO6,GIO7,GIO8,GIO9,GIO10,GIO11,GIO12,GIO13, + GIO14,GIO15,PREVIEW0,PREVIEW1,WATCHDOG,I2C,CLKC, + ICE,ARMCOM_RX,ARMCOM_TX,RESERVED +}; + +static const char * const irqname[] = +{ + "TIMER0","TIMER1","TIMER2","TIMER3","CCD_VD0","CCD_VD1", + "CCD_WEN","VENC","SERIAL0","SERIAL1","EXT_HOST","DSPHINT", + "UART0","UART1","USB_DMA","USB_CORE","VLYNQ","MTC0","MTC1", + "SD_MMC","SDIO_MS","GIO0","GIO1","GIO2","GIO3","GIO4","GIO5", + "GIO6","GIO7","GIO8","GIO9","GIO10","GIO11","GIO12","GIO13", + "GIO14","GIO15","PREVIEW0","PREVIEW1","WATCHDOG","I2C","CLKC", + "ICE","ARMCOM_RX","ARMCOM_TX","RESERVED" +}; + +static void UIRQ(void) +{ + unsigned int offset = inw(IO_INTC_IRQENTRY0); + panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]); +} + +void irq_handler(void) __attribute__((interrupt ("IRQ"), naked)); +void irq_handler(void) +{ + /* + * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c + */ + + asm volatile ( + "sub lr, lr, #4 \r\n" + "stmfd sp!, {r0-r3, ip, lr} \r\n" + "mov r0, #0x00030000 \r\n" + "ldr r0, [r0, #0x518] \r\n" + "ldr r1, =irqvector \r\n" + "ldr r1, [r1, r0, lsl #2] \r\n" + "mov lr, pc \r\n" + "bx r1 \r\n" + "ldmfd sp!, {r0-r3, ip, pc}^ \r\n" + ); +} + +void system_reboot(void) +{ + +} + +void system_init(void) +{ + /* taken from linux/arch/arm/mach-itdm320-20/irq.c */ + + /* Clearing all FIQs and IRQs. */ + outw(0xFFFF, IO_INTC_IRQ0); + outw(0xFFFF, IO_INTC_IRQ1); + outw(0xFFFF, IO_INTC_IRQ2); + + outw(0xFFFF, IO_INTC_FIQ0); + outw(0xFFFF, IO_INTC_FIQ1); + outw(0xFFFF, IO_INTC_FIQ2); + + /* Masking all Interrupts. */ + outw(0, IO_INTC_EINT0); + outw(0, IO_INTC_EINT1); + outw(0, IO_INTC_EINT2); + + /* Setting INTC to all IRQs. */ + outw(0, IO_INTC_FISEL0); + outw(0, IO_INTC_FISEL1); + outw(0, IO_INTC_FISEL2); +} + +int system_memory_guard(int newmode) +{ + (void)newmode; + return 0; +} + +#ifdef HAVE_ADJUSTABLE_CPU_FREQ + +void set_cpu_frequency(long frequency) +{ + if (frequency == CPUFREQ_MAX) + { + asm volatile("mov r0, #0\n" + "mrc p15, 0, r0, c1, c0, 0\n" + "orr r0, r0, #3<<30\n" /* set to Asynchronous mode*/ + "mcr p15, 0, r0, c1, c0, 0" : : : "r0"); + + FREQ = CPUFREQ_MAX; + } + else + { + asm volatile("mov r0, #0\n" + "mrc p15, 0, r0, c1, c0, 0\n" + "bic r0, r0, #3<<30\n" /* set to FastBus mode*/ + "mcr p15, 0, r0, c1, c0, 0" : : : "r0"); + + FREQ = CPUFREQ_NORMAL; + } +} + +#endif diff --git a/firmware/target/arm/olympus/mrobe-500/timer-mr500.c b/firmware/target/arm/olympus/mrobe-500/timer-mr500.c new file mode 100644 index 0000000000..cd3cec5663 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/timer-mr500.c @@ -0,0 +1,108 @@ +/*************************************************************************** +* __________ __ ___. +* Open \______ \ ____ ____ | | _\_ |__ _______ ___ +* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / +* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < +* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ +* \/ \/ \/ \/ \/ +* $Id: $ +* +* Copyright (C) 2007 by Karl Kurbjun +* +* All files in this archive are subject to the GNU General Public License. +* See the file COPYING in the source tree root for full license agreement. +* +* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY +* KIND, either express or implied. +* +****************************************************************************/ + +#include "config.h" +#include "cpu.h" +#include "system.h" +#include "timer.h" +#include "logf.h" + +/* GPB0/TOUT0 should already have been configured as output so that pin + should not be a functional pin and TIMER0 output unseen there */ +void TIMER0(void) +{ + if (pfn_timer != NULL) + pfn_timer(); +} + +static void stop_timer(void) +{ +} + +bool __timer_set(long cycles, bool start) +{ + /* taken from linux/arch/arm/mach-itdm320-20/time.c and timer-meg-fx.c */ + + /* Turn off all timers */ +/* outw(CONFIG_TIMER0_TMMD_STOP, IO_TIMER0_TMMD); + outw(CONFIG_TIMER1_TMMD_STOP, IO_TIMER1_TMMD); + outw(CONFIG_TIMER2_TMMD_STOP, IO_TIMER2_TMMD); + outw(CONFIG_TIMER3_TMMD_STOP, IO_TIMER3_TMMD); + */ + /* Turn Timer0 to Free Run mode */ +// outw(CONFIG_TIMER0_TMMD_FREE_RUN, IO_TIMER0_TMMD); + + bool retval = false; + + /* Find the minimum factor that puts the counter in range 1-65535 */ + unsigned int prescaler = (cycles + 65534) / 65535; + + /* Test this by writing 1's to registers to see how many bits we have */ + /* Maximum divider setting is x / 1024 / 65536 = x / 67108864 */ + { + int oldlevel; + unsigned int divider; + + if (start && pfn_unregister != NULL) + { + pfn_unregister(); + pfn_unregister = NULL; + } + + oldlevel = set_irq_level(HIGHEST_IRQ_LEVEL); + + /* Max prescale is 1023+1 */ + for (divider = 0; prescaler > 1024; prescaler >>= 1, divider++); + + /* Setup the Prescalar */ + outw(prescaler, IO_TIMER0_TMPRSCL); + + /* Setup the Divisor */ + outw(divider, IO_TIMER0_TMDIV); + + set_irq_level(oldlevel); + + retval = true; + } + + return retval; +} + +bool __timer_register(void) +{ + bool retval = true; + + int oldstatus = set_interrupt_status(IRQ_FIQ_DISABLED, IRQ_FIQ_STATUS); + + stop_timer(); + + /* Turn Timer0 to Free Run mode */ + outw(0x0002, IO_TIMER0_TMMD); + + set_interrupt_status(oldstatus, IRQ_FIQ_STATUS); + + return retval; +} + +void __timer_unregister(void) +{ + int oldstatus = set_interrupt_status(IRQ_FIQ_DISABLED, IRQ_FIQ_STATUS); + stop_timer(); + set_interrupt_status(oldstatus, IRQ_FIQ_STATUS); +} diff --git a/firmware/target/arm/olympus/mrobe-500/timer-target.h b/firmware/target/arm/olympus/mrobe-500/timer-target.h new file mode 100644 index 0000000000..320b35d5d3 --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/timer-target.h @@ -0,0 +1,39 @@ +/*************************************************************************** +* __________ __ ___. +* Open \______ \ ____ ____ | | _\_ |__ _______ ___ +* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / +* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < +* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ +* \/ \/ \/ \/ \/ +* $Id: $ +* +* Copyright (C) 2007 by Karl Kurbjun +* +* All files in this archive are subject to the GNU General Public License. +* See the file COPYING in the source tree root for full license agreement. +* +* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY +* KIND, either express or implied. +* +****************************************************************************/ +#ifndef TIMER_TARGET_H +#define TIMER_TARGET_H + +/* timer is based on PCLK and minimum division is 2 */ +#define TIMER_FREQ (49156800/2) + +bool __timer_set(long cycles, bool set); +bool __timer_register(void); +void __timer_unregister(void); + +#define __TIMER_SET(cycles, set) \ + __timer_set(cycles, set) + +#define __TIMER_REGISTER(reg_prio, unregister_callback, cycles, \ + int_prio, timer_callback) \ + __timer_register() + +#define __TIMER_UNREGISTER(...) \ + __timer_unregister() + +#endif /* TIMER_TARGET_H */ diff --git a/firmware/target/arm/olympus/mrobe-500/usb-mr500.c b/firmware/target/arm/olympus/mrobe-500/usb-mr500.c new file mode 100644 index 0000000000..e8d0e39c2e --- /dev/null +++ b/firmware/target/arm/olympus/mrobe-500/usb-mr500.c @@ -0,0 +1,55 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id: $ + * + * Copyright (C) 2007 by Karl Kurbjun + * + * All files in this archive are subject to the GNU General Public License. + * See the file COPYING in the source tree root for full license agreement. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +#include "config.h" +#include "cpu.h" +#include "system.h" +#include "kernel.h" +#include "ata.h" + +#define USB_RST_ASSERT +#define USB_RST_DEASSERT + +#define USB_VPLUS_PWR_ASSERT +#define USB_VPLUS_PWR_DEASSERT + +#define USB_UNIT_IS_PRESENT false + +/* The usb detect is one pin to the cpu active low */ +inline bool usb_detect(void) +{ + return USB_UNIT_IS_PRESENT; +} + +void usb_init_device(void) +{ +// ata_enable(true); +} + +void usb_enable(bool on) +{ + if (on) + { + USB_VPLUS_PWR_ASSERT; + } + else + { + USB_VPLUS_PWR_DEASSERT; + } +} diff --git a/firmware/target/arm/system-arm.h b/firmware/target/arm/system-arm.h index 1a9cccc711..aeb90df399 100644 --- a/firmware/target/arm/system-arm.h +++ b/firmware/target/arm/system-arm.h @@ -22,6 +22,15 @@ #define nop \ asm volatile ("nop") +//#define outw(v,a) *(volatile unsigned short *)(a+PHY_IO_BASE) = (v) +#ifndef outw +#define outw(v,p) (*((unsigned short*)(p + PHY_IO_BASE)) = v) +#endif + +#ifndef inw +#define inw(p) (*((unsigned short*)(p + PHY_IO_BASE))) +#endif + /* This gets too complicated otherwise with all the ARM variation and would have conflicts with another system-target.h elsewhere so include a subheader from here. */ diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 522e73123a..5cfd02840c 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h @@ -22,6 +22,7 @@ #include "system-arm.h" +#if (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) /* TODO: This header is actually portalplayer specific, and should be * moved into an appropriate subdir (or even split in 2). */ @@ -90,5 +91,6 @@ static inline void flush_icache(void) } #endif /* CONFIG_CPU */ +#endif #endif /* SYSTEM_TARGET_H */ diff --git a/firmware/thread.c b/firmware/thread.c index a4981af256..86b90f4f0d 100644 --- a/firmware/thread.c +++ b/firmware/thread.c @@ -105,7 +105,7 @@ static void remove_from_list(struct thread_entry **list, struct thread_entry *thread) ICODE_ATTR; */ -void switch_thread(bool save_context, struct thread_entry **blocked_list) +void switch_thread(bool save_context, struct thread_entry **blocked_list) ICODE_ATTR; static inline void store_context(void* addr) __attribute__ ((always_inline)); @@ -196,6 +196,11 @@ static inline void core_sleep(void) for(i=0; i<10; i++); /* wait for IDLE */ CLKCON &= ~(1 << 2); /* reset IDLE bit when wake up */ } +#else +static inline void core_sleep(void) +{ + +} #endif #elif defined(CPU_COLDFIRE) diff --git a/firmware/timer.c b/firmware/timer.c index 1ac16b697a..b86d4493a3 100644 --- a/firmware/timer.c +++ b/firmware/timer.c @@ -208,7 +208,7 @@ static bool timer_set(long cycles, bool start) cycles_new = cycles; return true; -#elif CONFIG_CPU == S3C2440 +#else return __TIMER_SET(cycles, start); #endif /* CONFIG_CPU */ } @@ -268,7 +268,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR); irq_enable_int(IRQ_TIMER1); return true; -#elif CONFIG_CPU == S3C2440 +#else return __TIMER_REGISTER(reg_prio, unregister_callback, cycles, int_prio, timer_callback); #endif diff --git a/tools/configure b/tools/configure index 61c2618a98..a928e3060c 100755 --- a/tools/configure +++ b/tools/configure @@ -618,8 +618,8 @@ cat <<EOF 31) M5/M5L 51) Sansa e200R 52) Sansa c200 - ==Tatung== - 60) Elio TPJ-1022 + ==Tatung== ==Olympus== + 60) Elio TPJ-1022 70) M:Robe 500 EOF buildfor=`input`; @@ -1257,6 +1257,30 @@ EOF t_model="gigabeat-fx" ;; + 70|mrobe500) + target_id=20 + archos="mrobe500" + target="-DMROBE_500" + memory=64 # always + arm9tdmicc + tool="$rootdir/tools/scramble -add=giga" + bmp2rb_mono="$rootdir/tools/bmp2rb -f 0" + bmp2rb_native="$rootdir/tools/bmp2rb -f 4" + output="rockbox.mrobe500" + appextra="recorder:gui" + archosrom="" + flash="" + plugins="no" + swcodec="yes" + toolset=$gigabeatbitmaptools + boottool="cp " + bootoutput="rockbox.mrboot" + # architecture, manufacturer and model for the target-tree build + t_cpu="arm" + t_manufacturer="olympus" + t_model="mrobe-500" + ;; + 50|e200) target_id=23 archos="e200" |