diff options
authorAidan MacDonald <>2021-03-03 23:48:49 +0000
committerAidan MacDonald <>2021-03-03 23:57:08 +0000
commit8cb4c18310f3975adfa318154b1b9c317fcdbfab (patch)
parentcde5ae755fde5b645ab287a91c613f803a88d79d (diff)
Really fix the MIPS cache bug this time
In fixing the original bug I tried to optimize discard_dcache_range() to minimize writeback and inadvertently introduced a second bug, which typically ends in a TLB refill panic. It occurs only if the range fits within one cache line, and when both the start and end of the range are not aligned to a cache line. This causes ptr to be incremented and end to be decremented, so ptr > end, and the loop can't terminate. Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c
index f4ffbfa6ee..46094bf6b6 100644
--- a/firmware/target/mips/mmu-mips.c
+++ b/firmware/target/mips/mmu-mips.c
@@ -235,7 +235,7 @@ void discard_dcache_range(const void *base, unsigned int size)
/* Interior of region is safe to discard */
- for(; ptr != end; ptr += CACHEALIGN_SIZE)
+ for(; ptr <= end; ptr += CACHEALIGN_SIZE)
__CACHE_OP(DCHitInv, ptr);