diff options
| author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-30 21:24:36 -0400 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-30 21:36:26 -0400 |
| commit | 8dadce5c4cc9564cfeb49f42ec83fd1727c9ccdb (patch) | |
| tree | 613042111cd214bb267a6d9cec0f81b0c0830ea9 | |
| parent | 06e9abc428fc5add36bebf9fed8a5a6353e41b21 (diff) | |
| download | rockbox-8dadce5.tar.gz rockbox-8dadce5.zip | |
jz4760: Explicitly disable UARTs at startup
(Bootloader uses UART1, and leaves it running when it hands it off to us)
Change-Id: Icde1d713574582f18e9f91b5c95f3917fe324b74
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/debug-jz4760.c | 12 | ||||
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 12 | ||||
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-target.h | 2 |
3 files changed, 24 insertions, 2 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c b/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c index ee247a9cff..3634a88f11 100644 --- a/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c @@ -138,6 +138,8 @@ bool dbg_ports(void) return false; } +extern uint32_t irqstackend,irqstackbegin; + bool dbg_hw_info(void) { int btn = 0; @@ -151,6 +153,12 @@ bool dbg_hw_info(void) { lcd_clear_display(); line = 0; + + uint32_t *ptr = &irqstackbegin; + for ( ; ptr < &irqstackend && *ptr == 0xDEADBEEF; ptr++) {} + + lcd_putsf(0, line++, "IRQ stack max: %d", (uint32_t)&irqstackend - (uint32_t)ptr); + display_clocks(); display_enabled_clocks(); #ifdef HAVE_TOUCHSCREEN @@ -169,8 +177,7 @@ bool dbg_hw_info(void) return true; } -#define CFG_UART_BASE UART1_BASE /* Base of the UART channel */ - +#ifdef WITH_SERIAL void serial_putc (const char c) { volatile u8 *uart_lsr = (volatile u8 *)(CFG_UART_BASE + OFF_LSR); @@ -271,3 +278,4 @@ void serial_dump_data(unsigned char* data, int len) serial_putc( '\n' ); } +#endif diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index 4489212ccc..a8e40e4e31 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c @@ -29,6 +29,9 @@ #include "power.h" //#define USE_HW_UDELAY // This is BROKEN. +#ifdef BOOTLOADER +#define WITH_SERIAL +#endif static int irq; static void UIRQ(void) @@ -535,6 +538,7 @@ void pll1_disable(void) REG_CPM_CPPCR1 &= ~CPPCR1_PLL1EN; } +#ifdef WITH_SERIAL static void serial_setbrg(void) { volatile u8 *uart_lcr = (volatile u8 *)(CFG_UART_BASE + OFF_LCR); @@ -589,6 +593,7 @@ int serial_preinit(void) return 0; } +#endif #ifndef HAVE_ADJUSTABLE_CPU_FREQ #define cpu_frequency CPU_FREQ @@ -698,7 +703,14 @@ void ICODE_ATTR system_main(void) pll0_init(CPUFREQ_DEFAULT); // PLL0 drives everything but audio pll1_disable(); // Leave PLL1 disabled until audio needs it + /* Make sure UARTs are off */ + __cpm_stop_uart0(); + __cpm_stop_uart1(); + __cpm_stop_uart2(); +#ifdef WITH_SERIAL serial_preinit(); +#endif + usb_preinit(); dma_preinit(); diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h index dd42fac633..d8c395cef2 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-target.h +++ b/firmware/target/mips/ingenic_jz47xx/system-target.h @@ -32,6 +32,8 @@ #define CACHE_LINE_SIZE 32 #include "mmu-mips.h" +#define CFG_UART_BASE UART1_BASE /* Base of the UART channel */ + /* no optimized byteswap functions implemented for mips, yet */ #define NEED_GENERIC_BYTESWAPS |