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| author | Tomasz Moń <desowin@gmail.com> | 2016-05-19 20:57:20 +0300 |
|---|---|---|
| committer | Gerrit Rockbox <gerrit@rockbox.org> | 2016-05-25 17:03:19 +0200 |
| commit | 94b23da3c4a9a96af8ae4a4b2308037acb8d58dd (patch) | |
| tree | 7d4849766bddf4bcc00ae57073f2803cbc152a52 | |
| parent | 9327885d141d9cdf8a476640b3e3ce572bd37790 (diff) | |
| download | rockbox-94b23da.tar.gz rockbox-94b23da.tar.bz2 rockbox-94b23da.zip | |
Sansa Connect: change bootloader linker file
This change ensures that Sansa Connect bootloader.bin will fit in its flash
partition.
Fix _flash_sizem calculation, division was not working properly because
FLASHSIZE included subtraction and defined value was not in parenthesis.
Prior to this change _flash_sizem was 0x00800000, now it is correctly set
to 4 in case of Sansa Connect and 8 in case of other TMS320DM320 players.
This significantly improves boot time as cache is now enabled only for
real flash memory region.
Change-Id: If3e50a3075c840dcb69dfafe5bba608a0acd2bf8
| -rw-r--r-- | firmware/target/arm/tms320dm320/boot.lds | 19 | ||||
| -rw-r--r-- | firmware/target/arm/tms320dm320/crt0.S | 2 |
2 files changed, 14 insertions, 7 deletions
diff --git a/firmware/target/arm/tms320dm320/boot.lds b/firmware/target/arm/tms320dm320/boot.lds index 43ed6486e9..c59cc7f514 100644 --- a/firmware/target/arm/tms320dm320/boot.lds +++ b/firmware/target/arm/tms320dm320/boot.lds @@ -34,6 +34,8 @@ STARTUP(target/arm/tms320dm320/crt0.o) #define IRAMORIG 0x00000000 #define IRAMSIZE 0x4000 +#define FLASHORIG 0x00100000 + #ifdef SANSA_CONNECT /* Offset in flash from beginning, we don't want overwrite OF bootloader due to recovery mode and more importantly - hardware block protection. @@ -41,15 +43,18 @@ STARTUP(target/arm/tms320dm320/crt0.o) In .srr file header add any valid memory address from following <0x1000000; 0x1300180) u (0x131EAF4; 0x1420000) u (0x1440000; 0x5000000> ensuring that complete bootloader fits in. - Entry point in .srr file should be 0x120010. */ -#define FLASHOFFSET 0x20010 + Entry point in .srr file should be equal to _loadaddress. */ +#define FLASHSIZE 0x00400000 +#define FLASHMEMORIG 0x00120010 +/* Kernel partition is 2 M, srr header is 16 bytes, sig is 2048 bytes */ +#define FLASHMEMSIZE 0x001FF7F0 #else -#define FLASHOFFSET 0 +/* On targets other than Sansa Connect use whole flash for bootloader */ +#define FLASHSIZE 0x00800000 +#define FLASHMEMORIG FLASHORIG +#define FLASHMEMSIZE FLASHSIZE #endif -#define FLASHORIG 0x00100000 -#define FLASHSIZE 0x00800000-FLASHOFFSET - PRO_STACK_SIZE = 0x2000; IRQ_STACK_SIZE = 0x400; FIQ_STACK_SIZE = 0x400; @@ -61,7 +66,7 @@ MEMORY { DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE - FLASH : ORIGIN = FLASHORIG+FLASHOFFSET, LENGTH = FLASHSIZE + FLASH : ORIGIN = FLASHMEMORIG, LENGTH = FLASHMEMSIZE } SECTIONS diff --git a/firmware/target/arm/tms320dm320/crt0.S b/firmware/target/arm/tms320dm320/crt0.S index 8351ddbf25..9f2c8dbe04 100644 --- a/firmware/target/arm/tms320dm320/crt0.S +++ b/firmware/target/arm/tms320dm320/crt0.S @@ -121,9 +121,11 @@ _start: ldr r2, =_vectorsend bl _copy_section +#if !defined(SANSA_CONNECT) /* Add some delay time to make sure JTAG can be accessed cleanly */ mov r0, #0x100000 bl _delay_cycles +#endif #if defined(BOOTLOADER) /* Copy the DRAM */ |