diff options
| author | Aidan MacDonald <amachronic@protonmail.com> | 2022-03-26 17:49:09 +0000 |
|---|---|---|
| committer | Aidan MacDonald <amachronic@protonmail.com> | 2022-04-01 12:08:41 -0400 |
| commit | 98f762316f0b065e9e4ce0ed8027eb0cc378eb32 (patch) | |
| tree | 084b14cfd35aa60751529ef946b2e484ff11c4c5 | |
| parent | de285741bfe5094d5f67b9244378359cb94b66ee (diff) | |
| download | rockbox-98f762316f.tar.gz rockbox-98f762316f.zip | |
system: update MEM_ALIGN_ATTR for targets with CPU cachesbootloader_erosq_v1
MEM_ALIGN_ATTR should take advantage of cache line alignment on
all native CPUs which define it, not just ARM CPUs. (This could
arguably be done for hosted targets too, but we don't necessarily
know the size of a cache line there.)
Change-Id: Ife9302105ea57388afd55ce31da848b00b5b1b25
| -rw-r--r-- | firmware/export/system.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h index f554ac7cf1..9558be559a 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h @@ -307,8 +307,8 @@ static inline void cpu_boost_unlock(void) /* Define MEM_ALIGN_ATTR which may be used to align e.g. buffers for faster * access. */ -#if defined(CPU_ARM) - /* Use ARMs cache alignment. */ +#if defined(HAVE_CPU_CACHE_ALIGN) + /* Align to a cache line. */ #define MEM_ALIGN_ATTR CACHEALIGN_ATTR #define MEM_ALIGN_SIZE CACHEALIGN_SIZE #elif defined(CPU_COLDFIRE) |