S5L8702: Move I/O addresses from DMA driver to SoC definitions, reuse existing definitions

No difference in the produced binaries for ipod6g (normal and bootloader)

This is a part of the large iPod Nano 3G and iPod Nano 4G support patch.

Change-Id: I82943e91ba7e6764428f853f84799f0d54b700a6

2 files changed, 50 insertions, 33 deletions

diff --git a/firmware/export/s5l87xx.h b/firmware/export/s5l87xx.h
index a6555d16ef..7a244264fd 100644
--- a/firmware/export/s5l87xx.h
+++ b/firmware/export/s5l87xx.h
@@ -1002,7 +1002,9 @@
 #define ECCCTRL_STARTDECNOSYND (1 << 2)
 
 /* 17. IIS Tx/Rx INTERFACE */
-#define I2S_BASE 0x3CA00000
+#define I2S_BASE              0x3CA00000
+#define I2S_INTERFACE1_OFFSET   0x300000
+#define I2S_INTERFACE2_OFFSET   0xA00000
 
 #define I2SCLKCON               (*(REG32_PTR_T)(I2S_BASE))            /* Clock Control Register */
 #define I2STXCON                (*(REG32_PTR_T)(I2S_BASE + 0x04))     /* Tx configuration Register */
@@ -1279,6 +1281,10 @@
 #define UARTC_BASE_ADDR     0x3CC00000
 #define UARTC_N_PORTS       4
 #define UARTC_PORT_OFFSET   0x4000
+#if CONFIG_CPU == S5L8720
+#define UARTC_DMA_BASE_ADDR   0x3DB00000
+#define UARTC_DMA_PORT_OFFSET 0x100000
+#endif
 #endif
 
 /* 26. LCD INTERFACE CONTROLLER */
@@ -1727,10 +1733,10 @@ Information for them was gathered solely by reverse-engineering Apple's firmware
 #define IRQ_EXT6        33
 #endif
 
-#if CONFIG_CPU == S5L8702
-/* Something related to the ATA controller, needed for power up */
+/* Something related to the ATA controller, needed for HDD power up on ipod6g */
 #define ATA_UNKNOWN_BASE 0x38a00000
 
+#if CONFIG_CPU == S5L8702
 #define ATA_UNKNOWN (*((REG32_PTR_T)(ATA_UNKNOWN_BASE)))
 #endif
 
diff --git a/firmware/target/arm/s5l8702/dma-s5l8702.h b/firmware/target/arm/s5l8702/dma-s5l8702.h
index 9065867481..79f15a9b07 100644
--- a/firmware/target/arm/s5l8702/dma-s5l8702.h
+++ b/firmware/target/arm/s5l8702/dma-s5l8702.h
@@ -84,43 +84,54 @@ extern struct dmac s5l8702_dmac1;
 #define S5L8702_DMAC1_PERI_MEM              DMAC_PERI_NONE
 
 /* s5l8702 peripheral DMA R/W addesses */
-#define S5L8702_DADDR_PERI_LCD_WR           0x38300040
+#define S5L8702_DADDR_PERI_LCD_WR           (LCD_BASE + 0x40)
 #if CONFIG_CPU == S5L8702
-#define S5L8702_DADDR_PERI_SPDIF_TX         0x3CB00010  /* TBC */
+#define S5L8702_DADDR_PERI_SPDIF_TX         (SPD_BASE + 0x10)  /* TBC */
 #endif
-#define S5L8702_DADDR_PERI_UART0_TX         0x3CC00020
-#define S5L8702_DADDR_PERI_UART0_RX         0x3CC00024
+#define S5L8702_DADDR_PERI_UART_TX(i)       (UARTC_BASE_ADDR + UARTC_PORT_OFFSET * (i) + 0x20)
+#define S5L8702_DADDR_PERI_UART_RX(i)       (UARTC_BASE_ADDR + UARTC_PORT_OFFSET * (i) + 0x24)
+#define S5L8702_DADDR_PERI_UART0_TX         S5L8702_DADDR_PERI_UART_TX(0)
+#define S5L8702_DADDR_PERI_UART0_RX         S5L8702_DADDR_PERI_UART_RX(0)
 #if CONFIG_CPU == S5L8702
-#define S5L8702_DADDR_PERI_UART1_TX         0x3CC04020
-#define S5L8702_DADDR_PERI_UART1_RX         0x3CC04024
-#define S5L8702_DADDR_PERI_UART2_TX         0x3CC08020
-#define S5L8702_DADDR_PERI_UART2_RX         0x3CC08024
-#define S5L8702_DADDR_PERI_UART3_TX         0x3CC0C020
-#define S5L8702_DADDR_PERI_UART3_RX         0x3CC0C024
+#define S5L8702_DADDR_PERI_UART1_TX         S5L8702_DADDR_PERI_UART_TX(1)
+#define S5L8702_DADDR_PERI_UART1_RX         S5L8702_DADDR_PERI_UART_RX(1)
+#define S5L8702_DADDR_PERI_UART2_TX         S5L8702_DADDR_PERI_UART_TX(2)
+#define S5L8702_DADDR_PERI_UART2_RX         S5L8702_DADDR_PERI_UART_RX(2)
+#define S5L8702_DADDR_PERI_UART3_TX         S5L8702_DADDR_PERI_UART_TX(3)
+#define S5L8702_DADDR_PERI_UART3_RX         S5L8702_DADDR_PERI_UART_RX(3)
 #elif CONFIG_CPU == S5L8720
-#define S5L8702_DADDR_PERI_UART1_TX         0x3DB00020
-#define S5L8702_DADDR_PERI_UART1_RX         0x3DB00024
-#define S5L8702_DADDR_PERI_UART2_TX         0x3DC00020
-#define S5L8702_DADDR_PERI_UART2_RX         0x3DC00024
-#define S5L8702_DADDR_PERI_UART3_TX         0x3DD00020
-#define S5L8702_DADDR_PERI_UART3_RX         0x3DD00024
+#define S5L8720_DADDR_PERI_UART_TX(i)       (UARTC_DMA_BASE_ADDR + UARTC_DMA_PORT_OFFSET * (i - 1) + 0x20)
+#define S5L8720_DADDR_PERI_UART_RX(i)       (UARTC_DMA_BASE_ADDR + UARTC_DMA_PORT_OFFSET * (i - 1) + 0x24)
+#define S5L8702_DADDR_PERI_UART1_TX         S5L8720_DADDR_PERI_UART_TX(1)
+#define S5L8702_DADDR_PERI_UART1_RX         S5L8720_DADDR_PERI_UART_RX(1)
+#define S5L8702_DADDR_PERI_UART2_TX         S5L8720_DADDR_PERI_UART_TX(2)
+#define S5L8702_DADDR_PERI_UART2_RX         S5L8720_DADDR_PERI_UART_RX(2)
+#define S5L8702_DADDR_PERI_UART3_TX         S5L8720_DADDR_PERI_UART_TX(3)
+#define S5L8702_DADDR_PERI_UART3_RX         S5L8720_DADDR_PERI_UART_RX(3)
 #endif
-#define S5L8702_DADDR_PERI_IIS0_TX          0x3CA00010
-#define S5L8702_DADDR_PERI_IIS0_RX          0x3CA00038
-#define S5L8702_DADDR_PERI_IIS1_TX          0x3CD00010
-#define S5L8702_DADDR_PERI_IIS1_RX          0x3CD00038
-#define S5L8702_DADDR_PERI_IIS2_TX          0x3D400010
-#define S5L8702_DADDR_PERI_IIS2_RX          0x3D400038
-#define S5L8702_DADDR_PERI_CEATA_WR         0x38A00080
+#define S5L8702_DADDR_PERI_IIS_OFFSET(i)    ((i) == 2 ? I2S_INTERFACE2_OFFSET : \
+                                             (i) == 1 ? I2S_INTERFACE1_OFFSET : \
+                                                        0)
+#define S5L8702_DADDR_PERI_IIS_TX(i)        (I2S_BASE + S5L8702_DADDR_PERI_IIS_OFFSET(i) + 0x10)
+#define S5L8702_DADDR_PERI_IIS_RX(i)        (I2S_BASE + S5L8702_DADDR_PERI_IIS_OFFSET(i) + 0x38)
+#define S5L8702_DADDR_PERI_IIS0_TX          S5L8702_DADDR_PERI_IIS_TX(0)
+#define S5L8702_DADDR_PERI_IIS0_RX          S5L8702_DADDR_PERI_IIS_RX(0)
+#define S5L8702_DADDR_PERI_IIS1_TX          S5L8702_DADDR_PERI_IIS_TX(1)
+#define S5L8702_DADDR_PERI_IIS1_RX          S5L8702_DADDR_PERI_IIS_RX(1)
+#define S5L8702_DADDR_PERI_IIS2_TX          S5L8702_DADDR_PERI_IIS_TX(2)
+#define S5L8702_DADDR_PERI_IIS2_RX          S5L8702_DADDR_PERI_IIS_RX(2)
+#define S5L8702_DADDR_PERI_CEATA_WR         (ATA_UNKNOWN_BASE + 0x80)
 #if CONFIG_CPU == S5L8702
-#define S5L8702_DADDR_PERI_CEATA_RD         0x38A04080
+#define S5L8702_DADDR_PERI_CEATA_RD         (ATA_UNKNOWN_BASE + 0x4000 + 0x80)
 #endif
-#define S5L8702_DADDR_PERI_SPI0_TX          0x3C300010
-#define S5L8702_DADDR_PERI_SPI0_RX          0x3C300020
-#define S5L8702_DADDR_PERI_SPI1_TX          0x3CE00010
-#define S5L8702_DADDR_PERI_SPI1_RX          0x3CE00020
-#define S5L8702_DADDR_PERI_SPI2_TX          0x3D200010
-#define S5L8702_DADDR_PERI_SPI2_RX          0x3D200020
+#define S5L8702_DADDR_PERI_SPI_TX(i)        (SPIBASE(i) + 0x10)
+#define S5L8702_DADDR_PERI_SPI_RX(i)        (SPIBASE(i) + 0x20)
+#define S5L8702_DADDR_PERI_SPI0_TX          S5L8702_DADDR_PERI_SPI_TX(0)
+#define S5L8702_DADDR_PERI_SPI0_RX          S5L8702_DADDR_PERI_SPI_RX(0)
+#define S5L8702_DADDR_PERI_SPI1_TX          S5L8702_DADDR_PERI_SPI_TX(1)
+#define S5L8702_DADDR_PERI_SPI1_RX          S5L8702_DADDR_PERI_SPI_RX(1)
+#define S5L8702_DADDR_PERI_SPI2_TX          S5L8702_DADDR_PERI_SPI_TX(2)
+#define S5L8702_DADDR_PERI_SPI2_RX          S5L8702_DADDR_PERI_SPI_RX(2)
 
 /* proto */
 void dma_init(void);