summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMarcoen Hirschberg <marcoen@gmail.com>2008-03-27 11:29:24 +0000
committerMarcoen Hirschberg <marcoen@gmail.com>2008-03-27 11:29:24 +0000
commitc7e5d78241699500b18ce783607af7ae52ee021f (patch)
treea6aaf5c7d59fedf18fe944956c4e2c3b72cbd638
parentbe40427baeacb88e27a4d8117addd60ca1fbc4c7 (diff)
downloadrockbox-c7e5d78241699500b18ce783607af7ae52ee021f.tar.gz
rockbox-c7e5d78241699500b18ce783607af7ae52ee021f.tar.bz2
rockbox-c7e5d78241699500b18ce783607af7ae52ee021f.zip
initial Meizu M6SL port
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16844 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--apps/SOURCES2
-rw-r--r--apps/keymaps/keymap-meizu-m6sl.c303
-rw-r--r--bootloader/SOURCES2
-rw-r--r--firmware/SOURCES7
-rw-r--r--firmware/drivers/tuner/tea5760uk.c135
-rw-r--r--firmware/export/config-meizu-m6sl.h170
-rw-r--r--firmware/export/config.h15
-rw-r--r--firmware/export/s5l8700.h536
-rw-r--r--firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h33
-rw-r--r--firmware/target/arm/s5l8700/meizu-m6sl/button-target.h52
-rwxr-xr-xtools/configure26
-rw-r--r--tools/makesrc.inc3
-rw-r--r--uisimulator/sdl/button.c31
-rw-r--r--uisimulator/sdl/uisdl.h13
14 files changed, 1323 insertions, 5 deletions
diff --git a/apps/SOURCES b/apps/SOURCES
index 96b5c0f825..7096d06a41 100644
--- a/apps/SOURCES
+++ b/apps/SOURCES
@@ -175,4 +175,6 @@ keymaps/keymap-mr500.c
keymaps/keymap-mr100.c
#elif CONFIG_KEYPAD == COWOND2_PAD
keymaps/keymap-cowond2.c
+#elif CONFIG_KEYPAD == MEIZU_M6SL_PAD
+keymaps/keymap-meizu-m6sl.c
#endif
diff --git a/apps/keymaps/keymap-meizu-m6sl.c b/apps/keymaps/keymap-meizu-m6sl.c
new file mode 100644
index 0000000000..a473c88311
--- /dev/null
+++ b/apps/keymaps/keymap-meizu-m6sl.c
@@ -0,0 +1,303 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2006 Jonathan Gordon
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* Button Code Definitions for the toshiba gigabeat target */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "config.h"
+#include "action.h"
+#include "button.h"
+#include "settings.h"
+
+/*
+ * The format of the list is as follows
+ * { Action Code, Button code, Prereq button code }
+ * if there's no need to check the previous button's value, use BUTTON_NONE
+ * Insert LAST_ITEM_IN_LIST at the end of each mapping
+ */
+
+/* CONTEXT_CUSTOM's used in this file...
+
+CONTEXT_CUSTOM|CONTEXT_TREE = the standard list/tree defines (without directions)
+CONTEXT_CUSTOM|CONTEXT_SETTINGS = the direction keys for the eq/col picker screens
+ i.e where up/down is inc/dec
+ CONTEXT_SETTINGS = up/down is prev/next, l/r is inc/dec
+
+*/
+
+
+static const struct button_mapping button_context_standard[] = {
+ { ACTION_STD_PREV, BUTTON_UP, BUTTON_NONE },
+ { ACTION_STD_PREVREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_STD_NEXT, BUTTON_DOWN, BUTTON_NONE },
+ { ACTION_STD_NEXTREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
+
+ { ACTION_STD_CANCEL, BUTTON_LEFT, BUTTON_NONE },
+
+ { ACTION_STD_CONTEXT, BUTTON_SELECT|BUTTON_REPEAT,BUTTON_SELECT },
+
+ { ACTION_STD_QUICKSCREEN, BUTTON_MENU|BUTTON_REPEAT, BUTTON_MENU },
+ { ACTION_STD_MENU, BUTTON_MENU|BUTTON_REL, BUTTON_MENU },
+
+ { ACTION_STD_OK, BUTTON_SELECT|BUTTON_REL, BUTTON_SELECT },
+ { ACTION_STD_OK, BUTTON_RIGHT, BUTTON_NONE },
+
+ LAST_ITEM_IN_LIST
+}; /* button_context_standard */
+
+
+static const struct button_mapping button_context_wps[] = {
+ { ACTION_WPS_PLAY, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY },
+ { ACTION_WPS_STOP, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE },
+
+ { ACTION_WPS_SKIPNEXT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT },
+ { ACTION_WPS_SKIPPREV, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT },
+
+ { ACTION_WPS_SEEKBACK, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_WPS_SEEKFWD, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_WPS_STOPSEEK, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT|BUTTON_REPEAT },
+ { ACTION_WPS_STOPSEEK, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT|BUTTON_REPEAT },
+
+ { ACTION_WPS_ABSETB_NEXTDIR, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_NONE },
+ { ACTION_WPS_ABSETA_PREVDIR, BUTTON_PLAY|BUTTON_LEFT, BUTTON_NONE },
+ { ACTION_WPS_ABRESET, BUTTON_PLAY|BUTTON_SELECT, BUTTON_NONE },
+
+ { ACTION_WPS_VOLDOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_WPS_VOLDOWN, BUTTON_DOWN, BUTTON_NONE },
+ { ACTION_WPS_VOLUP, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_WPS_VOLUP, BUTTON_UP, BUTTON_NONE },
+
+ { ACTION_WPS_PITCHSCREEN, BUTTON_PLAY|BUTTON_UP, BUTTON_PLAY },
+ { ACTION_WPS_PITCHSCREEN, BUTTON_PLAY|BUTTON_DOWN, BUTTON_PLAY },
+
+ { ACTION_WPS_QUICKSCREEN, BUTTON_MENU|BUTTON_REPEAT, BUTTON_MENU },
+ { ACTION_WPS_MENU, BUTTON_MENU|BUTTON_REL, BUTTON_MENU },
+ { ACTION_WPS_CONTEXT, BUTTON_SELECT|BUTTON_REPEAT, BUTTON_SELECT },
+
+ { ACTION_WPS_ID3SCREEN, BUTTON_PLAY|BUTTON_MENU, BUTTON_NONE },
+ { ACTION_WPS_BROWSE, BUTTON_SELECT|BUTTON_REL, BUTTON_SELECT },
+
+ LAST_ITEM_IN_LIST
+}; /* button_context_wps */
+
+static const struct button_mapping button_context_list[] = {
+ { ACTION_LISTTREE_PGUP, BUTTON_PLAY|BUTTON_UP, BUTTON_PLAY },
+ { ACTION_LISTTREE_PGUP, BUTTON_UP|BUTTON_REL, BUTTON_PLAY|BUTTON_UP },
+ { ACTION_LISTTREE_PGUP, BUTTON_PLAY|BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_LISTTREE_PGDOWN, BUTTON_PLAY|BUTTON_DOWN, BUTTON_PLAY },
+ { ACTION_LISTTREE_PGDOWN, BUTTON_DOWN|BUTTON_REL, BUTTON_PLAY|BUTTON_DOWN },
+ { ACTION_LISTTREE_PGDOWN, BUTTON_PLAY|BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
+
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_list */
+
+static const struct button_mapping button_context_tree[] = {
+ { ACTION_TREE_WPS, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY },
+ { ACTION_TREE_STOP, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE },
+
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST)
+}; /* button_context_tree */
+
+static const struct button_mapping button_context_listtree_scroll_with_combo[] = {
+ { ACTION_NONE, BUTTON_PLAY, BUTTON_NONE },
+ { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_PLAY },
+ { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REL, BUTTON_PLAY|BUTTON_LEFT },
+ { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_LEFT|BUTTON_REL },
+ { ACTION_TREE_ROOT_INIT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_PLAY|BUTTON_LEFT },
+ { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_PLAY },
+ { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REL, BUTTON_PLAY|BUTTON_RIGHT },
+ { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_RIGHT|BUTTON_REL },
+ { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE),
+};
+
+static const struct button_mapping button_context_listtree_scroll_without_combo[] = {
+ { ACTION_NONE, BUTTON_LEFT, BUTTON_NONE },
+ { ACTION_STD_CANCEL, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT },
+ { ACTION_TREE_ROOT_INIT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_LEFT },
+ { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT|BUTTON_REPEAT },
+ { ACTION_NONE, BUTTON_RIGHT, BUTTON_NONE },
+ { ACTION_STD_OK, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT },
+ { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT|BUTTON_REPEAT },
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE),
+};
+
+static const struct button_mapping button_context_settings[] = {
+ { ACTION_SETTINGS_INC, BUTTON_UP, BUTTON_NONE },
+ { ACTION_SETTINGS_INCREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_SETTINGS_DEC, BUTTON_DOWN, BUTTON_NONE },
+ { ACTION_SETTINGS_DECREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_STD_PREV, BUTTON_LEFT, BUTTON_NONE },
+ { ACTION_STD_PREVREPEAT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_STD_NEXT, BUTTON_RIGHT, BUTTON_NONE },
+ { ACTION_STD_NEXTREPEAT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_SETTINGS_RESET, BUTTON_PLAY, BUTTON_NONE },
+
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_settings */
+
+static const struct button_mapping button_context_settings_right_is_inc[] = {
+ { ACTION_SETTINGS_INC, BUTTON_RIGHT, BUTTON_NONE },
+ { ACTION_SETTINGS_INCREPEAT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_SETTINGS_DEC, BUTTON_LEFT, BUTTON_NONE },
+ { ACTION_SETTINGS_DECREPEAT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_STD_PREV, BUTTON_UP, BUTTON_NONE },
+ { ACTION_STD_PREVREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_STD_NEXT, BUTTON_DOWN, BUTTON_NONE },
+ { ACTION_STD_NEXTREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_SETTINGS_RESET, BUTTON_PLAY, BUTTON_NONE },
+
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_settingsgraphical */
+
+static const struct button_mapping button_context_yesno[] = {
+ { ACTION_YESNO_ACCEPT, BUTTON_SELECT, BUTTON_NONE },
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_settings_yesno */
+
+static const struct button_mapping button_context_colorchooser[] = {
+ { ACTION_STD_OK, BUTTON_PLAY|BUTTON_REL, BUTTON_NONE },
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS),
+}; /* button_context_colorchooser */
+
+static const struct button_mapping button_context_eq[] = {
+ { ACTION_STD_OK, BUTTON_SELECT|BUTTON_REL, BUTTON_NONE },
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS),
+}; /* button_context_eq */
+
+/** Bookmark Screen **/
+static const struct button_mapping button_context_bmark[] = {
+ { ACTION_BMS_DELETE, BUTTON_PLAY, BUTTON_NONE },
+
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST),
+}; /* button_context_bmark */
+
+static const struct button_mapping button_context_time[] = {
+ { ACTION_STD_CANCEL, BUTTON_LEFT, BUTTON_NONE },
+ { ACTION_STD_OK, BUTTON_PLAY, BUTTON_NONE },
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_SETTINGS),
+}; /* button_context_time */
+
+static const struct button_mapping button_context_quickscreen[] = {
+ { ACTION_QS_DOWNINV, BUTTON_UP, BUTTON_NONE },
+ { ACTION_QS_DOWNINV, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_QS_DOWN, BUTTON_DOWN, BUTTON_NONE },
+ { ACTION_QS_DOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_QS_LEFT, BUTTON_LEFT, BUTTON_NONE },
+ { ACTION_QS_LEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_QS_RIGHT, BUTTON_RIGHT, BUTTON_NONE },
+ { ACTION_QS_RIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_STD_CANCEL, BUTTON_MENU, BUTTON_NONE },
+
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_quickscreen */
+
+static const struct button_mapping button_context_pitchscreen[] = {
+ { ACTION_PS_INC_SMALL, BUTTON_UP, BUTTON_NONE },
+ { ACTION_PS_INC_BIG, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_PS_DEC_SMALL, BUTTON_DOWN, BUTTON_NONE },
+ { ACTION_PS_DEC_BIG, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_PS_NUDGE_LEFT, BUTTON_LEFT, BUTTON_NONE },
+ { ACTION_PS_NUDGE_LEFTOFF, BUTTON_LEFT|BUTTON_REL, BUTTON_NONE },
+ { ACTION_PS_NUDGE_RIGHT, BUTTON_RIGHT, BUTTON_NONE },
+ { ACTION_PS_NUDGE_RIGHTOFF, BUTTON_RIGHT|BUTTON_REL, BUTTON_NONE },
+ { ACTION_PS_TOGGLE_MODE, BUTTON_MENU, BUTTON_NONE },
+ { ACTION_PS_RESET, BUTTON_PLAY, BUTTON_NONE },
+ { ACTION_PS_EXIT, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE },
+
+ LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD)
+}; /* button_context_pitchcreen */
+
+static const struct button_mapping button_context_keyboard[] = {
+ { ACTION_KBD_LEFT, BUTTON_LEFT, BUTTON_NONE },
+ { ACTION_KBD_LEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_KBD_RIGHT, BUTTON_RIGHT, BUTTON_NONE },
+ { ACTION_KBD_RIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_KBD_CURSOR_LEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_NONE },
+ { ACTION_KBD_CURSOR_LEFT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_KBD_CURSOR_RIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_NONE },
+ { ACTION_KBD_CURSOR_RIGHT, BUTTON_PLAY|BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_KBD_SELECT, BUTTON_SELECT, BUTTON_NONE },
+ { ACTION_KBD_PAGE_FLIP, BUTTON_PLAY|BUTTON_MENU, BUTTON_NONE },
+ { ACTION_KBD_DONE, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY },
+ { ACTION_KBD_ABORT, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_KBD_BACKSPACE, BUTTON_MENU, BUTTON_NONE },
+ { ACTION_KBD_BACKSPACE, BUTTON_MENU|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_KBD_UP, BUTTON_UP, BUTTON_NONE },
+ { ACTION_KBD_UP, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE },
+ { ACTION_KBD_DOWN, BUTTON_DOWN, BUTTON_NONE },
+ { ACTION_KBD_DOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE },
+// { ACTION_KBD_MORSE_INPUT, BUTTON_PLAY|BUTTON_POWER, BUTTON_NONE },
+ { ACTION_KBD_MORSE_SELECT, BUTTON_SELECT|BUTTON_REL, BUTTON_NONE },
+
+ LAST_ITEM_IN_LIST
+}; /* button_context_keyboard */
+
+
+const struct button_mapping* get_context_mapping(int context)
+{
+ switch (context)
+ {
+ case CONTEXT_STD:
+ return button_context_standard;
+ case CONTEXT_WPS:
+ return button_context_wps;
+
+ case CONTEXT_LIST:
+ return button_context_list;
+ case CONTEXT_MAINMENU:
+ case CONTEXT_TREE:
+ if (global_settings.hold_lr_for_scroll_in_list)
+ return button_context_listtree_scroll_without_combo;
+ else
+ return button_context_listtree_scroll_with_combo;
+ case CONTEXT_CUSTOM|CONTEXT_TREE:
+ return button_context_tree;
+
+ case CONTEXT_SETTINGS:
+ return button_context_settings;
+ case CONTEXT_CUSTOM|CONTEXT_SETTINGS:
+ return button_context_settings_right_is_inc;
+
+ case CONTEXT_SETTINGS_COLOURCHOOSER:
+ return button_context_colorchooser;
+ case CONTEXT_SETTINGS_EQ:
+ return button_context_eq;
+
+ case CONTEXT_SETTINGS_TIME:
+ return button_context_time;
+
+ case CONTEXT_YESNOSCREEN:
+ return button_context_yesno;
+ case CONTEXT_BOOKMARKSCREEN:
+ return button_context_bmark;
+ case CONTEXT_QUICKSCREEN:
+ return button_context_quickscreen;
+ case CONTEXT_PITCHSCREEN:
+ return button_context_pitchscreen;
+ case CONTEXT_KEYBOARD:
+ return button_context_keyboard;
+ }
+ return button_context_standard;
+}
diff --git a/bootloader/SOURCES b/bootloader/SOURCES
index 9e961eeb29..2854878084 100644
--- a/bootloader/SOURCES
+++ b/bootloader/SOURCES
@@ -27,4 +27,6 @@ iriver_h300.c
mrobe500.c
#elif defined(CPU_TCC77X) || defined(CPU_TCC780X)
telechips.c
+#elif defined(MEIZU_M6SL)
+meizu_m6sl.c
#endif
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 8fe5661759..4937e6e6c6 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -924,3 +924,10 @@ target/arm/tcc780x/cowond2/pcm-cowond2.c
#endif /* BOOTLOADER */
#endif /* SIMULATOR */
#endif /* COWON_D2 */
+
+#ifdef MEIZU_M6SL
+#ifndef SIMULATOR
+#ifndef BOOTLOADER
+#endif /* BOOTLOADER */
+#endif /* SIMULATOR */
+#endif /* MEIZU_M6SL */
diff --git a/firmware/drivers/tuner/tea5760uk.c b/firmware/drivers/tuner/tea5760uk.c
new file mode 100644
index 0000000000..8ac6cb2dbc
--- /dev/null
+++ b/firmware/drivers/tuner/tea5760uk.c
@@ -0,0 +1,135 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ * Tuner "middleware" for Philips TEA5760 chip
+ *
+ * Copyright (C) 2004 Jörg Hohensohn
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include <stdbool.h>
+#include <string.h>
+#include <stdlib.h>
+#include "kernel.h"
+#include "tuner.h" /* tuner abstraction interface */
+#include "fmradio.h"
+#include "fmradio_i2c.h" /* physical interface driver */
+
+#define I2C_ADR 0xC0
+static unsigned char write_bytes[7] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+static void tea5760uk_set_clear(int byte, unsigned char bits, int set)
+{
+ write_bytes[byte] &= ~bits;
+ if (set)
+ write_bytes[byte] |= bits;
+}
+
+/* tuner abstraction layer: set something to the tuner */
+int tea5760uk_set(int setting, int value)
+{
+ switch(setting)
+ {
+ case RADIO_SLEEP:
+ /* init values */
+ write_bytes[0] |= (1<<7); /* mute */
+#if CONFIG_TUNER_XTAL == 32768
+ /* 32.768kHz, soft mute, stereo noise cancelling */
+ write_bytes[3] |= (1<<4) | (1<<3) | (1<<1);
+#else
+ /* soft mute, stereo noise cancelling */
+ write_bytes[3] |= (1<<3) | (1<<1);
+#endif
+ /* sleep / standby mode */
+ tea5760uk_set_clear(3, (1<<6), value);
+ break;
+
+ case RADIO_FREQUENCY:
+ {
+ int n;
+#if CONFIG_TUNER_XTAL == 32768
+ n = (4 * (value - 225000) + 16384) / 32768;
+#else
+ n = (4 * (value - 225000)) / 50000;
+#endif
+ write_bytes[6] = (write_bytes[6] & 0xC0) | (n >> 8);
+ write_bytes[7] = n;
+ }
+ break;
+
+ case RADIO_SCAN_FREQUENCY:
+ tea5760uk_set(RADIO_FREQUENCY, value);
+ sleep(HZ/30);
+ return tea5760uk_get(RADIO_TUNED);
+
+ case RADIO_MUTE:
+ tea5760uk_set_clear(3, (1<<2), value);
+ break;
+
+ case RADIO_REGION:
+ {
+ const struct tea5760uk_region_data *rd =
+ &tea5760uk_region_data[value];
+
+ tea5760uk_set_clear(4, (1<<1), rd->deemphasis);
+ tea5760uk_set_clear(3, (1<<5), rd->band);
+ break;
+ }
+ case RADIO_FORCE_MONO:
+ tea5760uk_set_clear(4, (1<<3), value);
+ break;
+ default:
+ return -1;
+ }
+
+ fmradio_i2c_write(I2C_ADR, write_bytes, sizeof(write_bytes));
+ return 1;
+}
+
+/* tuner abstraction layer: read something from the tuner */
+int tea5760uk_get(int setting)
+{
+ unsigned char read_bytes[16];
+ int val = -1; /* default for unsupported query */
+
+ fmradio_i2c_read(I2C_ADR, read_bytes, sizeof(read_bytes));
+
+ switch(setting)
+ {
+ case RADIO_PRESENT:
+ val = 1; /* true */
+ break;
+
+ case RADIO_TUNED:
+ val = 0;
+ if (read_bytes[0] & (1<<4)) /* IF count correct */
+ {
+ val = read_bytes[8] >> 1; /* IF counter */
+ val = (abs(val - 0x36) < 2); /* close match */
+ }
+ break;
+
+ case RADIO_STEREO:
+ val = read_bytes[9] >> 2;
+ break;
+ }
+
+ return val;
+}
+
+void tea5760uk_dbg_info(struct tea5760uk_dbg_info *info)
+{
+ fmradio_i2c_read(I2C_ADR, info->read_regs, 5);
+ memcpy(info->write_regs, write_bytes, 5);
+}
diff --git a/firmware/export/config-meizu-m6sl.h b/firmware/export/config-meizu-m6sl.h
new file mode 100644
index 0000000000..1c3b5f8a23
--- /dev/null
+++ b/firmware/export/config-meizu-m6sl.h
@@ -0,0 +1,170 @@
+/*
+ * This config file is for iAudio X5
+ */
+#define TARGET_TREE /* this target is using the target tree system */
+
+/* For Rolo and boot loader */
+#define MODEL_NUMBER 1
+
+/* define this if you have recording possibility */
+//#define HAVE_RECORDING
+
+/* Define bitmask of input sources - recordable bitmask can be defined
+ explicitly if different */
+#define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_FMRADIO)
+
+/* define the bitmask of hardware sample rates */
+#define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11)
+
+/* define the bitmask of recording sample rates */
+#define REC_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11)
+
+/* define this if you have a bitmap LCD display */
+#define HAVE_LCD_BITMAP
+
+/* define this if you can flip your LCD */
+//#define HAVE_LCD_FLIP
+
+/* define this if you have a colour LCD */
+#define HAVE_LCD_COLOR
+
+/* define this if you want album art for this target */
+#define HAVE_ALBUMART
+
+/* define this if you can invert the colours on your LCD */
+//#define HAVE_LCD_INVERT
+
+/* define this if you have access to the quickscreen */
+#define HAVE_QUICKSCREEN
+
+/* define this if you have access to the pitchscreen */
+#define HAVE_PITCHSCREEN
+
+/* define this if you would like tagcache to build on this target */
+#define HAVE_TAGCACHE
+
+/* define this if you have a flash memory storage */
+#define HAVE_FLASH_STORAGE
+
+/* LCD dimensions */
+#define LCD_WIDTH 320
+#define LCD_HEIGHT 240
+#define LCD_DEPTH 16 /* pseudo 262.144 colors */
+#define LCD_PIXELFORMAT RGB565 /* rgb565 */
+
+/* Define this if your LCD can be enabled/disabled */
+//#define HAVE_LCD_ENABLE
+
+/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
+ should be defined as well. */
+//#define HAVE_LCD_SLEEP
+
+#define CONFIG_KEYPAD MEIZU_M6SL_PAD
+
+//#define AB_REPEAT_ENABLE 1
+//#define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE
+
+/* Define this if you do software codec */
+#define CONFIG_CODEC SWCODEC
+
+/* define this if you have a real-time clock */
+#define CONFIG_RTC RTC_S5L8700
+//#define CONFIG_RTC RTC_S35390A
+
+#define CONFIG_LCD LCD_S6D0129
+
+/* Define this for LCD backlight available */
+#define HAVE_BACKLIGHT
+#define HAVE_BACKLIGHT_BRIGHTNESS
+
+/* Define this if you have a software controlled poweroff */
+#define HAVE_SW_POWEROFF
+
+/* The number of bytes reserved for loadable codecs */
+#define CODEC_SIZE 0x80000
+
+/* The number of bytes reserved for loadable plugins */
+#define PLUGIN_BUFFER_SIZE 0x80000
+
+/* FM Tuner */
+#define CONFIG_TUNER TEA5760
+#define CONFIG_TUNER_XTAL 32768
+
+//#define HAVE_TLV320
+
+/* TLV320 has no tone controls, so we use the software ones */
+#define HAVE_SW_TONE_CONTROLS
+
+#define BATTERY_CAPACITY_DEFAULT 700 /* default battery capacity */
+#define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */
+#define BATTERY_CAPACITY_MAX 2250 /* max. capacity selectable */
+#define BATTERY_CAPACITY_INC 50 /* capacity increment */
+#define BATTERY_TYPES_COUNT 1 /* only one type */
+
+/* Hardware controlled charging? FIXME */
+#define CONFIG_CHARGING CHARGING_SIMPLE
+
+#ifndef SIMULATOR
+
+/* Define this if your LCD can set contrast */
+//#define HAVE_LCD_CONTRAST
+
+/* Define this if you have a Motorola SCF5250 */
+#define CONFIG_CPU S5L8700
+
+/* Define this if you want to use coldfire's i2c interface */
+#define CONFIG_I2C I2C_S5L8700
+
+/* define this if the hardware can be powered off while charging */
+#define HAVE_POWEROFF_WHILE_CHARGING
+
+/* The size of the flash ROM */
+#define FLASH_SIZE 0x400000
+
+/* Define this to the CPU frequency */
+#define CPU_FREQ 11289600
+
+/* Define this if you have ATA power-off control */
+//#define HAVE_ATA_POWER_OFF
+
+/* Virtual LED (icon) */
+#define CONFIG_LED LED_VIRTUAL
+
+/* Offset ( in the firmware file's header ) to the file CRC */
+#define FIRMWARE_OFFSET_FILE_CRC 0
+
+/* Offset ( in the firmware file's header ) to the real data */
+#define FIRMWARE_OFFSET_FILE_DATA 8
+
+/* USB On-the-go */
+//#define CONFIG_USBOTG USBOTG_M5636
+
+/* Define this if you have adjustable CPU frequency */
+#define HAVE_ADJUSTABLE_CPU_FREQ
+
+#define BOOTFILE_EXT "meizu"
+#define BOOTFILE "rockbox." BOOTFILE_EXT
+#define BOOTDIR "/.rockbox"
+
+#define BOOTLOADER_ENTRYPOINT 0x001F0000
+#define FLASH_ENTRYPOINT 0x00001000
+#define FLASH_MAGIC 0xfbfbfbf1
+
+#endif /* SIMULATOR */
+
+/* Define this for FM radio input available */
+#define HAVE_FMRADIO_IN
+
+/** Port-specific settings **/
+
+/* Main LCD contrast range and defaults */
+#define MIN_CONTRAST_SETTING 1
+#define MAX_CONTRAST_SETTING 30
+#define DEFAULT_CONTRAST_SETTING 19 /* Match boot contrast */
+
+/* Main LCD backlight brightness range and defaults */
+/* PCF50506 can output 0%-100% duty cycle but D305A expects %15-100%. */
+#define MIN_BRIGHTNESS_SETTING 1 /* 15/16 (93.75%) */
+#define MAX_BRIGHTNESS_SETTING 13 /* 3/16 (18.75%) */
+#define DEFAULT_BRIGHTNESS_SETTING 8 /* 8/16 (50.00%) = x5 boot default */
+
diff --git a/firmware/export/config.h b/firmware/export/config.h
index 1a288dd590..4746506c99 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -31,6 +31,8 @@
#define TEA5767 0x02 /* Philips */
#define LV24020LP 0x04 /* Sanyo */
#define SI4700 0x08 /* Silicon Labs */
+#define TEA5760 0x10 /* Philips */
+#define LV240000 0x20 /* Sanyo */
/* CONFIG_CODEC */
#define MAS3587F 3587
@@ -54,6 +56,7 @@
#define TCC771L 771
#define TCC773L 773
#define TCC7801 7801
+#define S5L8700 8700
/* CONFIG_KEYPAD */
#define PLAYER_PAD 1
@@ -79,6 +82,7 @@
#define IAUDIO67_PAD 21
#define COWOND2_PAD 22
#define IAUDIO_M3_PAD 23
+#define MEIZU_M6SL_PAD 24
/* CONFIG_REMOTE_KEYPAD */
#define H100_REMOTE 1
@@ -117,6 +121,7 @@
#define LCD_CREATIVEZVM 22 /* as used by Creative Zen Vision:M */
#define LCD_TL0350A 23 /* as used by the iAudio M3 remote, treated as main LCD */
#define LCD_COWOND2 24 /* as used by Cowon D2 - LTV250QV, TCC7801 driver */
+#define LCD_S6D0129 25 /* as used by the Meizu M6SP and M6SL - S6D0129 */
/* LCD_PIXELFORMAT */
#define HORIZONTAL_PACKING 1
@@ -143,6 +148,7 @@
#define I2C_IMX31L 9
#define I2C_TCC77X 10
#define I2C_TCC780X 11
+#define I2C_S5L8700 12
/* CONFIG_LED */
#define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */
@@ -165,6 +171,8 @@
#define RTC_TCC77X 10
#define RTC_TCC780X 11
#define RTC_MR100 12
+#define RTC_S5L8700 13
+#define RTC_S35390A 14
/* USB On-the-go */
#define USBOTG_ISP1362 1362 /* iriver H300 */
@@ -246,6 +254,8 @@
#include "config-cowond2.h"
#elif defined(CREATIVE_ZVM)
#include "config-creativezvm.h"
+#elif defined(MEIZU_M6SL)
+#include "config-meizu-m6sl.h"
#else
/* no known platform */
#endif
@@ -382,7 +392,7 @@
#endif
#if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \
- || (CONFIG_CPU == DSC25) || (CONFIG_CPU == DM320)
+ || (CONFIG_CPU == DSC25) || (CONFIG_CPU == DM320) || (CONFIG_CPU == S5L8700)
#define CPU_ARM
#define ARM_ARCH 4 /* ARMv4 */
#endif
@@ -411,7 +421,8 @@
defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \
defined(CPU_TCC77X) || /* Telechips: core, plugins, codecs */ \
defined(CPU_TCC780X) || /* Telechips: core, plugins, codecs */ \
- (CONFIG_CPU == PNX0101))
+ (CONFIG_CPU == PNX0101) || \
+ (CONFIG_CPU == S5L8700))
#define ICODE_ATTR __attribute__ ((section(".icode")))
#define ICONST_ATTR __attribute__ ((section(".irodata")))
#define IDATA_ATTR __attribute__ ((section(".idata")))
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h
new file mode 100644
index 0000000000..d0956c4f26
--- /dev/null
+++ b/firmware/export/s5l8700.h
@@ -0,0 +1,536 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id: S5L8700X.h 2008-03-24 A4 $
+ *
+ * Copyright (C) 2008 by Bart van Adrichem
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* Copied from imx31l.h */
+#define REG8_PTR_T volatile unsigned char *
+#define REG16_PTR_T volatile unsigned short *
+#define REG32_PTR_T volatile unsigned long *
+
+/* Base Adresses chapter in datasheet
+*/
+#define ARM_BASE_ADDR 0x38000000
+#define MIU_BASE_ADDR 0x38200000 //07
+#define IODMA_BASE_ADDR 0x38400000 //08
+#define USB_H11_BASE_ADDR 0x38600000 //22
+#define USB_F20_BASE_ADDR 0x38800000 //21
+#define USB_H20_BASE_ADDR 0x38A00000
+#define ATA_BASE_ADDR 0x38E00000 //28
+#define ADM_BASE_ADDR 0x39000000 //04
+#define LCD_CTRL_BASE_ADDR 0x39200000 //27
+#define ICU_BASE_ADDR 0x39C00000 //06
+#define EEC_BASE_ADDR 0x39E00000 //16
+#define APB_BRIDGE_BASE_ADDR 0x3C000000
+#define LCD_IF_BASE_ADDR 0x3C100000 //26
+#define FMC_BASE_ADDR 0x3C200000 //12
+#define MMC_SD_BASE_ADDR 0x3C300000 //13
+#define USB_PHY_BASE_ADDR 0x3C400000 //23
+#define CLCK_GEN_BASE_ADDR 0x3C500000 //05
+#define MS_BASE_ADDR 0x3C600000 //14
+#define TIMER_BASE_ADDR 0x3C700000 //11
+#define WDT_BASE_ADDR 0x3C800000 //09
+#define IIC_BASE_ADDR 0x3C900000 //18
+#define IIS_BASE_ADDR 0x3CA00000 //17
+#define SPDIF_OUT_BASE_ADDR 0x3CB00000 //15
+#define UART0_BASE_ADDR 0x3CC00000 //25
+#define UART1_BASE_ADDR 0x3CC08000 //25
+#define SPI_BASE_ADDR 0x3CD00000 //19
+#define ADC_BASE_ADDR 0x3CE00000 //20
+#define GPIO_BASE_ADDR 0x3CF00000 //24
+#define CHIP_ID_BASE_ADDR 0x3D100000 //29
+#define RTC_BASE_ADDR 0x3D200000 //10
+
+
+/* 04. CALMADM2E */
+//Following registers are mapped on IO Area in data memory area of Calm.
+//TODO: not sure if the following list is correct concerning the 'h' added to the adresses in the datasheet
+//#DEFINE 7BIT OFFSET OR IS REG16_PTR_T CORRECT??
+#define CALM_BASE 0x3F0000 //7 BITS LONG
+#define CALM_CONFIG0 (*(REG16_PTR_T)(ADM_BASE_+0x00))
+#define CALM_CONFIG1 (*(REG16_PTR_T)(ADM_BASE_+0x02))
+#define CALM_COMMUN (*(REG16_PTR_T)(ADM_BASE_+0x04))
+#define CALM_DDATA0 (*(REG16_PTR_T)(ADM_BASE_+0x06))
+#define CALM_DDATA1 (*(REG16_PTR_T)(ADM_BASE_+0x08))
+#define CALM_DDATA2 (*(REG16_PTR_T)(ADM_BASE_+0x0A))
+#define CALM_DDATA3 (*(REG16_PTR_T)(ADM_BASE_+0x0C))
+#define CALM_DDATA4 (*(REG16_PTR_T)(ADM_BASE_+0x0E))
+#define CALM_DDATA5 (*(REG16_PTR_T)(ADM_BASE_+0x10))
+#define CALM_DDATA6 (*(REG16_PTR_T)(ADM_BASE_+0x12))
+#define CALM_DDATA7 (*(REG16_PTR_T)(ADM_BASE_+0x14))
+#define CALM_UDATA0 (*(REG16_PTR_T)(ADM_BASE_+0x16))
+#define CALM_UDATA1 (*(REG16_PTR_T)(ADM_BASE_+0x18))
+#define CALM_UDATA2 (*(REG16_PTR_T)(ADM_BASE_+0x1A))
+#define CALM_UDATA3 (*(REG16_PTR_T)(ADM_BASE_+0x1C))
+#define CALM_UDATA4 (*(REG16_PTR_T)(ADM_BASE_+0x1E))
+#define CALM_UDATA5 (*(REG16_PTR_T)(ADM_BASE_+0x20))
+#define CALM_UDATA6 (*(REG16_PTR_T)(ADM_BASE_+0x22))
+#define CALM_UDATA7 (*(REG16_PTR_T)(ADM_BASE_+0x24))
+#define CALM_IBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x26))
+#define CALM_IBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x28))
+#define CALM_DBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x2A))
+#define CALM_DBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x2C))
+#define CALM_XBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x2E))
+#define CALM_XBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x30))
+#define CALM_YBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x32))
+#define CALM_YBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x34))
+#define CALM_S0BASE_H (*(REG16_PTR_T)(ADM_BASE_+0x36))
+#define CALM_SOBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x38))
+#define CALM_S1BASE_H (*(REG16_PTR_T)(ADM_BASE_+0x3A))
+#define CALM_S1BASE_L (*(REG16_PTR_T)(ADM_BASE_+0x3C))
+#define CALM_CACHECON (*(REG16_PTR_T)(ADM_BASE_+0x3E))
+#define CALM_CACHESTAT (*(REG16_PTR_T)(ADM_BASE_+0x40))
+#define CALM_SBFCON (*(REG16_PTR_T)(ADM_BASE_+0x42))
+#define CALM_SBFSTAT (*(REG16_PTR_T)(ADM_BASE_+0x44))
+#define CALM_SBL0OFF_H (*(REG16_PTR_T)(ADM_BASE_+0x46))
+#define CALM_SBL0OFF_L (*(REG16_PTR_T)(ADM_BASE_+0x48))
+#define CALM_SBL1OFF_H (*(REG16_PTR_T)(ADM_BASE_+0x4A))
+#define CALM_SBL1OFF_H (*(REG16_PTR_T)(ADM_BASE_+0x4C))
+#define CALM_SBL0BEGIN_H (*(REG16_PTR_T)(ADM_BASE_+0x4E))
+#define CALM_SBL0BEGIN_L (*(REG16_PTR_T)(ADM_BASE_+0x50))
+#define CALM_SBL1BEGIN_H (*(REG16_PTR_T)(ADM_BASE_+0x52))
+#define CALM_SBL1BEGIN_L (*(REG16_PTR_T)(ADM_BASE_+0x54))
+#define CALM_SBL0END_H (*(REG16_PTR_T)(ADM_BASE_+0x56))
+#define CALM_SBL0END_L (*(REG16_PTR_T)(ADM_BASE_+0x58))
+#define CALM_SBL0END_H (*(REG16_PTR_T)(ADM_BASE_+0x5A))
+#define CALM_SBL0END_L (*(REG16_PTR_T)(ADM_BASE_+0x5C))
+//Following registers are components of SFRS of the target system
+#define ADM_CONFIG (*(REG32_PTR_T)(ADM_BASE_ADDR+0x00))
+#define ADM_COMMUN (*(REG32_PTR_T)(ADM_BASE_ADDR+0x04))
+#define ADM_DDATA0 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x10))
+#define ADM_DDATA1 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x14))
+#define ADM_DDATA2 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x18))
+#define ADM_DDATA3 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x2C))
+#define ADM_DDATA4 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x20))
+#define ADM_DDATA5 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x24))
+#define ADM_DDATA6 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x28))
+#define ADM_DDATA7 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x2C))
+#define ADM_UDATA0 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x30))
+#define ADM_UDATA1 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x34))
+#define ADM_UDATA2 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x38))
+#define ADM_UDATA3 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x3C))
+#define ADM_UDATA4 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x40))
+#define ADM_UDATA5 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x44))
+#define ADM_UDATA6 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x48))
+#define ADM_UDATA7 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x4C))
+#define ADM_IBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x50))
+#define ADM_DBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x54))
+#define ADM_XBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x58))
+#define ADM_YBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x5C))
+#define ADM_S0BASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x60))
+#define ADM_S1BASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x64))
+
+/* 05. CLOCK & POWER MANAGEMENT */
+#define CLK_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x00))
+#define PLL_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x24))
+#define PLL0_PMS (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x04))
+#define PLL1_PMS (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x08))
+#define PLL0_CNT (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x14))
+#define PLL1_CNT (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x18))
+#define PLL_LOCK (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x20))
+#define PWR_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x28))
+#define PWR_MODE (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x2C))
+#define SWR_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x30))
+#define RST_SR (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x34))
+#define DSP_CLK_MD (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x38))
+#define CLK_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x3C))
+
+/* 06. INTERRUPT CONTROLLER UNIT */
+#define ICU_SRC_PND (*(REG32_PTR_T)(ICU_BASE_ADDR+0x00))
+#define ICU_INT_MOD (*(REG32_PTR_T)(ICU_BASE_ADDR+0x04))
+#define ICU_INT_MSK (*(REG32_PTR_T)(ICU_BASE_ADDR+0x08))
+#define ICU_PRIORITY (*(REG32_PTR_T)(ICU_BASE_ADDR+0x0C))
+#define ICU_INT_PND (*(REG32_PTR_T)(ICU_BASE_ADDR+0x10))
+#define ICU_INT_OFFSET (*(REG32_PTR_T)(ICU_BASE_ADDR+0x14))
+#define ICU_EINT_POL (*(REG32_PTR_T)(ICU_BASE_ADDR+0x18))
+#define ICU_EINT_PEND (*(REG32_PTR_T)(ICU_BASE_ADDR+0x1C))
+#define ICU_EINT_MSK (*(REG32_PTR_T)(ICU_BASE_ADDR+0x20))
+
+/* 07. MEMORY INTERFACE UNIT (MIU) */
+#define MIU_CON (*(REG32_PTR_T)(MIU_BASE_ADDR+0x00))
+#define MIU_COM (*(REG32_PTR_T)(MIU_BASE_ADDR+0x04))
+#define MIU_AREF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x08))
+#define MIU_MRS (*(REG32_PTR_T)(MIU_BASE_ADDR+0x0C))
+#define MIU_SDPARA (*(REG32_PTR_T)(MIU_BASE_ADDR+0x10))
+
+#define MIU_MEM_CONF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x020H)) // 9 BIT ADRESS IN DATASHEET????????
+#define MIU_USR_CMD (*(REG32_PTR_T)(MIU_BASE_ADDR+0x024H))
+#define MIU_AREF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x028H))
+#define MIU_MRS (*(REG32_PTR_T)(MIU_BASE_ADDR+0x02CH))
+#define MIU_DPARAM (*(REG32_PTR_T)(MIU_BASE_ADDR+0x030H))
+#define MIU_SMEM_CONF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x034H))
+#define MIU_S01PARA (*(REG32_PTR_T)(MIU_BASE_ADDR+0x038H))
+#define MIU_S23PARA (*(REG32_PTR_T)(MIU_BASE_ADDR+0x03CH))
+/* TODO:
+#define MIU_ORG
+#define MIU_DLYDQS
+#define MIU_DLYCLK
+#define MIU_DSS_SEL_B
+#define MIU_DSS_SEL_O
+#define MIU_PAD_DSS_SEL_NOR
+#define MIU_PAD_DSS_SEL_ATA
+#define MIU_SSTL2_PAD_ON
+*/
+
+/* 08. IODMA CONTROLLER */
+#define DMA_BASE0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x00))
+#define DMA_BASE1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x20))
+#define DMA_BASE2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x40))
+#define DMA_BASE3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x60))
+#define DMA_CNT0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x08))
+#define DMA_CNT1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x28))
+#define DMA_CNT2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x48))
+#define DMA_CNT3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x68))
+#define DMA_CADDR0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x0C))
+#define DMA_CADDR1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x2C))
+#define DMA_CADDR2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x4C))
+#define DMA_CADDR3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x6C))
+#define DMA_CON0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x04))
+#define DMA_CON1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x24))
+#define DMA_CON2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x44))
+#define DMA_CON3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x64))
+#define DMA_CTCNT0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x10))
+#define DMA_CTCNT1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x30))
+#define DMA_CTCNT2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x50))
+#define DMA_CTCNT3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x70))
+#define DMA_COM0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x14))
+#define DMA_COM1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x34))
+#define DMA_COM2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x54))
+#define DMA_COM3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x74))
+#define DMA_OFF1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x18))
+#define DMA_ALLST (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x0100))
+
+/* 10. REAL TIMER CLOCK (RTC) */
+#define RTC_CON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
+#define RTC_RST (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
+#define RTC_ALM_CON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
+#define RTC_ALM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
+#define RTC_ALM_MIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
+#define RTC_ALM_HOUR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
+#define RTC_ALM_DATE (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
+#define RTC_ALM_DAY (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
+#define RTC_ALM_MON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
+#define RTC_AML_YEAR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
+#define RTC_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x28))
+#define RTC_MIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x2C))
+#define RTC_HOUR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x30))
+#define RTC_DATE (*(REG32_PTR_T)(RTC_BASE_ADDR+0x34))
+#define RTC_DAY (*(REG32_PTR_T)(RTC_BASE_ADDR+0x38))
+#define RTC_MON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x3C))
+#define RTC_YEAR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x40))
+#define RTC_IM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x44))
+#define RTC_PEND (*(REG32_PTR_T)(RTC_BASE_ADDR+0x48))
+
+/* 09. WATCHDOG TIMER*/
+#define WDT_CON (*(REG32_PTR_T)(WDT_BASE_ADDR+0x00))
+#define WDT_CNT (*(REG32_PTR_T)(WDT_BASE_ADDR+0x04))
+
+/* 11. 16 BIT TIMER */
+#define TA_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x00))
+#define TA_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x04))
+#define TA_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x08))
+#define TA_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x0C))
+#define TA_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x10))
+#define TA_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x14))
+#define TB_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x20))
+#define TB_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x24))
+#define TB_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x28))
+#define TB_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x2C))
+#define TB_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x30))
+#define TB_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x34))
+#define TC_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x40))
+#define TC_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x44))
+#define TC_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x48))
+#define TC_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x4C))
+#define TC_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x50))
+#define TC_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x54))
+#define TD_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x60))
+#define TD_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x64))
+#define TD_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x68))
+#define TD_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x6C))
+#define TD_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x70))
+#define TD_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x74))
+
+/* 12. NAND FLASH CONTROLER */
+// TODO: FIFO
+#define FM_CTRL0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0000))
+#define FM_CTRL1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0004))
+#define FM_CMD (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0008))
+#define FM_ADR0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x000C))
+#define FM_ADR1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0010))
+#define FM_ADR2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0014))
+#define FM_ADR3 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0018))
+#define FM_ADR4 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x001C))
+#define FM_ADR5 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0020))
+#define FM_ADR6 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0024))
+#define FM_ADR7 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0028))
+#define FM_ANUM (*(REG32_PTR_T)(FMC_BASE_ADDR+0x002C))
+#define FM_DNUM (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0030))
+#define FM_DATAW0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0034))
+#define FM_DATAW1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0038))
+#define FM_DATAW2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x003C))
+#define FM_DATAW3 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0040))
+#define FM_CSTAT (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0048))
+#define FM_SYND0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x004C))
+#define FM_SYND1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0050))
+#define FM_SYND2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0054))
+#define FM_SYND3 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0058))
+#define FM_SYND4 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x005C))
+#define FM_SYND5 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0060))
+#define FM_SYND6 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0064))
+#define FM_SYND7 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0068))
+#define FM_FIFO (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0080)) // UNTILL (INCLUDING) 0x00FC <--
+#define RS_CTRL (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0100))
+#define RS_PAITY0-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0110))
+#define RS_PAITY0-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0114))
+#define RS_PAITY0-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0118))
+#define RS_PAITY1-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0120))
+#define RS_PAITY1-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0124))
+#define RS_PAITY1-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0128))
+#define RS_PAITY2-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0130))
+#define RS_PAITY2-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0134))
+#define RS_PAITY2-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0138))
+#define RS_PAITY3-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0140))
+#define RS_PAITY3-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0144))
+#define RS_PAITY3-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0148))
+#define RS_SYND0-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0150))
+#define RS_SYND0-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0154))
+#define RS_SYND0-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0158))
+#define RS_SYND1-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0160))
+#define RS_SYND1-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0164))
+#define RS_SYND1-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0168))
+#define RS_SYND2-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0170))
+#define RS_SYND2-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0174))
+#define RS_SYND2-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0178))
+#define RS_SYND3-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0180))
+#define RS_SYND3-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0184))
+#define RS_SYND3-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0188))
+#define FLAG_SYND (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0190))
+
+/* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */
+// TODO
+
+/* 14. MEMORY STICK HOST CONTROLLER */
+//TODO
+
+/* 15. SPDIF TRANSMITTER (SPDIFOUT) */
+#define SPD_CLKCON (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x00))
+#define SPD_CON (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x04))
+#define SPD_BSTAS (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x08))
+#define SPD_CSTAS (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x0C))
+#define SPD_DAT (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x10))
+#define SPD_CNT (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x14))
+
+/* 16. REED-SOLOMON ECC CODEC */
+//TODO
+
+/* 17. IIS Tx/Rx INTERFACE */
+#define I2S_CLK_CON (*(REG32_PTR_T)(IIS_BASE_ADDR+0x00))
+#define I2S_TX_CON (*(REG32_PTR_T)(IIS_BASE_ADDR+0x04))
+#define I2S_TX_COM (*(REG32_PTR_T)(IIS_BASE_ADDR+0x08))
+#define I2S_TX_DB (*(REG32_PTR_T)(IIS_BASE_ADDR+0x10))
+#define I2S_RX_CON (*(REG32_PTR_T)(IIS_BASE_ADDR+0x30))
+#define I2S_RX_COM (*(REG32_PTR_T)(IIS_BASE_ADDR+0x34))
+#define I2S_RX_DB (*(REG32_PTR_T)(IIS_BASE_ADDR+0x38))
+#define I2S_STATUS (*(REG32_PTR_T)(IIS_BASE_ADDR+0x3C))
+
+/* 18. IIC BUS INTERFACE */
+#define IIC_CON (*(REG32_PTR_T)(IIC_BASE_ADDR+0x00))
+#define IIC_STST (*(REG32_PTR_T)(IIC_BASE_ADDR+0x04))
+#define IIC_ADD (*(REG32_PTR_T)(IIC_BASE_ADDR+0x08))
+#define IIC_DS (*(REG32_PTR_T)(IIC_BASE_ADDR+0x0C))
+
+/* 19. SPI (SERIAL PERHIPERAL INTERFACE) */
+#define SP_CLK_CON (*(REG32_PTR_T)(SPI_BASE_ADDR+0x00))
+#define SP_CON (*(REG32_PTR_T)(SPI_BASE_ADDR+0x04))
+#define SP_STA (*(REG32_PTR_T)(SPI_BASE_ADDR+0x08))
+#define SP_PIN (*(REG32_PTR_T)(SPI_BASE_ADDR+0x0C))
+#define SP_TDAT (*(REG32_PTR_T)(SPI_BASE_ADDR+0x10))
+#define SP_RDAT (*(REG32_PTR_T)(SPI_BASE_ADDR+0x14))
+#define SP_PRE (*(REG32_PTR_T)(SPI_BASE_ADDR+0x18))
+
+/* 20. ADC CONTROLLER */
+#define ADC_CON (*(REG32_PTR_T)(ADC_BASE_ADDR+0x00))
+#define ADC_TSC (*(REG32_PTR_T)(ADC_BASE_ADDR+0x04))
+#define ADC_DLY (*(REG32_PTR_T)(ADC_BASE_ADDR+0x08))
+#define ADC_DAT0 (*(REG32_PTR_T)(ADC_BASE_ADDR+0x0C))
+#define ADC_DAT1 (*(REG32_PTR_T)(ADC_BASE_ADDR+0x10))
+#define ADC_UPDN (*(REG32_PTR_T)(ADC_BASE_ADDR+0x14))
+
+/* 21. USB 2.0 FUNCTION CONTROLER SPECIAL REGISTER */
+#define USB2_IN (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x00))
+#define USB2_EIR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x04))
+#define USB2_EIER (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x08))
+#define USB2_FAR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x0C))
+#define USB2_FNR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x10))
+#define USB2_EDR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x14))
+#define USB2_TR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x18))
+#define USB2_SSR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x1C))
+#define USB2_SCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x20))
+#define USB2_EP0SR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x24))
+#define USB2_EP0CR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x28))
+#define USB2_EP0BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x60))
+#define USB2_EP1BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x64))
+#define USB2_EP2BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x68))
+#define USB2_EP3BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x6C))
+#define USB2_EP4BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x70))
+#define USB2_EP5BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x74))
+#define USB2_EP6BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x78))
+#define USB2_ESR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x2C))
+#define USB2_ECR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x30))
+#define USB2_BRCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x34))
+#define USB2_BSCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x38))
+#define USB2_MPR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x3C))
+#define USB2_MCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x40))
+#define USB2_MTCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x44))
+#define USB2_MFCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x48))
+#define USB2_MTTCR1 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x4C))
+#define USB2_MTTCR2 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x50))
+#define USB2_MICR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x84))
+#define USB2_MBAR1 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x88))
+#define USB2_MBAR2 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x8C))
+#define USB2_MCAR1 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x94))
+#define USB2_MCAR2 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x98))
+
+/* 22. USB 1.1 HOST CONTROLER SPECIAL REGISTER */
+#define HC_REV (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x00))
+#define HC_CON (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x04))
+#define HC_COMSTAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x08))
+#define HC_INTSTAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x0C))
+#define HC_INTEN (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x10))
+#define HC_INTDIS (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x14))
+#define HC_HCCA (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x18))
+#define HC_PCED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x1C))
+#define HC_CHED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x20))
+#define HC_CCED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x24))
+#define HC_BHED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x28))
+#define HC_BCED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x2C))
+#define HC_DH (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x30))
+#define HC_FMI (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x34))
+#define HC_FMR (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x38))
+#define HC_FMNR (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x3C))
+#define HC_PS (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x40))
+#define HC_LSTRESH (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x44))
+#define HC_RHSECA (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x48))
+#define HC_RHDESB (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x4C))
+#define HC_STAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x50))
+#define HC_PSTAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x54))
+
+/* 23. USB 2.0 PHY CONTROL */
+#define PHY_CTRL (*(REG32_PTR_T)(USB_PHY_BASE_ADDR+0x00))
+#define ULCK_CON (*(REG32_PTR_T)(USB_PHY_BASE_ADDR+0x04))
+#define URST_CON (*(REG32_PTR_T)(USB_PHY_BASE_ADDR+0x08))
+
+/* 24. GPIO PORT CONTROLL */
+#define GPIO_PCON0 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x00))
+#define GPIO_PDAT0 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x04))
+#define GPIO_PCON1 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x10))
+#define GPIO_PDAT1 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x14))
+#define GPIO_PCON2 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x20))
+#define GPIO_PDAT2 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x24))
+#define GPIO_PCON3 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x30))
+#define GPIO_PDAT3 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x34))
+#define GPIO_PCON4 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x40))
+#define GPIO_PDAT4 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x44))
+#define GPIO_PCON5 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x50))
+#define GPIO_PDAT5 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x54))
+#define GPIO_PCON6 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x60))
+#define GPIO_PDAT6 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x64))
+#define GPIO_PCON7 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x70))
+#define GPIO_PDAT7 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x74))
+#define GPIO_PCON10 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xA0))
+#define GPIO_PDAT10 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xA4))
+#define GPIO_PCON11 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xF8))
+#define GPIO_PDAT11 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xFC))
+#define GPIO_PCON_ASRAM (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xF0))
+#define GPIO_PCON_SDRAM (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xF4))
+
+/* 25. UART */
+#define UART0_LCON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x00))
+#define UART0_CON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x04))
+#define UART0_FCON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x08))
+#define UART0_MCON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x0C))
+#define UART0_TRSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x10))
+#define UART0_ERSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x14))
+#define UART0_FSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x18))
+#define UART0_MSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x1C))
+#define UART0_TXH (*(REG32_PTR_T)(UART0_BASE_ADDR+0x10))
+#define UART0_RXH (*(REG32_PTR_T)(UART0_BASE_ADDR+0x24))
+#define UART0_BRDIV (*(REG32_PTR_T)(UART0_BASE_ADDR+0x28))
+
+#define UART1_LCON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
+#define UART1_CON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x04))
+#define UART1_FCON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x08))
+#define UART1_MCON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x0C))
+#define UART1_TRSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x10))
+#define UART1_ERSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x14))
+#define UART1_FSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x18))
+#define UART1_MSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x1C))
+#define UART1_TXH (*(REG32_PTR_T)(UART1_BASE_ADDR+0x10))
+#define UART1_RXH (*(REG32_PTR_T)(UART1_BASE_ADDR+0x24))
+#define UART1_BRDIV (*(REG32_PTR_T)(UART1_BASE_ADDR+0x28))
+
+/* 26. LCD INTERFACE CONTROLLER */
+// TODO: WDATA
+#define LCD_CON (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x00))
+#define LCD_WCMD (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x04))
+#define LCD_RCMD (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x0C))
+#define LCD_RDATA (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x10))
+#define LCD_DBUFF (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x14))
+#define LCD_INTCON (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x18))
+#define LCD_STATUS (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x1C))
+#define LCD_PHTIME (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x20))
+#define LCD_RST_TIME (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x24))
+#define LCD_DRV_RST (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x28))
+#define LCD_WDATA (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x40)) // UNTILL (INCLUDING) 0x5C <--
+
+/* 27. CLCD CONTROLLER */
+#define CLCD_CON1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x00))
+#define CLCD_CON2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x04))
+#define CLCD_TCON1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x08))
+#define CLCD_TCON2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x0C))
+#define CLCD_TCON3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x10))
+#define CLCD_OSD1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x14))
+#define CLCD_OSD2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x18))
+#define CLCD_OSD3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x1C))
+#define CLCD_B1SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x20))
+#define CLCD_B2SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x24))
+#define CLCD_F1SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x28))
+#define CLCD_F2SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x2C))
+#define CLCD_B1SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x30))
+#define CLCD_B2SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x34))
+#define CLCD_F1SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x38))
+#define CLCD_F2SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x3C))
+#define CLCD_B1SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x40))
+#define CLCD_B2SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x44))
+#define CLCD_F1SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x48))
+#define CLCD_F2SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x4C))
+#define CLCD_INTCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x50))
+#define CLCD_KEYCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x54))
+#define CLCD_KEYVAL (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x58))
+#define CLCD_BGCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x5C))
+#define CLCD_FGCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x60))
+#define CLCD_DITHCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x64))
+
+/* 28. ATA CONTROLLER */
+// TODO
+
+/* 29. CHIP ID */
+
+#define REG_ONE (*(REG32_PTR_T)(CHIP_ID_BASE_ADDR+0x00))
+#define REG_TWO (*(REG32_PTR_T)(CHIP_ID_BASE_ADDR+0x04))
+
diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h
new file mode 100644
index 0000000000..c0a069ac0c
--- /dev/null
+++ b/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h
@@ -0,0 +1,33 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Barry Wardell
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef _ADC_TARGET_H_
+#define _ADC_TARGET_H_
+
+/* only two channels used by the Gigabeat */
+#define NUM_ADC_CHANNELS 1
+
+#define ADC_UNKNOWN_1 0
+#define ADC_UNKNOWN_2 1
+#define ADC_BATTERY 2
+#define ADC_UNKNOWN_4 3
+
+#define ADC_UNREG_POWER ADC_BATTERY /* For compatibility */
+#define ADC_READ_ERROR 0xFFFF
+
+#endif
diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h
new file mode 100644
index 0000000000..7d0d7a1c4d
--- /dev/null
+++ b/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h
@@ -0,0 +1,52 @@
+/***************************************************************************
+ * __________ __ ___.
+ * Open \______ \ ____ ____ | | _\_ |__ _______ ___
+ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
+ * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
+ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
+ * \/ \/ \/ \/ \/
+ * $Id$
+ *
+ * Copyright (C) 2006 by Linus Nielsen Feltzing
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef _BUTTON_TARGET_H_
+#define _BUTTON_TARGET_H_
+
+#include <stdbool.h>
+#include "config.h"
+
+#define HAS_BUTTON_HOLD
+
+bool button_hold(void);
+void button_init_device(void);
+int button_read_device(void);
+
+/* Toshiba Gigabeat specific button codes */
+
+#define BUTTON_LEFT 0x00000001
+#define BUTTON_RIGHT 0x00000002
+#define BUTTON_UP 0x00000004
+#define BUTTON_DOWN 0x00000008
+
+#define BUTTON_SELECT 0x00000010
+
+#define BUTTON_MENU 0x00000020
+#define BUTTON_PLAY 0x00000040
+
+
+#define BUTTON_MAIN (BUTTON_MENU|BUTTON_LEFT|BUTTON_RIGHT\
+ |BUTTON_UP|BUTTON_DOWN|BUTTON_SELECT|BUTTON_PLAY)
+
+#define BUTTON_REMOTE 0
+
+#define POWEROFF_BUTTON BUTTON_PLAY
+#define POWEROFF_COUNT 10
+
+#endif /* _BUTTON_TARGET_H_ */
diff --git a/tools/configure b/tools/configure
index d81f0e2fe0..51707e970b 100755
--- a/tools/configure
+++ b/tools/configure
@@ -626,8 +626,9 @@ cat <<EOF
==Tatung== ==Olympus== ==Logik==
60) Elio TPJ-1022 70) M:Robe 500 80) DAX 1GB MP3/DAB
71) M:Robe 100
- ==Creative==
- 90) Zen Vision:M
+
+ ==Creative== ==Meizu==
+ 90) Zen Vision:M 100) M6SL
EOF
buildfor=`input`;
@@ -1521,6 +1522,27 @@ EOF
t_model="tpj1022"
;;
+ 100|meizum6sl)
+ target_id=20
+ modelname="meizum6sl"
+ target="-DMEIZU_M6SL"
+ memory=16 # always
+ arm9tdmicc
+ tool="cp"
+ bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
+ bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
+ output="rockbox.meizu"
+ appextra="recorder:gui"
+ plugins="no" #FIXME
+ swcodec="yes"
+ toolset=$genericbitmaptools
+ boottool="cp"
+ bootoutput="rockboot.ebn"
+ # architecture, manufacturer and model for the target-tree build
+ t_cpu="arm"
+ t_manufacturer="s5l8700"
+ t_model="meizu-m6sl"
+ ;;
*)
echo "Please select a supported target platform!"
exit
diff --git a/tools/makesrc.inc b/tools/makesrc.inc
index 846df8cb9e..be9c34e16b 100644
--- a/tools/makesrc.inc
+++ b/tools/makesrc.inc
@@ -11,4 +11,5 @@
SRC := $(shell cat SOURCES | $(CC) -DMEMORYSIZE=$(MEMORYSIZE) $(INCLUDES) \
$(TARGET) $(DEFINES) $(EXTRA_DEFINES) -E -P -include "config.h" - 2>/dev/null \
-| grep -v "^\#")
+| grep -v "^\#" | xargs ls)
+#| grep -v "^\#")
diff --git a/uisimulator/sdl/button.c b/uisimulator/sdl/button.c
index 03f7dc1e96..78be6700ec 100644
--- a/uisimulator/sdl/button.c
+++ b/uisimulator/sdl/button.c
@@ -772,6 +772,37 @@ void button_event(int key, bool pressed)
case SDLK_KP9:
new_btn = BUTTON_MENU;
break;
+
+#elif CONFIG_KEYPAD == MEIZU_M6SL_PAD
+ case SDLK_KP4:
+ case SDLK_LEFT:
+ new_btn = BUTTON_LEFT;
+ break;
+ case SDLK_KP6:
+ case SDLK_RIGHT:
+ new_btn = BUTTON_RIGHT;
+ break;
+ case SDLK_KP8:
+ case SDLK_UP:
+ new_btn = BUTTON_UP;
+ break;
+ case SDLK_KP2:
+ case SDLK_DOWN:
+ new_btn = BUTTON_DOWN;
+ break;
+ case SDLK_KP_ENTER:
+ case SDLK_RETURN:
+ case SDLK_a:
+ new_btn = BUTTON_PLAY;
+ break;
+ case SDLK_KP5:
+ case SDLK_SPACE:
+ new_btn = BUTTON_SELECT;
+ break;
+ case SDLK_KP_PERIOD:
+ case SDLK_INSERT:
+ new_btn = BUTTON_MENU;
+ break;
#else
#error No keymap defined!
#endif /* CONFIG_KEYPAD */
diff --git a/uisimulator/sdl/uisdl.h b/uisimulator/sdl/uisdl.h
index 37989a682b..890c6d0638 100644
--- a/uisimulator/sdl/uisdl.h
+++ b/uisimulator/sdl/uisdl.h
@@ -374,6 +374,19 @@
#define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */
#define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */
+#elif defined(MEIZU_M6SL)
+#define UI_TITLE "Meizu M6"
+#define UI_WIDTH 512 /* width of GUI window */
+#define UI_HEIGHT 322 /* height of GUI window */
+#define UI_LCD_POSX 39 /* x position of lcd */
+#define UI_LCD_POSY 38 /* y position of lcd */
+#define UI_LCD_WIDTH 320
+#define UI_LCD_HEIGHT 240
+#define UI_LCD_BGCOLOR 32, 32, 32 /* bkgnd color of LCD (no backlight) */
+#define UI_LCD_BGCOLORLIGHT 192, 192, 192 /* bkgnd color of LCD (backlight) */
+#define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */
+#define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */
+
#endif
extern SDL_Surface *gui_surface;
extern bool background; /* True if the background image is enabled */