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authorAmaury Pouly <amaury.pouly@gmail.com>2013-06-17 00:28:19 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2013-06-17 00:29:26 +0200
commitdafc359fad4c6b8d4964bafcf6a1f61547c6e6d8 (patch)
treec7ea099e1806de78815c7ddc42c47ad26d92195e
parent8d7cc320b720c088a8ccb7e33ed85a7de0b89aeb (diff)
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imx233: fix system for stmp3600 and stmp3700
Change-Id: I2b425b56358ed21269beae27a4afb490939b7f9d
-rw-r--r--firmware/target/arm/imx233/system-imx233.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c
index dcf3b82408..9a8ff61af0 100644
--- a/firmware/target/arm/imx233/system-imx233.c
+++ b/firmware/target/arm/imx233/system-imx233.c
@@ -30,7 +30,9 @@
#include "dma-imx233.h"
#include "ssp-imx233.h"
#include "i2c-imx233.h"
+#if IMX233_SUBTARGET >= 3700
#include "dcp-imx233.h"
+#endif
#include "pwm-imx233.h"
#include "icoll-imx233.h"
#include "lradc-imx233.h"
@@ -44,7 +46,11 @@
void imx233_chip_reset(void)
{
+#if IMX233_SUBTARGET >= 3700
HW_CLKCTRL_RESET = BM_CLKCTRL_RESET_CHIP;
+#else
+ HW_POWER_RESET = BF_OR2(POWER_RESET, UNLOCK_V(KEY), RST_DIG(1));
+#endif
}
void system_reboot(void)
@@ -109,7 +115,9 @@ void system_init(void)
* Make sure IO clock is running at expected speed */
imx233_clkctrl_init();
imx233_clkctrl_enable(CLK_PLL, true);
+#if IMX233_SUBTARGET >= 3700
imx233_clkctrl_set_frac_div(CLK_IO, 18); // clk_io@clk_pll
+#endif
imx233_rtc_init();
imx233_icoll_init();
@@ -117,7 +125,9 @@ void system_init(void)
imx233_timrot_init();
imx233_dma_init();
imx233_ssp_init();
+#if IMX233_SUBTARGET >= 3700
imx233_dcp_init();
+#endif
imx233_pwm_init();
imx233_lradc_init();
imx233_power_init();
@@ -166,8 +176,13 @@ void udelay(unsigned us)
void imx233_digctl_set_arm_cache_timings(unsigned timings)
{
+#if IMX233_SUBTARGET >= 3780
HW_DIGCTL_ARMCACHE = BF_OR5(DIGCTL_ARMCACHE, ITAG_SS(timings),
DTAG_SS(timings), CACHE_SS(timings), DRTY_SS(timings), VALID_SS(timings));
+#else
+ HW_DIGCTL_ARMCACHE = BF_OR3(DIGCTL_ARMCACHE, ITAG_SS(timings),
+ DTAG_SS(timings), CACHE_SS(timings));
+#endif
}
#ifdef HAVE_ADJUSTABLE_CPU_FREQ