Improvements to mini2440 audio; change CPU freq to 406MHz

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23495 a1c6a512-1295-4272-9138-f99709370657

6 files changed, 20 insertions, 21 deletions

diff --git a/firmware/drivers/audio/uda1341.c b/firmware/drivers/audio/uda1341.c
index 0171169942..17d0475f2b 100644
--- a/firmware/drivers/audio/uda1341.c
+++ b/firmware/drivers/audio/uda1341.c
@@ -170,7 +170,6 @@ static void udacodec_reset(void)
 /* [reserved, master clock rate] */
 static const unsigned char uda_freq_parms[HW_NUM_FREQ][2] =
 {
-    [HW_FREQ_64] = { 0, UDA_SYSCLK_256FS },
     [HW_FREQ_44] = { 0, UDA_SYSCLK_384FS },
     [HW_FREQ_22] = { 0, UDA_SYSCLK_256FS },
     [HW_FREQ_11] = { 0, UDA_SYSCLK_256FS },
diff --git a/firmware/export/config-mini2440.h b/firmware/export/config-mini2440.h
index a477236d19..f08d4875ef 100644
--- a/firmware/export/config-mini2440.h
+++ b/firmware/export/config-mini2440.h
@@ -84,11 +84,8 @@
 
 /* Define DAC/Codec */
 #define HAVE_UDA1341
-/* ... tone controls, use the software ones */
-#define HAVE_SW_TONE_CONTROLS
 
-#define HW_SAMPR_CAPS (SAMPR_CAP_64 | SAMPR_CAP_44 | SAMPR_CAP_22 | \
-                       SAMPR_CAP_11)
+#define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11)
 
 /* Battery */
 #define BATTERY_CAPACITY_DEFAULT 1100   /* default battery capacity */
@@ -130,7 +127,7 @@
 #define CONFIG_CPU S3C2440
 
 /* Define this to the CPU frequency */
-#define CPU_FREQ      405000000
+#define CPU_FREQ      406000000
 #define MCK_FREQ   (CPU_FREQ/4)
 #define SLOW_CLOCK        32768
 
diff --git a/firmware/sound.c b/firmware/sound.c
index b327e3839c..bd85ad17ce 100644
--- a/firmware/sound.c
+++ b/firmware/sound.c
@@ -205,7 +205,7 @@ static void set_prescaled_volume(void)
 #if defined(HAVE_SW_TONE_CONTROLS) || !(defined(HAVE_WM8975) \
     || defined(HAVE_WM8711) || defined(HAVE_WM8721) || defined(HAVE_WM8731) \
     || defined(HAVE_WM8751) || defined(HAVE_WM8758) || defined(HAVE_WM8985)) \
-    || defined(HAVE_TSC2100)
+    || defined(HAVE_TSC2100) || defined(HAVE_UDA1341)
 
     prescale = MAX(current_bass, current_treble);
     if (prescale < 0)
@@ -250,7 +250,7 @@ static void set_prescaled_volume(void)
 #elif defined(HAVE_UDA1380) || defined(HAVE_WM8975) || defined(HAVE_WM8758) \
    || defined(HAVE_WM8711) || defined(HAVE_WM8721) || defined(HAVE_WM8731) \
    || defined(HAVE_WM8751) || defined(HAVE_AS3514) || defined(HAVE_TSC2100) \
-   || defined(HAVE_AK4537)
+   || defined(HAVE_AK4537) || defined(HAVE_UDA1341)
     audiohw_set_master_vol(tenthdb2master(l), tenthdb2master(r));
 #if defined(HAVE_WM8975) || defined(HAVE_WM8758) \
 	|| (defined(HAVE_WM8751) && !defined(MROBE_100)) || defined(HAVE_WM8985)
diff --git a/firmware/target/arm/s3c2440/crt0.S b/firmware/target/arm/s3c2440/crt0.S
index 3110c88be0..2188bc07da 100644
--- a/firmware/target/arm/s3c2440/crt0.S
+++ b/firmware/target/arm/s3c2440/crt0.S
@@ -138,13 +138,11 @@
 
 /* For Mini2440 board or compatible */
 /* Clock and Power Management setup values */
+/* NB: clock settings must match values in s3c2440/system-target.h */
 #define VAL_CLKDIV    0x5         /* HCLK = FCLK/4, PCLK = HCLK/2 */
 #define VAL_UPLLCON   0x00038022  /* UCLK = 48 MHz */
-#define VAL_MPLLCON   0x0007F021  /* FCLK = 405 MHz */
+#define VAL_MPLLCON   0x000C3041  /* FCLK = 406 MHz */
 
-#define FCLK 405000000
-#define HCLK (FCLK/4)   /* = 101,250,000 */
-#define PCLK (HCLK/2)   /* =  50,625,000 */
 
 /* Memory Controller setup */
 #define VAL_BWSCON    0x22111112    
diff --git a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
index 9c898f88d9..7779639c8f 100644
--- a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
+++ b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c
@@ -48,7 +48,6 @@ static struct
 /* [prescaler, master clock rate] */
 static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
 {
-    [HW_FREQ_64] = { 2, IISMOD_MASTER_CLOCK_256FS },
     [HW_FREQ_44] = { 2, IISMOD_MASTER_CLOCK_384FS },
     [HW_FREQ_22] = { 8, IISMOD_MASTER_CLOCK_256FS },
     [HW_FREQ_11] = { 17, IISMOD_MASTER_CLOCK_256FS },
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h
index cf3db301eb..7bb49c01c4 100644
--- a/firmware/target/arm/s3c2440/system-target.h
+++ b/firmware/target/arm/s3c2440/system-target.h
@@ -24,13 +24,18 @@
 #include "system-arm.h"

 #include "mmu-arm.h"

 

-/* TODO: Needs checking/porting */

+/* NB: These values must match the register settings in s3c2440/crt0.S */
 

 #ifdef GIGABEAT_F

     #define CPUFREQ_DEFAULT 98784000

     #define CPUFREQ_NORMAL  98784000

     #define CPUFREQ_MAX    296352000

 

+    /* Uses 1:3:6 */
+    #define FCLK    CPUFREQ_MAX
+    #define HCLK    (FCLK/3)   /* = 98,784,000 */
+    #define PCLK    (HCLK/2)   /* = 49,392,000 */
+
     #ifdef BOOTLOADER

         /* All addresses within rockbox are in IRAM in the bootloader so

            are therefore uncached */

@@ -42,17 +47,18 @@
 

 #elif defined(MINI2440)

 

-    #define CPUFREQ_DEFAULT 101250000

-    #define CPUFREQ_NORMAL  101250000

-    #define CPUFREQ_MAX     405000000

+    /* Uses 1:4:8 */
+    #define FCLK 406000000
+    #define HCLK (FCLK/4)   /* = 101,250,000 */
+    #define PCLK (HCLK/2)   /* =  50,625,000 */
+

+    #define CPUFREQ_DEFAULT FCLK    /* 406 MHz */
+    #define CPUFREQ_NORMAL  (FCLK/4)/* 101.25 MHz */   
+    #define CPUFREQ_MAX     FCLK    /* 406 MHz */
     

     #define UNCACHED_BASE_ADDR 0x30000000

     #define UNCACHED_ADDR(a)  ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))

 

-    #define FCLK 405000000

-    #define HCLK (FCLK/4)   /* = 101,250,000 */

-    #define PCLK (HCLK/2)   /* =  50,625,000 */

-    

 #else

     #error Unknown target

 #endif