S5L8702: Move I/O addresses from drivers to SoC definitions

No changes to ipod6g binaries (normal + bootloader).

Change-Id: Iaad0d0de16176ff94b1f67aa3fdb7c6cc063b27e

4 files changed, 142 insertions, 133 deletions

diff --git a/firmware/export/s5l87xx.h b/firmware/export/s5l87xx.h
index dea25f9c02..a6555d16ef 100644
--- a/firmware/export/s5l87xx.h
+++ b/firmware/export/s5l87xx.h
@@ -58,6 +58,9 @@
 #define TTB_BASE_ADDR   (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
 #endif
 
+/* Base address of the memory-mapped I/O */
+#define IO_BASE 0x38000000
+
 /* 04. CALMADM2E */
 
 /* Following registers are mapped on IO Area in data memory area of Calm. */
@@ -1219,6 +1222,7 @@
 #define PDAT6                   PDAT(6)      /* The data register for port 6 */
 #define PCON7                   PCON(7)      /* Configures the pins of port 7 */
 #define PDAT7                   PDAT(7)      /* The data register for port 7 */
+#define PUNK8                   PUNB(8)      /* Unknown thing for port 8 */
 #define PCON10                  PCON(10)     /* Configures the pins of port 10 */
 #define PDAT10                  PDAT(10)     /* The data register for port 10 */
 #define PCON11                  PCON(11)     /* Configures the pins of port 11 */
@@ -1241,6 +1245,7 @@
 #elif CONFIG_CPU==S5L8702
 #define GPIO_N_GROUPS 16
 #define GPIOCMD       (*((REG32_PTR_T)(GPIO_BASE + 0x200)))
+#define GPIOUNK380    (*((REG32_PTR_T)(GPIO_BASE + 0x380)))
 #elif CONFIG_CPU==S5L8720
 #define GPIO_N_GROUPS 15
 #define GPIOCMD       (*((REG32_PTR_T)(GPIO_BASE + 0x1e0)))
@@ -1722,4 +1727,132 @@ Information for them was gathered solely by reverse-engineering Apple's firmware
 #define IRQ_EXT6        33
 #endif
 
+#if CONFIG_CPU == S5L8702
+/* Something related to the ATA controller, needed for power up */
+#define ATA_UNKNOWN_BASE 0x38a00000
+
+#define ATA_UNKNOWN (*((REG32_PTR_T)(ATA_UNKNOWN_BASE)))
+#endif
+
+#if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
+/*
+ * s5l8702 External (GPIO) Interrupt Controller
+ *
+ * 7 groups of 32 interrupts, GPIO pins are seen as 'wired'
+ * to groups 6..3 in reverse order.
+ * On group 3, last four bits are dissbled (GPIO 124..127).
+ * All bits in groups 1 and 2 are disabled (not used).
+ * On group 0, all bits are masked except bits 0 and 2:
+ *  bit 0: if unmasked, EINT6 is generated when ALVTCNT
+ *         reachs ALVTEND.
+ *  bit 2: if unmasked, EINT6 is generated when USB cable
+ *         is plugged and/or(TBC) unplugged.
+ *
+ * EIC_GROUP0..6 are connected to EINT6..0 of the VIC.
+ */
+#define EIC_N_GROUPS    7
+
+/* get EIC group and bit for a given GPIO port */
+#define EIC_GROUP(n)    (6 - ((n) >> 5))
+#define EIC_INDEX(n)    ((0x18 - ((n) & 0x18)) | ((n) & 0x7))
+
+/* SoC EINTs uses these 'gpio' numbers */
+#define GPIO_EINT_USB       0xd8
+#define GPIO_EINT_ALIVE     0xda
+
+/* probably a part of the system controller */
+#if CONFIG_CPU == S5L8702
+#define EIC_BASE 0x39a00000
+#elif CONFIG_CPU == S5L8720
+#define EIC_BASE 0x39700000
+#endif
+
+#define EIC_INTLEVEL(g) (*((REG32_PTR_T)(EIC_BASE + 0x80 + 4*(g))))
+#define EIC_INTSTAT(g)  (*((REG32_PTR_T)(EIC_BASE + 0xA0 + 4*(g))))
+#define EIC_INTEN(g)    (*((REG32_PTR_T)(EIC_BASE + 0xC0 + 4*(g))))
+#define EIC_INTTYPE(g)  (*((REG32_PTR_T)(EIC_BASE + 0xE0 + 4*(g))))
+
+#define EIC_INTLEVEL_LOW    0
+#define EIC_INTLEVEL_HIGH   1
+
+#define EIC_INTTYPE_EDGE    0
+#define EIC_INTTYPE_LEVEL   1
+#endif
+
+#if CONFIG_CPU == S5L8702
+/*
+ * This is very preliminary work in progress, ATM this region is called
+ * system 'alive' because it seems there are similiarities when mixing
+ * concepts from:
+ *  - s3c2440 datasheet (figure 7-12, Sleep mode) and
+ *  - ARM-DDI-0287B (2.1.8 System Mode Control, Sleep an Doze modes)
+ *
+ * Known components:
+ * - independent clocking
+ * - 32-bit timer
+ * - level/edge configurable interrupt controller
+ *
+ *
+ *        OSCSEL
+ *          |\    CKSEL
+ *  OSC0 -->| |    |\
+ *          | |--->| |     _________             ___________
+ *  OSC1 -->| |    | |    |         | SClk      |           |
+ *          |/     | |--->| 1/CKDIV |---------->| 1/ALVTDIV |--> Timer
+ *                 | |    |_________|       |   |___________|    counter
+ *  PClk --------->| |                      |    ___________
+ *                 |/                       |   |           |
+ *                                          +-->| 1/UNKDIV  |--> Unknown
+ *                                              |___________|
+ */
+#define SYSALV_BASE 0x39a00000
+
+#define ALVCON          (*((REG32_PTR_T)(SYSALV_BASE)))
+#define ALVUNK4         (*((REG32_PTR_T)(SYSALV_BASE + 0x4)))
+#define ALVUNK100       (*((REG32_PTR_T)(SYSALV_BASE + 0x100)))
+#define ALVUNK104       (*((REG32_PTR_T)(SYSALV_BASE + 0x104)))
+
+
+/*
+ * System Alive control register
+ */
+#define ALVCON_CKSEL_BIT    (1 << 25)  /* 0 -> S5L8702_OSCx, 1 -> PClk */
+#define ALVCON_CKDIVEN_BIT  (1 << 24)  /* 0 -> CK divider Off, 1 -> On */
+#define ALVCON_CKDIV_POS    20         /* real_val = reg_val+1 */
+#define ALVCON_CKDIV_MSK    0xf
+
+/* UNKDIV: real_val = reg_val+1 (TBC), valid reg_val=0,1,2 */
+/* experimental: for registers in this region, read/write speed is
+ * scaled by this divider, so probably it is related with internal
+ * 'working' frequency.
+ */
+#define ALVCON_UNKDIV_POS   16
+#define ALVCON_UNKDIV_MSK   0x3
+
+/* bits[14:1] are UNKNOWN */
+
+#define ALVCON_OSCSEL_BIT   (1 << 0)   /* 0 -> OSC0, 1 -> OSC1 */
+
+
+/*
+ * System Alive timer
+ *
+ * ALVCOM_RUN_BIT starts/stops count on ALVTCNT, counter frequency
+ * is SClk / ALVTDIV. When count reachs ALVTEND then ALVTSTAT[0]
+ * and ALVUNK4[0] are set, optionally an interrupt is generated (see
+ * GPIO_EINT_ALIVE). Writing 1 to ALVTCOM_RST_BIT clears ALVSTAT[0]
+ * and ALVUNK4[0], and initializes ALVTCNT to zero.
+ */
+#define ALVTCOM         (*((REG32_PTR_T)(SYSALV_BASE + 0x6c)))
+#define ALVTCOM_RUN_BIT     (1 << 0)  /* 0 -> Stop, 1 -> Start */
+#define ALVTCOM_RST_BIT     (1 << 1)  /* 1 -> Reset */
+
+#define ALVTEND         (*((REG32_PTR_T)(SYSALV_BASE + 0x70)))
+#define ALVTDIV         (*((REG32_PTR_T)(SYSALV_BASE + 0x74)))
+
+#define ALVTCNT         (*((REG32_PTR_T)(SYSALV_BASE + 0x78)))
+#define ALVTSTAT        (*((REG32_PTR_T)(SYSALV_BASE + 0x7c)))
+
+#endif /* CONFIG_CPU == S5L8702 */
+
 #endif /* __S5L87XX_H__ */
diff --git a/firmware/target/arm/s5l8702/gpio-s5l8702.h b/firmware/target/arm/s5l8702/gpio-s5l8702.h
index 05197eaf62..2acf52c7b8 100644
--- a/firmware/target/arm/s5l8702/gpio-s5l8702.h
+++ b/firmware/target/arm/s5l8702/gpio-s5l8702.h
@@ -23,53 +23,6 @@
 #define __GPIO_S5L8702_H__
 #include <stdint.h>
 
-
-#define REG32_PTR_T volatile uint32_t *
-
-/*
- * s5l8702 External (GPIO) Interrupt Controller
- *
- * 7 groups of 32 interrupts, GPIO pins are seen as 'wired'
- * to groups 6..3 in reverse order.
- * On group 3, last four bits are dissbled (GPIO 124..127).
- * All bits in groups 1 and 2 are disabled (not used).
- * On group 0, all bits are masked except bits 0 and 2:
- *  bit 0: if unmasked, EINT6 is generated when ALVTCNT
- *         reachs ALVTEND.
- *  bit 2: if unmasked, EINT6 is generated when USB cable
- *         is plugged and/or(TBC) unplugged.
- *
- * EIC_GROUP0..6 are connected to EINT6..0 of the VIC.
- */
-#define EIC_N_GROUPS    7
-
-/* get EIC group and bit for a given GPIO port */
-#define EIC_GROUP(n)    (6 - ((n) >> 5))
-#define EIC_INDEX(n)    ((0x18 - ((n) & 0x18)) | ((n) & 0x7))
-
-/* SoC EINTs uses these 'gpio' numbers */
-#define GPIO_EINT_USB       0xd8
-#define GPIO_EINT_ALIVE     0xda
-
-/* probably a part of the system controller */
-#if CONFIG_CPU == S5L8702
-#define EIC_BASE 0x39a00000
-#elif CONFIG_CPU == S5L8720
-#define EIC_BASE 0x39700000
-#endif
-
-#define EIC_INTLEVEL(g) (*((REG32_PTR_T)(EIC_BASE + 0x80 + 4*(g))))
-#define EIC_INTSTAT(g)  (*((REG32_PTR_T)(EIC_BASE + 0xA0 + 4*(g))))
-#define EIC_INTEN(g)    (*((REG32_PTR_T)(EIC_BASE + 0xC0 + 4*(g))))
-#define EIC_INTTYPE(g)  (*((REG32_PTR_T)(EIC_BASE + 0xE0 + 4*(g))))
-
-#define EIC_INTLEVEL_LOW    0
-#define EIC_INTLEVEL_HIGH   1
-
-#define EIC_INTTYPE_EDGE    0
-#define EIC_INTTYPE_LEVEL   1
-
-
 struct eic_handler {
     uint8_t gpio_n;
     uint8_t type;       /* EIC_INTTYPE_ */
@@ -88,81 +41,4 @@ void gpio_init(void);
 uint32_t gpio_group_get(int group);
 void gpio_group_set(int group, uint32_t mask, uint32_t cfg);
 
-
-#if CONFIG_CPU == S5L8702
-/*
- * This is very preliminary work in progress, ATM this region is called
- * system 'alive' because it seems there are similiarities when mixing
- * concepts from:
- *  - s3c2440 datasheet (figure 7-12, Sleep mode) and
- *  - ARM-DDI-0287B (2.1.8 System Mode Control, Sleep an Doze modes)
- *
- * Known components:
- * - independent clocking
- * - 32-bit timer
- * - level/edge configurable interrupt controller
- *
- *
- *        OSCSEL
- *          |\    CKSEL
- *  OSC0 -->| |    |\
- *          | |--->| |     _________             ___________
- *  OSC1 -->| |    | |    |         | SClk      |           |
- *          |/     | |--->| 1/CKDIV |---------->| 1/ALVTDIV |--> Timer
- *                 | |    |_________|       |   |___________|    counter
- *  PClk --------->| |                      |    ___________
- *                 |/                       |   |           |
- *                                          +-->| 1/UNKDIV  |--> Unknown
- *                                              |___________|
- */
-#define SYSALV_BASE 0x39a00000
-
-#define ALVCON          (*((REG32_PTR_T)(SYSALV_BASE + 0x0)))
-#define ALVUNK4         (*((REG32_PTR_T)(SYSALV_BASE + 0x4)))
-#define ALVUNK100       (*((REG32_PTR_T)(SYSALV_BASE + 0x100)))
-#define ALVUNK104       (*((REG32_PTR_T)(SYSALV_BASE + 0x104)))
-
-
-/*
- * System Alive control register
- */
-#define ALVCON_CKSEL_BIT    (1 << 25)  /* 0 -> S5L8702_OSCx, 1 -> PClk */
-#define ALVCON_CKDIVEN_BIT  (1 << 24)  /* 0 -> CK divider Off, 1 -> On */
-#define ALVCON_CKDIV_POS    20         /* real_val = reg_val+1 */
-#define ALVCON_CKDIV_MSK    0xf
-
-/* UNKDIV: real_val = reg_val+1 (TBC), valid reg_val=0,1,2 */
-/* experimental: for registers in this region, read/write speed is
- * scaled by this divider, so probably it is related with internal
- * 'working' frequency.
- */
-#define ALVCON_UNKDIV_POS   16
-#define ALVCON_UNKDIV_MSK   0x3
-
-/* bits[14:1] are UNKNOWN */
-
-#define ALVCON_OSCSEL_BIT   (1 << 0)   /* 0 -> OSC0, 1 -> OSC1 */
-
-
-/*
- * System Alive timer
- *
- * ALVCOM_RUN_BIT starts/stops count on ALVTCNT, counter frequency
- * is SClk / ALVTDIV. When count reachs ALVTEND then ALVTSTAT[0]
- * and ALVUNK4[0] are set, optionally an interrupt is generated (see
- * GPIO_EINT_ALIVE). Writing 1 to ALVTCOM_RST_BIT clears ALVSTAT[0]
- * and ALVUNK4[0], and initializes ALVTCNT to zero.
- */
-#define ALVTCOM         (*((REG32_PTR_T)(SYSALV_BASE + 0x6c)))
-#define ALVTCOM_RUN_BIT     (1 << 0)  /* 0 -> Stop, 1 -> Start */
-#define ALVTCOM_RST_BIT     (1 << 1)  /* 1 -> Reset */
-
-#define ALVTEND         (*((REG32_PTR_T)(SYSALV_BASE + 0x70)))
-#define ALVTDIV         (*((REG32_PTR_T)(SYSALV_BASE + 0x74)))
-
-#define ALVTCNT         (*((REG32_PTR_T)(SYSALV_BASE + 0x78)))
-#define ALVTSTAT        (*((REG32_PTR_T)(SYSALV_BASE + 0x7c)))
-
-#endif /* CONFIG_CPU == S5L8702 */
-
 #endif /* __GPIO_S5L8702_H__ */
diff --git a/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c b/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c
index fabc0f869b..9f452cbe56 100644
--- a/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c
+++ b/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c
@@ -483,11 +483,11 @@ static int ceata_wait_idle(void)
 
 static int ceata_cancel_command(void)
 {
-    *((uint32_t volatile*)0x3cf00200) = 0x9000e;
+    GPIOCMD = 0x9000e;
     udelay(1);
-    *((uint32_t volatile*)0x3cf00200) = 0x9000f;
+    GPIOCMD = 0x9000f;
     udelay(1);
-    *((uint32_t volatile*)0x3cf00200) = 0x90003;
+    GPIOCMD = 0x90003;
     udelay(1);
     PASS_RC(mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_STOP_TRANSMISSION)
                            | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1 | SDCI_CMD_RES_BUSY
@@ -669,17 +669,17 @@ static int ata_power_up(void)
         PCON(8) = 0x33333333;
         PCON(9) = 0x00000033;
         PCON(11) |= 0xf;
-        *((uint32_t volatile*)0x38a00000) = 0;
-        *((uint32_t volatile*)0x38700000) = 0;
+        ATA_UNKNOWN = 0;
+        ATA_CONTROL = 0;
         PWRCON(0) &= ~(1 << 9);
         SDCI_RESET = 0xa5;
         sleep(HZ / 100);
-        *((uint32_t volatile*)0x3cf00380) = 0;
-        *((uint32_t volatile*)0x3cf0010c) = 0xff;
+        GPIOUNK380 = 0;
+        PUNK8 = 0xff;
         SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK
                   | SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
         SDCI_CLKDIV = SDCI_CDIV_CLKDIV(260);
-        *((uint32_t volatile*)0x3cf00200) = 0xb000f;
+        GPIOCMD = 0xb000f;
         SDCI_IRQ_MASK = SDCI_IRQ_MASK_MASK_DAT_DONE_INT | SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT;
         PASS_RC(mmc_init(), 3, 0);
         SDCI_CLKDIV = SDCI_CDIV_CLKDIV(4);
diff --git a/firmware/target/arm/s5l8702/system-s5l8702.c b/firmware/target/arm/s5l8702/system-s5l8702.c
index 59165ac004..b0d73f8518 100644
--- a/firmware/target/arm/s5l8702/system-s5l8702.c
+++ b/firmware/target/arm/s5l8702/system-s5l8702.c
@@ -301,7 +301,7 @@ static void set_page_tables(void)
 #endif
 
     /* disable caching for I/O area */
-    map_section(0x38000000, 0x38000000, 0x80, CACHE_NONE);
+    map_section(IO_BASE, IO_BASE, 0x80, CACHE_NONE);
 
     /* map RAM uncached addresses */
     map_section(0, S5L8702_UNCACHED_ADDR(0x0), 0x380, CACHE_NONE);