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authorAmaury Pouly <amaury.pouly@gmail.com>2017-09-24 23:25:08 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2017-09-24 23:32:47 +0200
commit13364c552548ca15c34f781613762e88f6f2e327 (patch)
tree06acd878fc97e679bede1c8bc3cff8d1a9bcd023 /apps/lang/lang.make
parent533b2da2ab10e3149e0ece7c9e21380db075c1ee (diff)
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Fix make race conditions reharding lang.h
The bug is due to a stupid make misfeature. The article [1] contains much more information but in a nutshell, the following code: a b: c bla is equivalent to: a: c bla b: c bla This is bad because in parallel runs (make -j typically), "bla" can be run TWICE and even worse, twice in PARALLEL. Obviously the result will be completely unexpected. This is a real bummer because on the other hand, the following code: %.c %.h: %:in bla actually expresses the fact that bla produces two files. For some reasons, pattern rules work differently from implicit rules. This commit attempts to fix the problem with lang.h by rewriting (simplified): lang.c lang.h: lang.in genlang as lang.h: lang.in genlang lang.c: lang.h This works (it correctly expresses the dependency chain and ensures genlang runs once) but as one drawback: if one manually removes lang.c, then genlang will not re-run since the second rule does nothing. This is minor drawback since no one ever removes lang.c manually and "clean" removes lang.h which triggers a rebuild. [1]: https://www.gnu.org/software/automake/manual/html_node/Multiple-Outputs.html Change-Id: Ic0bf7c7c203dc599b00fde457946d2316c70474e
Diffstat (limited to 'apps/lang/lang.make')
-rw-r--r--apps/lang/lang.make10
1 files changed, 9 insertions, 1 deletions
diff --git a/apps/lang/lang.make b/apps/lang/lang.make
index 6465b426b7..cee2456b5d 100644
--- a/apps/lang/lang.make
+++ b/apps/lang/lang.make
@@ -31,11 +31,19 @@ $(BUILDDIR)/lang/max_language_size.h: $(LANGOBJ) $(BUILDDIR)/apps/lang/voicestri
$(BUILDDIR)/lang/lang_core.o: $(BUILDDIR)/lang/lang.h $(BUILDDIR)/lang/lang_core.c
$(call PRINTS,CC lang_core.c)$(CC) $(CFLAGS) -c $(BUILDDIR)/lang/lang_core.c -o $@
-$(BUILDDIR)/lang/lang.h $(BUILDDIR)/lang/lang_core.c: $(APPSDIR)/lang/$(LANGUAGE).lang $(BUILDDIR)/apps/features
+# genlang creates *both* lang.c and lang.h but in Make there is no wat to express this rule
+# (multiple target rules DO NOT express that, they are a simple shortcut for multiple rules)
+# instead we pretend that genlang create lang_core.c and that lang.c depends from lang.h
+# it will work fine as long as one never manually removes lang.c and not lang.h, and it will avoid
+# race conditions such as running genlang twice or worse in parallel with other things!
+$(BUILDDIR)/lang/lang.h: $(APPSDIR)/lang/$(LANGUAGE).lang $(BUILDDIR)/apps/features
$(call PRINTS,GEN lang.h)
$(SILENT)for f in `cat $(BUILDDIR)/apps/features`; do feat="$$feat:$$f" ; done; \
perl -s $(TOOLSDIR)/genlang -p=$(BUILDDIR)/lang -t=$(MODELNAME)$$feat $<
+$(BUILDDIR)/lang/lang_core.c: $(BUILDDIR)/lang/lang.h
+# NOTE: for some weird reasons in GNU make, multi targets rules WITH patterns actually express
+# the fact that the two files are created as the result of one invocation of the rule
$(BUILDDIR)/%.lng $(BUILDDIR)/%.vstrings: $(ROOTDIR)/%.lang $(BUILDDIR)/apps/genlang-features
$(call PRINTS,GENLANG $(subst $(ROOTDIR)/,,$<))
$(SILENT)mkdir -p $(dir $@)