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authorAndree Buschmann <AndreeBuschmann@t-online.de>2010-11-21 12:27:01 +0000
committerAndree Buschmann <AndreeBuschmann@t-online.de>2010-11-21 12:27:01 +0000
commiteef21cb18ae4bc7cdf83830554a848e0c733a73d (patch)
treedb04e994c7be9d634a49245928a99f6888e576b5 /apps/plugins/imageviewer/imageviewer.make
parentf54cbfa1647a1bcacb7998e0e19b17f0d1bde84a (diff)
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Change alignment macros to allow further performance optimization. Define the CACHEALIGN macros for all ARM CPUs, the used alignment size is derived from CACHEALIGN_BITS which has been defined for each supported ARM CPU with r28619. The default alignment size for ARM is set to 32 bytes as new -- not yet supported -- ARM CPUs will most probably need this alignment. To be able to differ between ARM and other CPUs a new macro called MEM_ALIGN_ATTR is introduced. This equals CACHEALIGN_ATTR for ARM, 16 byte alignment for Coldfire and is kept empty for other CPUs. MEM_ALIGN_ATTR is available system wide. From measurements it is expected that the usage of MEM_ALIGN_ATTR can give significant performance gain on ARM11 CPUs.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28625 a1c6a512-1295-4272-9138-f99709370657
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