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authorSolomon Peachy <pizza@shaftnet.org>2020-08-08 22:25:04 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-08-08 22:29:29 -0400
commit08c4b708ae52dc6bb5848b72a897e7790da5dd9e (patch)
treec7dbccc45f6ba8c54712f41f6f855030bc8b3a73 /apps
parentbe2c8734cbf3f32fcf3513e8899e3b7596c2c19d (diff)
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jz4760: Move 11/22/44/88KHz back onto the PLL
PLL1 clock for those frequencies has been dropped from 508 to 169.5 MHz, so it's still a respectable reduction. (I'm not sure how/why it ever worked with the XTAL source, but it did, and was off by an audible amount) Change-Id: I614d87e7dfdfe9210702b9c646d3863c06d6780b
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