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authorSolomon Peachy <pizza@shaftnet.org>2020-08-06 22:17:23 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-08-07 03:44:01 +0000
commite0bb30a1bdf977765d1e891c1bc32bed3fa7c36e (patch)
tree8e34e32bb4c34bc68e11cabcf35922ade9b60db0 /apps
parentf554c7873428018b482e57c6ba9c96e0e67d320c (diff)
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xduoox3: Set PLL0 to 480MHz, not 492.
PLL0 Needs to be a multiple of 48MHz for sane USB operation! (Indeed, "typical" clock for this part is 528, but that seems a waste of power) Also fixes a minor bugaboo in the jz4670 usb divisor calculation that won't matter until we enable reclocking Change-Id: I40b1fd1ae48871e50885981ccc8b01feb711b9a5
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