|author||Solomon Peachy <email@example.com>||2020-08-06 22:17:23 -0400|
|committer||Solomon Peachy <firstname.lastname@example.org>||2020-08-07 03:44:01 +0000|
xduoox3: Set PLL0 to 480MHz, not 492.
PLL0 Needs to be a multiple of 48MHz for sane USB operation! (Indeed, "typical" clock for this part is 528, but that seems a waste of power) Also fixes a minor bugaboo in the jz4670 usb divisor calculation that won't matter until we enable reclocking Change-Id: I40b1fd1ae48871e50885981ccc8b01feb711b9a5
Diffstat (limited to 'apps')
0 files changed, 0 insertions, 0 deletions