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authorAidan MacDonald <amachronic@protonmail.com>2021-04-15 03:00:04 +0100
committerAidan MacDonald <amachronic@protonmail.com>2021-04-17 20:24:07 +0000
commit01d1eb425874813864d12d72c93e6e74ab92ac1f (patch)
treee4bc6171342e1ef4160b2e32653f5668f9be3d69 /firmware/export/hd66789r.h
parente123c5d2f27e9efbef8b4264f1576e4e10ba7b82 (diff)
downloadrockbox-01d1eb425874813864d12d72c93e6e74ab92ac1f.tar.gz
rockbox-01d1eb425874813864d12d72c93e6e74ab92ac1f.zip
FiiO M3K/X1000: Do system clock initialization in the SPL
Initializing the clocks in the SPL brings Rockbox in line with how the FiiO M3K's original SPL works. It's likely other X1000 devices do this too. There was a logic error in the previous setup: the code falsely assumed that DDR memory would always be running from MPLL, but it would be switched to APLL by the bootloader. Rockbox would then try to re-init APLL, albeit with the same parameters. Maybe this was the cause of the boot hang on some units. Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917
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