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authorSolomon Peachy <pizza@shaftnet.org>2020-08-28 21:45:58 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-09-03 15:34:28 -0400
commit0cb162a76b16d58250a33e817af6a763e89a770a (patch)
treeaf5ac50c1ec59f665e0a4845672a16d758b44953 /firmware/rolo.c
parent1ae8213a64c23ac86173b8139e01c7cad350ec6b (diff)
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mips: Heavily rework DMA & caching code
Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527) but rebased and heavily updated. Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
Diffstat (limited to 'firmware/rolo.c')
-rw-r--r--firmware/rolo.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/rolo.c b/firmware/rolo.c
index de19c8e925..e60af46704 100644
--- a/firmware/rolo.c
+++ b/firmware/rolo.c
@@ -201,7 +201,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
: : "r"(dest)
);
#elif defined(CPU_MIPS)
- __dcache_writeback_all();
+ commit_discard_idcache();
asm volatile(
"jr %0 \n"
: : "r"(dest)