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authorMichael Sevakis <jethead71@rockbox.org>2007-04-13 20:55:48 +0000
committerMichael Sevakis <jethead71@rockbox.org>2007-04-13 20:55:48 +0000
commitd95c39072ace1a7aeaad3ee49ed668399b4862bd (patch)
tree7f8c8e41e5e793daa64051f153bbbd52ccbe8fc9 /firmware/rolo.c
parente10f455fbd3149a034e35d30be333f958d773d92 (diff)
downloadrockbox-d95c39072ace1a7aeaad3ee49ed668399b4862bd.tar.gz
rockbox-d95c39072ace1a7aeaad3ee49ed668399b4862bd.zip
Portal Player: Add invalidate_icache and flush_icache. Flush the cache on the core for newborn threads. In doing so, move more ARM stuff to the target tree and organize it to make a clean job of it. If anything isn't appropriate for some particular device give a hollar or even just fix it by some added #ifdefing. I was informed that the PP targets are register compatible so I'm going off that advice. The Sansa likes it though.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13144 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/rolo.c')
-rw-r--r--firmware/rolo.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/firmware/rolo.c b/firmware/rolo.c
index 0689e8be5b..0375a7ac82 100644
--- a/firmware/rolo.c
+++ b/firmware/rolo.c
@@ -49,8 +49,7 @@ void rolo_restart_cop(void) ICODE_ATTR;
void rolo_restart_cop(void)
{
/* Invalidate cache */
- outl(inl(0xf000f044) | 0x6, 0xf000f044);
- while ((CACHE_CTL & 0x8000) != 0) {}
+ invalidate_icache();
/* Disable cache */
CACHE_CTL = CACHE_DISABLE;
@@ -119,8 +118,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
cpu_message = 0;
/* Flush cache */
- outl(inl(0xf000f044) | 0x2, 0xf000f044);
- while ((CACHE_CTL & 0x8000) != 0) {}
+ flush_icache();
/* Disable cache */
CACHE_CTL = CACHE_DISABLE;