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authorLinus Nielsen Feltzing <linus@haxx.se>2005-04-14 05:56:36 +0000
committerLinus Nielsen Feltzing <linus@haxx.se>2005-04-14 05:56:36 +0000
commit81bd3692882707d90a2be6a8c8de67fa9b2e9815 (patch)
tree3e4ecbfe18581b122d9c932346a747852b90bf65 /firmware/system.c
parent4488ad63de89dbf4b539dafd0f027289986dfe38 (diff)
downloadrockbox-81bd3692882707d90a2be6a8c8de67fa9b2e9815.tar.gz
rockbox-81bd3692882707d90a2be6a8c8de67fa9b2e9815.zip
Wrong setting of AUDIOSEL caused double pitch 120MHz playback
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6282 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/system.c')
-rw-r--r--firmware/system.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/system.c b/firmware/system.c
index 341e2938fb..3253d3d7c5 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -483,7 +483,7 @@ void set_cpu_frequency(long frequency)
DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass
frequency */
PLLCR &= ~1; /* Bypass mode */
- PLLCR = 0x11c53005;
+ PLLCR = 0x11853005;
CSCR0 = 0x00000980; /* Flash: 2 wait state */
CSCR1 = 0x00002580; /* LCD: 9 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -502,7 +502,7 @@ void set_cpu_frequency(long frequency)
DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass
frequency */
PLLCR &= ~1; /* Bypass mode */
- PLLCR = 0x10c86001;
+ PLLCR = 0x10886001;
CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000980; /* LCD: 2 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@@ -519,7 +519,7 @@ void set_cpu_frequency(long frequency)
default:
DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass
frequency */
- PLLCR = 0x00400000; /* Bypass mode */
+ PLLCR = 0x00000000; /* Bypass mode */
CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
cpu_frequency = CPU_FREQ;