path: root/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c
diff options
authorWilliam Wilgus <>2018-07-27 23:56:32 +0200
committerWilliam Wilgus <>2018-07-27 23:56:32 +0200
commit6f0320a9535bc1aa81d83fa879ac14d5ee603658 (patch)
tree3b12fc361595ecd2249f391e114036cb30150105 /firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c
parent400603abdfb4ba7566e0cae8dbed9268f06716dc (diff)
As3525 v1/v2 Add power savings menu
Allow user to select cpu undervolt There have been quite a few issues across the SANSA AMS line related to CPU undervolting while most players show greatly increased runtime some crash. Rather than constanly upping the voltage we now have a setting with a safe value for all players and the option for lower voltages I plan to add a few other options here later such as disk timings and maybe some other clocks/experimental settings Added: Disk Low speed option for AS3525v2 devices cuts frequency to 12 MHz from 24 MHz Added: Disk Low speed option for AS3525v1 devices cuts frequency to 15.5 MHz from 31 MHz Added: I2c Low Speed AS3525 devices, should be bigger improvement for v1 devices Fixed: Debug menu for AS3525v2 No SDSLOT frequency, Showed IDE freq though it is unused Added: DBOP and SSP underclocking affects display on v1/v2 respectively Fixed: debug menu now has SSP frequency, and SSP_CPSR Update: made settings menu more generic Update: cleaned up code Added: Clip v1 & Fuze v1 didn't have HAVE_ADJUSTABLE_CPU_VOLTAGE. not sure why but, waiting on testing to confirm Added: C200v2 and E200v2 devices and HAVE_ADJUSTABLE_CPU_VOLTAGE. Fixed: v1 devices don't like display timing set lower (dbop) v1 devices don't have a divider set for ssp (causes divide by 0) Fixed: ClipZip display lags with Max SSP divider changed from 0xFE to 0x32 Fixed: v1 devices didn't work properly with highspeed sd cards Added code from Added powersave and IDE interface enable/disable Added: V2 devices now have powersave enabled on sd interface Update: cleaned up code, lang defines, added manual entries Update ssp clock mechanism added calculated ssp divider to clipzip Update turn display clock off when clip+ turns off display Fixed: clipzip wrong register for SSP clock Change-Id: I04137682243be92f0f8d8bf1cfa54fbb1965559b TODO: add other players?
Diffstat (limited to 'firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c')
1 files changed, 23 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c b/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c
index e17bfc421b..8a3df517fb 100644
--- a/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c
+++ b/firmware/target/arm/as3525/sansa-clipzip/lcd-clipzip.c
@@ -35,12 +35,26 @@ static int lcd_type;
static bool lcd_enabled;
+static void ssp_set_prescaler(unsigned int prescaler)
+ int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
+ /* must be on to write regs */
+ bool ssp_enabled = bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE) &
+ SSP_CPSR = prescaler;
+ if (!ssp_enabled) /* put it back how we found it */
+ restore_irq(oldlevel);
/* initialises the host lcd hardware, returns the lcd type */
static int lcd_hw_init(void)
/* configure SSP */
- SSP_CPSR = 4; /* TODO: use AS3525_SSP_PRESCALER, OF uses 8 */
+ ssp_set_prescaler(AS3525_SSP_PRESCALER); /* OF = 0x8 */
SSP_CR0 = (0 << 8) | /* SCR, serial clock rate divider = 1 */
(1 << 7) | /* SPH, phase = 1 */
(1 << 6) | /* SPO, polarity = 1 */
@@ -437,3 +451,11 @@ void lcd_update(void)
lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
+/* declared in system-as3525.c */
+void ams_ssp_set_low_speed(bool slow)
+ ssp_set_prescaler(slow ? AS3525_SSP_PRESCALER_MAX : AS3525_SSP_PRESCALER);