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authorAmaury Pouly <amaury.pouly@gmail.com>2013-06-16 20:08:49 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2013-06-17 00:29:24 +0200
commitf5ac658d160d11880c2affa9c5b669404c4fe207 (patch)
tree120f5e132430ea032d12d765fc6f407c020a908e /firmware/target/arm/imx233/clkctrl-imx233.c
parent84fc327aeb7be91e611520bb058a6c8d318401c3 (diff)
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imx233: normalise clkctrl
The clkctrl functions were becoming a mess. Normalise the names, get rid of the xtal derived as special case and use the same interface. Change-Id: Ib954a8d30a6bd691914b5e0d97774ec9fc560c50
Diffstat (limited to 'firmware/target/arm/imx233/clkctrl-imx233.c')
-rw-r--r--firmware/target/arm/imx233/clkctrl-imx233.c151
1 files changed, 68 insertions, 83 deletions
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c
index 1553889543..102ef4e432 100644
--- a/firmware/target/arm/imx233/clkctrl-imx233.c
+++ b/firmware/target/arm/imx233/clkctrl-imx233.c
@@ -20,29 +20,19 @@
****************************************************************************/
#include "clkctrl-imx233.h"
-#define __CLK_CLKGATE (1 << 31)
-#define __CLK_BUSY (1 << 29)
-
-void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable)
-{
- if(enable)
- HW_CLKCTRL_XTAL_CLR = xtal_clk;
- else
- HW_CLKCTRL_XTAL_SET = xtal_clk;
-}
-
-bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk)
-{
- return HW_CLKCTRL_XTAL & clk;
-}
-
-void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable)
+void imx233_clkctrl_enable(enum imx233_clock_t clk, bool enable)
{
+ /* NOTE some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */
bool gate = !enable;
switch(clk)
{
case CLK_PIX: BF_WR(CLKCTRL_PIX, CLKGATE, gate); break;
case CLK_SSP: BF_WR(CLKCTRL_SSP, CLKGATE, gate); break;
+ case CLK_DRI: BF_WR(CLKCTRL_XTAL, DRI_CLK24M_GATE, gate); break;
+ case CLK_PWM: BF_WR(CLKCTRL_XTAL, PWM_CLK24M_GATE, gate); break;
+ case CLK_UART: BF_WR(CLKCTRL_XTAL, UART_CLK_GATE, gate); break;
+ case CLK_FILT: BF_WR(CLKCTRL_XTAL, FILT_CLK24M_GATE, gate); break;
+ case CLK_TIMROT: BF_WR(CLKCTRL_XTAL, TIMROT_CLK32K_GATE, gate); break;
case CLK_PLL:
/* pll is a special case */
if(enable)
@@ -58,18 +48,23 @@ void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable)
}
}
-bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t clk)
+bool imx233_clkctrl_is_enabled(enum imx233_clock_t clk)
{
switch(clk)
{
case CLK_PLL: return BF_RD(CLKCTRL_PLLCTRL0, POWER);
case CLK_PIX: return !BF_RD(CLKCTRL_PIX, CLKGATE);
case CLK_SSP: return !BF_RD(CLKCTRL_SSP, CLKGATE);
+ case CLK_DRI: return !BF_RD(CLKCTRL_XTAL, DRI_CLK24M_GATE);
+ case CLK_PWM: return !BF_RD(CLKCTRL_XTAL, PWM_CLK24M_GATE);
+ case CLK_UART: return !BF_RD(CLKCTRL_XTAL, UART_CLK_GATE);
+ case CLK_FILT: return !BF_RD(CLKCTRL_XTAL, FILT_CLK24M_GATE);
+ case CLK_TIMROT: return !BF_RD(CLKCTRL_XTAL, TIMROT_CLK32K_GATE);
default: return true;
}
}
-void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div)
+void imx233_clkctrl_set_div(enum imx233_clock_t clk, int div)
{
/* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant !
* assume that we always derive emi and cpu from ref_XX */
@@ -85,7 +80,7 @@ void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div)
}
}
-int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk)
+int imx233_clkctrl_get_div(enum imx233_clock_t clk)
{
switch(clk)
{
@@ -99,7 +94,7 @@ int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk)
}
}
-void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
+void imx233_clkctrl_set_frac_div(enum imx233_clock_t clk, int fracdiv)
{
#define handle_frac(dev) \
case CLK_##dev: \
@@ -120,7 +115,7 @@ void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv)
#undef handle_frac
}
-int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk)
+int imx233_clkctrl_get_frac_div(enum imx233_clock_t clk)
{
#define handle_frac(dev) \
case CLK_##dev:\
@@ -139,7 +134,7 @@ int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk)
#undef handle_frac
}
-void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
+void imx233_clkctrl_set_bypass(enum imx233_clock_t clk, bool bypass)
{
uint32_t msk;
switch(clk)
@@ -157,7 +152,7 @@ void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass)
HW_CLKCTRL_CLKSEQ_CLR = msk;
}
-bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk)
+bool imx233_clkctrl_get_bypass(enum imx233_clock_t clk)
{
switch(clk)
{
@@ -169,7 +164,7 @@ bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk)
}
}
-void imx233_clkctrl_enable_usb_pll(bool enable)
+void imx233_clkctrl_enable_usb(bool enable)
{
if(enable)
BF_SET(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
@@ -177,12 +172,12 @@ void imx233_clkctrl_enable_usb_pll(bool enable)
BF_CLR(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
}
-bool imx233_clkctrl_is_usb_pll_enabled(void)
+bool imx233_clkctrl_is_usb_enabled(void)
{
return BF_RD(CLKCTRL_PLLCTRL0, EN_USB_CLKS);
}
-void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div)
+void imx233_clkctrl_set_auto_slow_div(unsigned div)
{
/* the SLOW_DIV must only be set when auto-slow is disabled */
bool old_status = imx233_clkctrl_is_auto_slow_enabled();
@@ -191,7 +186,7 @@ void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div)
imx233_clkctrl_enable_auto_slow(old_status);
}
-enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void)
+unsigned imx233_clkctrl_get_auto_slow_div(void)
{
return BF_RD(CLKCTRL_HBUS, SLOW_DIV);
}
@@ -206,30 +201,12 @@ bool imx233_clkctrl_is_auto_slow_enabled(void)
return BF_RD(CLKCTRL_HBUS, AUTO_SLOW_MODE);
}
-void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable)
-{
- if(enable)
- HW_CLKCTRL_HBUS_SET = monitor;
- else
- HW_CLKCTRL_HBUS_CLR = monitor;
-}
-
-bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor)
-{
- return HW_CLKCTRL_HBUS & monitor;
-}
-
-bool imx233_clkctrl_is_emi_sync_enabled(void)
-{
- return BF_RD(CLKCTRL_EMI, SYNC_MODE_EN);
-}
-
-unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
+unsigned imx233_clkctrl_get_freq(enum imx233_clock_t clk)
{
switch(clk)
{
case CLK_PLL: /* PLL: 480MHz when enable */
- return imx233_clkctrl_is_clock_enabled(CLK_PLL) ? 480000 : 0;
+ return imx233_clkctrl_is_enabled(CLK_PLL) ? 480000 : 0;
case CLK_XTAL: /* crystal: 24MHz */
return 24000;
case CLK_CPU:
@@ -238,78 +215,78 @@ unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
/* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider
* otherwise, clk_p derived from clk_cpu via int div and clk_cpu
* derived from clk_pll fracdiv */
- if(imx233_clkctrl_get_bypass_pll(CLK_CPU))
+ if(imx233_clkctrl_get_bypass(CLK_CPU))
{
- ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
+ ref = imx233_clkctrl_get_freq(CLK_XTAL);
/* Integer divide mode vs fractional divide mode */
if(BF_RD(CLKCTRL_CPU, DIV_XTAL_FRAC_EN))
return (ref * BF_RD(CLKCTRL_CPU, DIV_XTAL)) / 32;
else
- return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
+ return ref / imx233_clkctrl_get_div(CLK_CPU);
}
else
{
- ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
+ ref = imx233_clkctrl_get_freq(CLK_PLL);
/* fractional divider enable ? */
- if(imx233_clkctrl_get_fractional_divisor(CLK_CPU) != 0)
- ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_CPU);
- return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU);
+ if(imx233_clkctrl_get_frac_div(CLK_CPU) != 0)
+ ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_CPU);
+ return ref / imx233_clkctrl_get_div(CLK_CPU);
}
}
case CLK_HBUS:
{
/* Derived from clk_p via integer/fractional div */
- unsigned ref = imx233_clkctrl_get_clock_freq(CLK_CPU);
- if(imx233_clkctrl_get_fractional_divisor(CLK_HBUS) != 0)
- ref = (ref * imx233_clkctrl_get_fractional_divisor(CLK_HBUS)) / 32;
- if(imx233_clkctrl_get_clock_divisor(CLK_HBUS) != 0)
- ref /= imx233_clkctrl_get_clock_divisor(CLK_HBUS);
+ unsigned ref = imx233_clkctrl_get_freq(CLK_CPU);
+ if(imx233_clkctrl_get_frac_div(CLK_HBUS) != 0)
+ ref = (ref * imx233_clkctrl_get_frac_div(CLK_HBUS)) / 32;
+ if(imx233_clkctrl_get_div(CLK_HBUS) != 0)
+ ref /= imx233_clkctrl_get_div(CLK_HBUS);
return ref;
}
case CLK_IO:
{
/* Derived from clk_pll via fracdiv */
- unsigned ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
- if(imx233_clkctrl_get_fractional_divisor(CLK_IO) != 0)
- ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_IO);
+ unsigned ref = imx233_clkctrl_get_freq(CLK_PLL);
+ if(imx233_clkctrl_get_frac_div(CLK_IO) != 0)
+ ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_IO);
return ref;
}
case CLK_PIX:
{
unsigned ref;
/* Derived from clk_pll or clk_xtal */
- if(!imx233_clkctrl_is_clock_enabled(CLK_PIX))
+ if(!imx233_clkctrl_is_enabled(CLK_PIX))
ref = 0;
- else if(imx233_clkctrl_get_bypass_pll(CLK_PIX))
- ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
+ else if(imx233_clkctrl_get_bypass(CLK_PIX))
+ ref = imx233_clkctrl_get_freq(CLK_XTAL);
else
{
- ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
- if(imx233_clkctrl_get_fractional_divisor(CLK_PIX) != 0)
- ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_PIX);
+ ref = imx233_clkctrl_get_freq(CLK_PLL);
+ if(imx233_clkctrl_get_frac_div(CLK_PIX) != 0)
+ ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_PIX);
}
- return ref / imx233_clkctrl_get_clock_divisor(CLK_PIX);
+ return ref / imx233_clkctrl_get_div(CLK_PIX);
}
case CLK_SSP:
{
unsigned ref;
/* Derived from clk_pll or clk_xtal */
- if(!imx233_clkctrl_is_clock_enabled(CLK_SSP))
+ if(!imx233_clkctrl_is_enabled(CLK_SSP))
ref = 0;
- else if(imx233_clkctrl_get_bypass_pll(CLK_SSP))
- ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
+ else if(imx233_clkctrl_get_bypass(CLK_SSP))
+ ref = imx233_clkctrl_get_freq(CLK_XTAL);
else
- ref = imx233_clkctrl_get_clock_freq(CLK_IO);
- return ref / imx233_clkctrl_get_clock_divisor(CLK_SSP);
+ ref = imx233_clkctrl_get_freq(CLK_IO);
+ return ref / imx233_clkctrl_get_div(CLK_SSP);
}
case CLK_EMI:
{
unsigned ref;
/* Derived from clk_pll or clk_xtal */
- if(imx233_clkctrl_get_bypass_pll(CLK_EMI))
+ if(imx233_clkctrl_get_bypass(CLK_EMI))
{
- ref = imx233_clkctrl_get_clock_freq(CLK_XTAL);
+ ref = imx233_clkctrl_get_freq(CLK_XTAL);
if(BF_RD(CLKCTRL_EMI, CLKGATE))
return 0;
else
@@ -317,16 +294,24 @@ unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk)
}
else
{
- ref = imx233_clkctrl_get_clock_freq(CLK_PLL);
- if(imx233_clkctrl_get_fractional_divisor(CLK_EMI) != 0)
- ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_EMI);
- return ref / imx233_clkctrl_get_clock_divisor(CLK_EMI);
+ ref = imx233_clkctrl_get_freq(CLK_PLL);
+ if(imx233_clkctrl_get_frac_div(CLK_EMI) != 0)
+ ref = (ref * 18) / imx233_clkctrl_get_frac_div(CLK_EMI);
+ return ref / imx233_clkctrl_get_div(CLK_EMI);
}
}
case CLK_XBUS:
- return imx233_clkctrl_get_clock_freq(CLK_XTAL) /
- imx233_clkctrl_get_clock_divisor(CLK_XBUS);
+ return imx233_clkctrl_get_freq(CLK_XTAL) / imx233_clkctrl_get_div(CLK_XBUS);
default:
return 0;
}
}
+
+void imx233_clkctrl_init(void)
+{
+ /* set auto-slow monitor to all */
+ HW_CLKCTRL_HBUS_SET = BF_OR8(CLKCTRL_HBUS,
+ APBHDMA_AS_ENABLE(1), TRAFFIC_JAM_AS_ENABLE(1), TRAFFIC_AS_ENABLE(1),
+ APBXDMA_AS_ENABLE(1), CPU_INSTR_AS_ENABLE(1), CPU_DATA_AS_ENABLE(1),
+ DCP_AS_ENABLE(1), PXP_AS_ENABLE(1));
+}