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authorAmaury Pouly <amaury.pouly@gmail.com>2012-01-21 20:14:27 +0100
committerAmaury Pouly <amaury.pouly@gmail.com>2012-01-21 20:15:29 +0100
commiteaa83bd64775b87e943d345e2810deed44408776 (patch)
tree2d3eb4c5c29338c5bd254c1c54e8114d07cfc062 /firmware/target/arm/imx233/clkctrl-imx233.h
parent6b7db7e465f03712520128b4a527829c5f2be3ca (diff)
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imx233: fix clkctrl code (some registers don't have a SET/CLR variant)
Change-Id: I3ce6a77cdc5ea89e1e43bc00c9ec43664e765fdc
Diffstat (limited to 'firmware/target/arm/imx233/clkctrl-imx233.h')
-rw-r--r--firmware/target/arm/imx233/clkctrl-imx233.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.h b/firmware/target/arm/imx233/clkctrl-imx233.h
index 8a52620f7e..ae2e0465a0 100644
--- a/firmware/target/arm/imx233/clkctrl-imx233.h
+++ b/firmware/target/arm/imx233/clkctrl-imx233.h
@@ -52,6 +52,7 @@
#define HW_CLKCTRL_HBUS__SLOW_DIV_BM (0x7 << 16)
#define HW_CLKCTRL_HBUS__AUTO_SLOW_MODE (1 << 20)
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_XBUS (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x40))
#define HW_CLKCTRL_XBUS__DIV_BP 0
#define HW_CLKCTRL_XBUS__DIV_BM 0x3ff
@@ -62,14 +63,17 @@
#define HW_CLKCTRL_XTAL__DRI_CLK24M_GATE (1 << 28)
#define HW_CLKCTRL_XTAL__FILT_CLK24M_GATE (1 << 30)
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_PIX (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x60))
#define HW_CLKCTRL_PIX__DIV_BP 0
#define HW_CLKCTRL_PIX__DIV_BM 0xfff
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_SSP (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x70))
#define HW_CLKCTRL_SSP__DIV_BP 0
#define HW_CLKCTRL_SSP__DIV_BM 0x1ff
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_EMI (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0xa0))
#define HW_CLKCTRL_EMI__DIV_EMI_BP 0
#define HW_CLKCTRL_EMI__DIV_EMI_BM 0x3f
@@ -94,6 +98,7 @@
#define HW_CLKCTRL_FRAC_XX__XX_STABLE (1 << 6)
#define HW_CLKCTRL_FRAC_XX__CLKGATEXX (1 << 7)
+/* warning: this register doesn't have a CLR/SET variant ! */
#define HW_CLKCTRL_RESET (*(volatile uint32_t *)(HW_CLKCTRL_BASE + 0x120))
#define HW_CLKCTRL_RESET_CHIP 0x2
#define HW_CLKCTRL_RESET_DIG 0x1