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authorAmaury Pouly <amaury.pouly@gmail.com>2014-02-04 00:26:13 +0100
committerAmaury Pouly <amaury.pouly@gmail.com>2014-02-10 23:14:25 +0100
commit65d5c426a798e6738999b02187d34728c306165a (patch)
tree727480dc98f651f519da13987caf5c29159e741e /firmware/target/arm/imx233/creative-zen
parent965c268e5f486ea9fc564c31bcdb2391ed2fb2b6 (diff)
downloadrockbox-65d5c426a798e6738999b02187d34728c306165a.tar.gz
rockbox-65d5c426a798e6738999b02187d34728c306165a.zip
imx233: fix typos
Change-Id: If5bc0f09dc0b3b1e833e41bbbdd216002e37d147
Diffstat (limited to 'firmware/target/arm/imx233/creative-zen')
-rw-r--r--firmware/target/arm/imx233/creative-zen/lcd-zen.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/target/arm/imx233/creative-zen/lcd-zen.c b/firmware/target/arm/imx233/creative-zen/lcd-zen.c
index c653b54848..dcdeeee7a1 100644
--- a/firmware/target/arm/imx233/creative-zen/lcd-zen.c
+++ b/firmware/target/arm/imx233/creative-zen/lcd-zen.c
@@ -176,7 +176,7 @@ static void lcd_init_seq(void)
* at negative edge of dotclk, reflect this in the polarity settings */
spi_write_reg(0x3, 0xd040);// polarity (OF uses 0xc040, seems incorrect)
spi_write_reg(0x8, 0); // vsync back porch (0=3H)
- spi_write_reg(0x9, 0); // hsync back porhc (0=24clk)
+ spi_write_reg(0x9, 0); // hsync back porch (0=24clk)
spi_write_reg(0x76, 0x2213);
spi_write_reg(0xb, 0x33e1);
spi_write_reg(0xc, 0x23);
@@ -296,10 +296,10 @@ void lcd_init_device(void)
imx233_lcdif_setup_dotclk_pins(8, false);
imx233_lcdif_set_word_length(8);
/** Datasheet states:
- * 257H >= VBP >= 3H, VBP > VLW, VFP > 1H
+ * 257H >= VBP >= 3H, VBP > VLW, VFP >= 1H
* 1533clk >= HBP >= 24clk, HBP > HLW, HFP >= 4clk
*
- * Take VLW=1H, VBP=3H, VFP=2H, HLW=8, HBP=24, HFP=4
+ * Take VLW=1H, VBP=3H, VFP=1H, HLW=8, HBP=24, HFP=4
* Take 3clk/pix because we send 24-bit/pix with 8-bit data bus
* Keep consistent with register setting in lcd_init_seq
*/