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authorAmaury Pouly <amaury.pouly@gmail.com>2012-05-20 01:23:17 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2012-05-20 01:35:25 +0200
commit1b6e8cba62d0ea12bc39b0e3f60f66c3892ca1ff (patch)
tree9d034e05f485b42f837a509ff91844c0f7432be5 /firmware/target/arm/imx233/dma-imx233.h
parent1adc47477144e701dcb1184f907887eadec05fda (diff)
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imx233: make sure dma descriptors are cache friendly
Because DMA descriptors needs to be committed and discarded from the cache, if they are not cache aligned and/or if their size is not a multiple of cache ligne, nasty side effects could occur with adjacents data. The same applies to DMA buffers which are still potentially broken. Add a macro to ensure that these constraints will not break by error in the future. Change-Id: I1dd69a5a9c29796c156d953eaa57c0d281e79846
Diffstat (limited to 'firmware/target/arm/imx233/dma-imx233.h')
-rw-r--r--firmware/target/arm/imx233/dma-imx233.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/dma-imx233.h b/firmware/target/arm/imx233/dma-imx233.h
index fe220dc5f7..ee836c2186 100644
--- a/firmware/target/arm/imx233/dma-imx233.h
+++ b/firmware/target/arm/imx233/dma-imx233.h
@@ -118,6 +118,10 @@
* COMMON *
**********/
+/* DMA structures should be cache aligned and be padded so that their size
+ * is a multiple of a cache line size. Otherwise some nasty side effects
+ * could occur with adjacents data fields.
+ * The same apply to DMA buffers for the same reasons */
struct apb_dma_command_t
{
struct apb_dma_command_t *next;