imx233: generate register headers using headergen_v2 and update code for it

NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.

The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
  BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
  BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
  its equivalent for BF_WR(reg_SET, ...)

I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".

Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml

Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc

1 files changed, 16 insertions, 8 deletions

diff --git a/firmware/target/arm/imx233/pwm-imx233.c b/firmware/target/arm/imx233/pwm-imx233.c
index fb14fcb91f..5e1cc1daa5 100644
--- a/firmware/target/arm/imx233/pwm-imx233.c
+++ b/firmware/target/arm/imx233/pwm-imx233.c
@@ -24,6 +24,14 @@
 #include "clkctrl-imx233.h"
 #include "pinctrl-imx233.h"
 
+#include "regs/pwm.h"
+
+/* fake field for simpler programming */
+#define BP_PWM_CTRL_PWMx_ENABLE(x)  (x)
+#define BM_PWM_CTRL_PWMx_ENABLE(x)  (1 << (x))
+#define BF_PWM_CTRL_PWMx_ENABLE(x, v)   (((v) << BP_PWM_CTRL_PWMx_ENABLE(x)) & BM_PWM_CTRL_PWMx_ENABLE(x))
+#define BFM_PWM_CTRL_PWMx_ENABLE(x, v)  BM_PWM_CTRL_PWMx_ENABLE(x)
+
 /* list of divisors + register value by increasing order of divisors */
 static int pwm_cdiv_table[] =
 {
@@ -62,8 +70,8 @@ void imx233_pwm_setup(int channel, int period, int cdiv, int active,
     imx233_pinctrl_setup_vpin(VPIN_PWM(channel), "pwm", PINCTRL_DRIVE_4mA, false);
     /* watch the order ! active THEN period
      * NOTE: the register value is period-1 */
-    HW_PWM_ACTIVEn(channel) = BF_OR2(PWM_ACTIVEn, ACTIVE(active), INACTIVE(inactive));
-    HW_PWM_PERIODn(channel) = BF_OR4(PWM_PERIODn, PERIOD(period - 1),
+    BF_WR_ALL(PWM_ACTIVEn(channel), ACTIVE(active), INACTIVE(inactive));
+    BF_WR_ALL(PWM_PERIODn(channel), PERIOD(period - 1),
         ACTIVE_STATE(active_state), INACTIVE_STATE(inactive_state), CDIV(cdiv));
     /* restore */
     imx233_pwm_enable(channel, enable);
@@ -120,11 +128,11 @@ struct imx233_pwm_info_t imx233_pwm_get_info(int channel)
     struct imx233_pwm_info_t info;
     memset(&info, 0, sizeof(info));
     info.enabled = imx233_pwm_is_enabled(channel);
-    info.cdiv = pwm_cdiv_table[BF_RDn(PWM_PERIODn, channel, CDIV)];
-    info.period = BF_RDn(PWM_PERIODn, channel, PERIOD) + 1;
-    info.active = BF_RDn(PWM_ACTIVEn, channel, ACTIVE);
-    info.inactive = BF_RDn(PWM_ACTIVEn, channel, INACTIVE);
-    info.active_state = active_state[BF_RDn(PWM_PERIODn, channel, ACTIVE_STATE)];
-    info.inactive_state = inactive_state[BF_RDn(PWM_PERIODn, channel, INACTIVE_STATE)];
+    info.cdiv = pwm_cdiv_table[BF_RD(PWM_PERIODn(channel), CDIV)];
+    info.period = BF_RD(PWM_PERIODn(channel), PERIOD) + 1;
+    info.active = BF_RD(PWM_ACTIVEn(channel), ACTIVE);
+    info.inactive = BF_RD(PWM_ACTIVEn(channel), INACTIVE);
+    info.active_state = active_state[BF_RD(PWM_PERIODn(channel), ACTIVE_STATE)];
+    info.inactive_state = inactive_state[BF_RD(PWM_PERIODn(channel), INACTIVE_STATE)];
     return info;
 }