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| author | Amaury Pouly <amaury.pouly@gmail.com> | 2016-05-24 20:29:56 +0100 |
|---|---|---|
| committer | Amaury Pouly <amaury.pouly@gmail.com> | 2016-05-28 16:49:22 +0200 |
| commit | eac1ca22bd4a6c1849880d0f8b6764befb60bc21 (patch) | |
| tree | 681da66d77b9edcb33b868cf94886440d61997cc /firmware/target/arm/imx233/regs | |
| parent | 28920ec5cc994dff19bec100a57de4557f72a7f5 (diff) | |
| download | rockbox-eac1ca22bd4a6c1849880d0f8b6764befb60bc21.tar.gz rockbox-eac1ca22bd4a6c1849880d0f8b6764befb60bc21.tar.bz2 rockbox-eac1ca22bd4a6c1849880d0f8b6764befb60bc21.zip | |
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
Diffstat (limited to 'firmware/target/arm/imx233/regs')
260 files changed, 66522 insertions, 41902 deletions
diff --git a/firmware/target/arm/imx233/regs/regs-hwecc.h b/firmware/target/arm/imx233/regs/anatop.h index f156ef492c..2eec65a526 100644 --- a/firmware/target/arm/imx233/regs/regs-hwecc.h +++ b/firmware/target/arm/imx233/regs/anatop.h @@ -6,10 +6,9 @@ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. - * headergen version: 2.1.8 - * XML versions: stmp3600:2.3.0 + * headergen version: 3.0.0 * - * Copyright (C) 2013 by Amaury Pouly + * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,14 +19,15 @@ * KIND, either express or implied. * ****************************************************************************/ -#ifndef __SELECT__HWECC__H__ -#define __SELECT__HWECC__H__ -#include "regs-macro.h" +#ifndef __HEADERGEN_ANATOP_H__ +#define __HEADERGEN_ANATOP_H__ -#define STMP3600_INCLUDE "stmp3600/regs-hwecc.h" +#include "macro.h" -#include "regs-select.h" +#define STMP3600_INCLUDE "stmp3600/anatop.h" + +#include "select.h" #undef STMP3600_INCLUDE -#endif /* __SELECT__HWECC__H__ */ +#endif /* __HEADERGEN_ANATOP_H__*/ diff --git a/firmware/target/arm/imx233/regs/apbh.h b/firmware/target/arm/imx233/regs/apbh.h new file mode 100644 index 0000000000..ba97a2f67c --- /dev/null +++ b/firmware/target/arm/imx233/regs/apbh.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_APBH_H__ +#define __HEADERGEN_APBH_H__ + +#include "macro.h" + +#define STMP3600_INCLUDE "stmp3600/apbh.h" +#define STMP3700_INCLUDE "stmp3700/apbh.h" +#define IMX233_INCLUDE "imx233/apbh.h" + +#include "select.h" + +#undef STMP3600_INCLUDE +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_APBH_H__*/ diff --git a/firmware/target/arm/imx233/regs/apbx.h b/firmware/target/arm/imx233/regs/apbx.h new file mode 100644 index 0000000000..9ef52b9a24 --- /dev/null +++ b/firmware/target/arm/imx233/regs/apbx.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_APBX_H__ +#define __HEADERGEN_APBX_H__ + +#include "macro.h" + +#define STMP3600_INCLUDE "stmp3600/apbx.h" +#define STMP3700_INCLUDE "stmp3700/apbx.h" +#define IMX233_INCLUDE "imx233/apbx.h" + +#include "select.h" + +#undef STMP3600_INCLUDE +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_APBX_H__*/ diff --git a/firmware/target/arm/imx233/regs/regs-arc.h b/firmware/target/arm/imx233/regs/arc.h index 412cf56590..cbec580697 100644 --- a/firmware/target/arm/imx233/regs/regs-arc.h +++ b/firmware/target/arm/imx233/regs/arc.h @@ -6,10 +6,9 @@ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. - * headergen version: 2.1.8 - * XML versions: stmp3600:2.3.0 + * headergen version: 3.0.0 * - * Copyright (C) 2013 by Amaury Pouly + * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,14 +19,15 @@ * KIND, either express or implied. * ****************************************************************************/ -#ifndef __SELECT__ARC__H__ -#define __SELECT__ARC__H__ -#include "regs-macro.h" +#ifndef __HEADERGEN_ARC_H__ +#define __HEADERGEN_ARC_H__ -#define STMP3600_INCLUDE "stmp3600/regs-arc.h" +#include "macro.h" -#include "regs-select.h" +#define STMP3600_INCLUDE "stmp3600/arc.h" + +#include "select.h" #undef STMP3600_INCLUDE -#endif /* __SELECT__ARC__H__ */ +#endif /* __HEADERGEN_ARC_H__*/ diff --git a/firmware/target/arm/imx233/regs/audioin.h b/firmware/target/arm/imx233/regs/audioin.h new file mode 100644 index 0000000000..8abf7443eb --- /dev/null +++ b/firmware/target/arm/imx233/regs/audioin.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_AUDIOIN_H__ +#define __HEADERGEN_AUDIOIN_H__ + +#include "macro.h" + +#define STMP3600_INCLUDE "stmp3600/audioin.h" +#define STMP3700_INCLUDE "stmp3700/audioin.h" +#define IMX233_INCLUDE "imx233/audioin.h" + +#include "select.h" + +#undef STMP3600_INCLUDE +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_AUDIOIN_H__*/ diff --git a/firmware/target/arm/imx233/regs/audioout.h b/firmware/target/arm/imx233/regs/audioout.h new file mode 100644 index 0000000000..04d5c0f811 --- /dev/null +++ b/firmware/target/arm/imx233/regs/audioout.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_AUDIOOUT_H__ +#define __HEADERGEN_AUDIOOUT_H__ + +#include "macro.h" + +#define STMP3600_INCLUDE "stmp3600/audioout.h" +#define STMP3700_INCLUDE "stmp3700/audioout.h" +#define IMX233_INCLUDE "imx233/audioout.h" + +#include "select.h" + +#undef STMP3600_INCLUDE +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_AUDIOOUT_H__*/ diff --git a/firmware/target/arm/imx233/regs/regs-bch.h b/firmware/target/arm/imx233/regs/bch.h index 014f01385a..ff16dbd307 100644 --- a/firmware/target/arm/imx233/regs/regs-bch.h +++ b/firmware/target/arm/imx233/regs/bch.h @@ -6,10 +6,9 @@ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. - * headergen version: 2.1.8 - * XML versions: imx233:3.2.0 + * headergen version: 3.0.0 * - * Copyright (C) 2013 by Amaury Pouly + * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,14 +19,15 @@ * KIND, either express or implied. * ****************************************************************************/ -#ifndef __SELECT__BCH__H__ -#define __SELECT__BCH__H__ -#include "regs-macro.h" +#ifndef __HEADERGEN_BCH_H__ +#define __HEADERGEN_BCH_H__ -#define IMX233_INCLUDE "imx233/regs-bch.h" +#include "macro.h" -#include "regs-select.h" +#define IMX233_INCLUDE "imx233/bch.h" + +#include "select.h" #undef IMX233_INCLUDE -#endif /* __SELECT__BCH__H__ */ +#endif /* __HEADERGEN_BCH_H__*/ diff --git a/firmware/target/arm/imx233/regs/clkctrl.h b/firmware/target/arm/imx233/regs/clkctrl.h new file mode 100644 index 0000000000..8868495ec2 --- /dev/null +++ b/firmware/target/arm/imx233/regs/clkctrl.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_CLKCTRL_H__ +#define __HEADERGEN_CLKCTRL_H__ + +#include "macro.h" + +#define STMP3600_INCLUDE "stmp3600/clkctrl.h" +#define STMP3700_INCLUDE "stmp3700/clkctrl.h" +#define IMX233_INCLUDE "imx233/clkctrl.h" + +#include "select.h" + +#undef STMP3600_INCLUDE +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_CLKCTRL_H__*/ diff --git a/firmware/target/arm/imx233/regs/regs-anatop.h b/firmware/target/arm/imx233/regs/dacdma.h index 4072dc77d6..f0c42e88f1 100644 --- a/firmware/target/arm/imx233/regs/regs-anatop.h +++ b/firmware/target/arm/imx233/regs/dacdma.h @@ -6,10 +6,9 @@ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. - * headergen version: 2.1.8 - * XML versions: stmp3600:2.3.0 + * headergen version: 3.0.0 * - * Copyright (C) 2013 by Amaury Pouly + * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,14 +19,15 @@ * KIND, either express or implied. * ****************************************************************************/ -#ifndef __SELECT__ANATOP__H__ -#define __SELECT__ANATOP__H__ -#include "regs-macro.h" +#ifndef __HEADERGEN_DACDMA_H__ +#define __HEADERGEN_DACDMA_H__ -#define STMP3600_INCLUDE "stmp3600/regs-anatop.h" +#include "macro.h" -#include "regs-select.h" +#define STMP3600_INCLUDE "stmp3600/dacdma.h" + +#include "select.h" #undef STMP3600_INCLUDE -#endif /* __SELECT__ANATOP__H__ */ +#endif /* __HEADERGEN_DACDMA_H__*/ diff --git a/firmware/target/arm/imx233/regs/dcp.h b/firmware/target/arm/imx233/regs/dcp.h new file mode 100644 index 0000000000..5b72092248 --- /dev/null +++ b/firmware/target/arm/imx233/regs/dcp.h @@ -0,0 +1,35 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_DCP_H__ +#define __HEADERGEN_DCP_H__ + +#include "macro.h" + +#define STMP3700_INCLUDE "stmp3700/dcp.h" +#define IMX233_INCLUDE "imx233/dcp.h" + +#include "select.h" + +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_DCP_H__*/ diff --git a/firmware/target/arm/imx233/regs/digctl.h b/firmware/target/arm/imx233/regs/digctl.h new file mode 100644 index 0000000000..27ee2c5b2e --- /dev/null +++ b/firmware/target/arm/imx233/regs/digctl.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_DIGCTL_H__ +#define __HEADERGEN_DIGCTL_H__ + +#include "macro.h" + +#define STMP3600_INCLUDE "stmp3600/digctl.h" +#define STMP3700_INCLUDE "stmp3700/digctl.h" +#define IMX233_INCLUDE "imx233/digctl.h" + +#include "select.h" + +#undef STMP3600_INCLUDE +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_DIGCTL_H__*/ diff --git a/firmware/target/arm/imx233/regs/dram.h b/firmware/target/arm/imx233/regs/dram.h new file mode 100644 index 0000000000..dbd700ed9f --- /dev/null +++ b/firmware/target/arm/imx233/regs/dram.h @@ -0,0 +1,35 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_DRAM_H__ +#define __HEADERGEN_DRAM_H__ + +#include "macro.h" + +#define STMP3700_INCLUDE "stmp3700/dram.h" +#define IMX233_INCLUDE "imx233/dram.h" + +#include "select.h" + +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_DRAM_H__*/ diff --git a/firmware/target/arm/imx233/regs/regs-dram.h b/firmware/target/arm/imx233/regs/dri.h index ab9ff93624..7b72d85e7b 100644 --- a/firmware/target/arm/imx233/regs/regs-dram.h +++ b/firmware/target/arm/imx233/regs/dri.h @@ -6,10 +6,9 @@ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. - * headergen version: 2.1.8 - * XML versions: stmp3700:3.2.0 imx233:3.2.0 + * headergen version: 3.0.0 * - * Copyright (C) 2013 by Amaury Pouly + * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,16 +19,19 @@ * KIND, either express or implied. * ****************************************************************************/ -#ifndef __SELECT__DRAM__H__ -#define __SELECT__DRAM__H__ -#include "regs-macro.h" +#ifndef __HEADERGEN_DRI_H__ +#define __HEADERGEN_DRI_H__ -#define STMP3700_INCLUDE "stmp3700/regs-dram.h" -#define IMX233_INCLUDE "imx233/regs-dram.h" +#include "macro.h" -#include "regs-select.h" +#define STMP3600_INCLUDE "stmp3600/dri.h" +#define STMP3700_INCLUDE "stmp3700/dri.h" +#define IMX233_INCLUDE "imx233/dri.h" +#include "select.h" + +#undef STMP3600_INCLUDE #undef STMP3700_INCLUDE #undef IMX233_INCLUDE -#endif /* __SELECT__DRAM__H__ */ +#endif /* __HEADERGEN_DRI_H__*/ diff --git a/firmware/target/arm/imx233/regs/ecc8.h b/firmware/target/arm/imx233/regs/ecc8.h new file mode 100644 index 0000000000..66ff437f06 --- /dev/null +++ b/firmware/target/arm/imx233/regs/ecc8.h @@ -0,0 +1,35 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_ECC8_H__ +#define __HEADERGEN_ECC8_H__ + +#include "macro.h" + +#define STMP3700_INCLUDE "stmp3700/ecc8.h" +#define IMX233_INCLUDE "imx233/ecc8.h" + +#include "select.h" + +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_ECC8_H__*/ diff --git a/firmware/target/arm/imx233/regs/regs-ecc8.h b/firmware/target/arm/imx233/regs/emi.h index b8be14b90c..969bcafae4 100644 --- a/firmware/target/arm/imx233/regs/regs-ecc8.h +++ b/firmware/target/arm/imx233/regs/emi.h @@ -6,10 +6,9 @@ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. - * headergen version: 2.1.8 - * XML versions: stmp3700:3.2.0 imx233:3.2.0 + * headergen version: 3.0.0 * - * Copyright (C) 2013 by Amaury Pouly + * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,16 +19,19 @@ * KIND, either express or implied. * ****************************************************************************/ -#ifndef __SELECT__ECC8__H__ -#define __SELECT__ECC8__H__ -#include "regs-macro.h" +#ifndef __HEADERGEN_EMI_H__ +#define __HEADERGEN_EMI_H__ -#define STMP3700_INCLUDE "stmp3700/regs-ecc8.h" -#define IMX233_INCLUDE "imx233/regs-ecc8.h" +#include "macro.h" -#include "regs-select.h" +#define STMP3600_INCLUDE "stmp3600/emi.h" +#define STMP3700_INCLUDE "stmp3700/emi.h" +#define IMX233_INCLUDE "imx233/emi.h" +#include "select.h" + +#undef STMP3600_INCLUDE #undef STMP3700_INCLUDE #undef IMX233_INCLUDE -#endif /* __SELECT__ECC8__H__ */ +#endif /* __HEADERGEN_EMI_H__*/ diff --git a/firmware/target/arm/imx233/regs/regs-gpiomon.h b/firmware/target/arm/imx233/regs/gpiomon.h index 1a04fa45fb..1336d6cc77 100644 --- a/firmware/target/arm/imx233/regs/regs-gpiomon.h +++ b/firmware/target/arm/imx233/regs/gpiomon.h @@ -6,10 +6,9 @@ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. - * headergen version: 2.1.8 - * XML versions: stmp3700:3.2.0 + * headergen version: 3.0.0 * - * Copyright (C) 2013 by Amaury Pouly + * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,14 +19,15 @@ * KIND, either express or implied. * ****************************************************************************/ -#ifndef __SELECT__GPIOMON__H__ -#define __SELECT__GPIOMON__H__ -#include "regs-macro.h" +#ifndef __HEADERGEN_GPIOMON_H__ +#define __HEADERGEN_GPIOMON_H__ -#define STMP3700_INCLUDE "stmp3700/regs-gpiomon.h" +#include "macro.h" -#include "regs-select.h" +#define STMP3700_INCLUDE "stmp3700/gpiomon.h" + +#include "select.h" #undef STMP3700_INCLUDE -#endif /* __SELECT__GPIOMON__H__ */ +#endif /* __HEADERGEN_GPIOMON_H__*/ diff --git a/firmware/target/arm/imx233/regs/gpmi.h b/firmware/target/arm/imx233/regs/gpmi.h new file mode 100644 index 0000000000..7b234d12d2 --- /dev/null +++ b/firmware/target/arm/imx233/regs/gpmi.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_GPMI_H__ +#define __HEADERGEN_GPMI_H__ + +#include "macro.h" + +#define STMP3600_INCLUDE "stmp3600/gpmi.h" +#define STMP3700_INCLUDE "stmp3700/gpmi.h" +#define IMX233_INCLUDE "imx233/gpmi.h" + +#include "select.h" + +#undef STMP3600_INCLUDE +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_GPMI_H__*/ diff --git a/firmware/target/arm/imx233/regs/regs-dacdma.h b/firmware/target/arm/imx233/regs/hwecc.h index 0b36addc9e..d7bc8390fb 100644 --- a/firmware/target/arm/imx233/regs/regs-dacdma.h +++ b/firmware/target/arm/imx233/regs/hwecc.h @@ -6,10 +6,9 @@ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. - * headergen version: 2.1.8 - * XML versions: stmp3600:2.3.0 + * headergen version: 3.0.0 * - * Copyright (C) 2013 by Amaury Pouly + * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,14 +19,15 @@ * KIND, either express or implied. * ****************************************************************************/ -#ifndef __SELECT__DACDMA__H__ -#define __SELECT__DACDMA__H__ -#include "regs-macro.h" +#ifndef __HEADERGEN_HWECC_H__ +#define __HEADERGEN_HWECC_H__ -#define STMP3600_INCLUDE "stmp3600/regs-dacdma.h" +#include "macro.h" -#include "regs-select.h" +#define STMP3600_INCLUDE "stmp3600/hwecc.h" + +#include "select.h" #undef STMP3600_INCLUDE -#endif /* __SELECT__DACDMA__H__ */ +#endif /* __HEADERGEN_HWECC_H__*/ diff --git a/firmware/target/arm/imx233/regs/regs-ocotp.h b/firmware/target/arm/imx233/regs/i2c.h index 14ded64ea3..7ec29a13bb 100644 --- a/firmware/target/arm/imx233/regs/regs-ocotp.h +++ b/firmware/target/arm/imx233/regs/i2c.h @@ -6,10 +6,9 @@ * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. - * headergen version: 2.1.8 - * XML versions: stmp3700:3.2.0 imx233:3.2.0 + * headergen version: 3.0.0 * - * Copyright (C) 2013 by Amaury Pouly + * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -20,16 +19,19 @@ * KIND, either express or implied. * ****************************************************************************/ -#ifndef __SELECT__OCOTP__H__ -#define __SELECT__OCOTP__H__ -#include "regs-macro.h" +#ifndef __HEADERGEN_I2C_H__ +#define __HEADERGEN_I2C_H__ -#define STMP3700_INCLUDE "stmp3700/regs-ocotp.h" -#define IMX233_INCLUDE "imx233/regs-ocotp.h" +#include "macro.h" -#include "regs-select.h" +#define STMP3600_INCLUDE "stmp3600/i2c.h" +#define STMP3700_INCLUDE "stmp3700/i2c.h" +#define IMX233_INCLUDE "imx233/i2c.h" +#include "select.h" + +#undef STMP3600_INCLUDE #undef STMP3700_INCLUDE #undef IMX233_INCLUDE -#endif /* __SELECT__OCOTP__H__ */ +#endif /* __HEADERGEN_I2C_H__*/ diff --git a/firmware/target/arm/imx233/regs/icoll.h b/firmware/target/arm/imx233/regs/icoll.h new file mode 100644 index 0000000000..5d945b95bd --- /dev/null +++ b/firmware/target/arm/imx233/regs/icoll.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_ICOLL_H__ +#define __HEADERGEN_ICOLL_H__ + +#include "macro.h" + +#define STMP3600_INCLUDE "stmp3600/icoll.h" +#define STMP3700_INCLUDE "stmp3700/icoll.h" +#define IMX233_INCLUDE "imx233/icoll.h" + +#include "select.h" + +#undef STMP3600_INCLUDE +#undef STMP3700_INCLUDE +#undef IMX233_INCLUDE + +#endif /* __HEADERGEN_ICOLL_H__*/ diff --git a/firmware/target/arm/imx233/regs/imx233/apbh.h b/firmware/target/arm/imx233/regs/imx233/apbh.h new file mode 100644 index 0000000000..9500ff086e --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/apbh.h @@ -0,0 +1,554 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * imx233 version: 2.4.0 + * imx233 authors: Amaury Pouly + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_IMX233_APBH_H__ +#define __HEADERGEN_IMX233_APBH_H__ + +#define HW_APBH_CTRL0 HW(APBH_CTRL0) +#define HWA_APBH_CTRL0 (0x80004000 + 0x0) +#define HWT_APBH_CTRL0 HWIO_32_RW +#define HWN_APBH_CTRL0 APBH_CTRL0 +#define HWI_APBH_CTRL0 +#define HW_APBH_CTRL0_SET HW(APBH_CTRL0_SET) +#define HWA_APBH_CTRL0_SET (HWA_APBH_CTRL0 + 0x4) +#define HWT_APBH_CTRL0_SET HWIO_32_WO +#define HWN_APBH_CTRL0_SET APBH_CTRL0 +#define HWI_APBH_CTRL0_SET +#define HW_APBH_CTRL0_CLR HW(APBH_CTRL0_CLR) +#define HWA_APBH_CTRL0_CLR (HWA_APBH_CTRL0 + 0x8) +#define HWT_APBH_CTRL0_CLR HWIO_32_WO +#define HWN_APBH_CTRL0_CLR APBH_CTRL0 +#define HWI_APBH_CTRL0_CLR +#define HW_APBH_CTRL0_TOG HW(APBH_CTRL0_TOG) +#define HWA_APBH_CTRL0_TOG (HWA_APBH_CTRL0 + 0xc) +#define HWT_APBH_CTRL0_TOG HWIO_32_WO +#define HWN_APBH_CTRL0_TOG APBH_CTRL0 +#define HWI_APBH_CTRL0_TOG +#define BP_APBH_CTRL0_SFTRST 31 +#define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BF_APBH_CTRL0_SFTRST(v) (((v) & 0x1) << 31) +#define BFM_APBH_CTRL0_SFTRST(v) BM_APBH_CTRL0_SFTRST +#define BF_APBH_CTRL0_SFTRST_V(e) BF_APBH_CTRL0_SFTRST(BV_APBH_CTRL0_SFTRST__##e) +#define BFM_APBH_CTRL0_SFTRST_V(v) BM_APBH_CTRL0_SFTRST +#define BP_APBH_CTRL0_CLKGATE 30 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BF_APBH_CTRL0_CLKGATE(v) (((v) & 0x1) << 30) +#define BFM_APBH_CTRL0_CLKGATE(v) BM_APBH_CTRL0_CLKGATE +#define BF_APBH_CTRL0_CLKGATE_V(e) BF_APBH_CTRL0_CLKGATE(BV_APBH_CTRL0_CLKGATE__##e) +#define BFM_APBH_CTRL0_CLKGATE_V(v) BM_APBH_CTRL0_CLKGATE +#define BP_APBH_CTRL0_AHB_BURST8_EN 29 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BF_APBH_CTRL0_AHB_BURST8_EN(v) (((v) & 0x1) << 29) +#define BFM_APBH_CTRL0_AHB_BURST8_EN(v) BM_APBH_CTRL0_AHB_BURST8_EN +#define BF_APBH_CTRL0_AHB_BURST8_EN_V(e) BF_APBH_CTRL0_AHB_BURST8_EN(BV_APBH_CTRL0_AHB_BURST8_EN__##e) +#define BFM_APBH_CTRL0_AHB_BURST8_EN_V(v) BM_APBH_CTRL0_AHB_BURST8_EN +#define BP_APBH_CTRL0_APB_BURST4_EN 28 +#define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000 +#define BF_APBH_CTRL0_APB_BURST4_EN(v) (((v) & 0x1) << 28) +#define BFM_APBH_CTRL0_APB_BURST4_EN(v) BM_APBH_CTRL0_APB_BURST4_EN +#define BF_APBH_CTRL0_APB_BURST4_EN_V(e) BF_APBH_CTRL0_APB_BURST4_EN(BV_APBH_CTRL0_APB_BURST4_EN__##e) +#define BFM_APBH_CTRL0_APB_BURST4_EN_V(v) BM_APBH_CTRL0_APB_BURST4_EN +#define BP_APBH_CTRL0_RSVD0 24 +#define BM_APBH_CTRL0_RSVD0 0xf000000 +#define BF_APBH_CTRL0_RSVD0(v) (((v) & 0xf) << 24) +#define BFM_APBH_CTRL0_RSVD0(v) BM_APBH_CTRL0_RSVD0 +#define BF_APBH_CTRL0_RSVD0_V(e) BF_APBH_CTRL0_RSVD0(BV_APBH_CTRL0_RSVD0__##e) +#define BFM_APBH_CTRL0_RSVD0_V(v) BM_APBH_CTRL0_RSVD0 +#define BP_APBH_CTRL0_RESET_CHANNEL 16 +#define BM_APBH_CTRL0_RESET_CHANNEL 0xff0000 +#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1 0x2 +#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2 0x4 +#define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x40 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x80 +#define BF_APBH_CTRL0_RESET_CHANNEL(v) (((v) & 0xff) << 16) +#define BFM_APBH_CTRL0_RESET_CHANNEL(v) BM_APBH_CTRL0_RESET_CHANNEL +#define BF_APBH_CTRL0_RESET_CHANNEL_V(e) BF_APBH_CTRL0_RESET_CHANNEL(BV_APBH_CTRL0_RESET_CHANNEL__##e) +#define BFM_APBH_CTRL0_RESET_CHANNEL_V(v) BM_APBH_CTRL0_RESET_CHANNEL +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0xff00 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x2 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x4 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x40 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x80 +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) (((v) & 0xff) << 8) +#define BFM_APBH_CTRL0_CLKGATE_CHANNEL(v) BM_APBH_CTRL0_CLKGATE_CHANNEL +#define BF_APBH_CTRL0_CLKGATE_CHANNEL_V(e) BF_APBH_CTRL0_CLKGATE_CHANNEL(BV_APBH_CTRL0_CLKGATE_CHANNEL__##e) +#define BFM_APBH_CTRL0_CLKGATE_CHANNEL_V(v) BM_APBH_CTRL0_CLKGATE_CHANNEL +#define BP_APBH_CTRL0_FREEZE_CHANNEL 0 +#define BM_APBH_CTRL0_FREEZE_CHANNEL 0xff +#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1 0x2 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2 0x4 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x40 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x80 +#define BF_APBH_CTRL0_FREEZE_CHANNEL(v) (((v) & 0xff) << 0) +#define BFM_APBH_CTRL0_FREEZE_CHANNEL(v) BM_APBH_CTRL0_FREEZE_CHANNEL +#define BF_APBH_CTRL0_FREEZE_CHANNEL_V(e) BF_APBH_CTRL0_FREEZE_CHANNEL(BV_APBH_CTRL0_FREEZE_CHANNEL__##e) +#define BFM_APBH_CTRL0_FREEZE_CHANNEL_V(v) BM_APBH_CTRL0_FREEZE_CHANNEL + +#define HW_APBH_CTRL1 HW(APBH_CTRL1) +#define HWA_APBH_CTRL1 (0x80004000 + 0x10) +#define HWT_APBH_CTRL1 HWIO_32_RW +#define HWN_APBH_CTRL1 APBH_CTRL1 +#define HWI_APBH_CTRL1 +#define HW_APBH_CTRL1_SET HW(APBH_CTRL1_SET) +#define HWA_APBH_CTRL1_SET (HWA_APBH_CTRL1 + 0x4) +#define HWT_APBH_CTRL1_SET HWIO_32_WO +#define HWN_APBH_CTRL1_SET APBH_CTRL1 +#define HWI_APBH_CTRL1_SET +#define HW_APBH_CTRL1_CLR HW(APBH_CTRL1_CLR) +#define HWA_APBH_CTRL1_CLR (HWA_APBH_CTRL1 + 0x8) +#define HWT_APBH_CTRL1_CLR HWIO_32_WO +#define HWN_APBH_CTRL1_CLR APBH_CTRL1 +#define HWI_APBH_CTRL1_CLR +#define HW_APBH_CTRL1_TOG HW(APBH_CTRL1_TOG) +#define HWA_APBH_CTRL1_TOG (HWA_APBH_CTRL1 + 0xc) +#define HWT_APBH_CTRL1_TOG HWIO_32_WO +#define HWN_APBH_CTRL1_TOG APBH_CTRL1 +#define HWI_APBH_CTRL1_TOG +#define BP_APBH_CTRL1_RSVD1 24 +#define BM_APBH_CTRL1_RSVD1 0xff000000 +#define BF_APBH_CTRL1_RSVD1(v) (((v) & 0xff) << 24) +#define BFM_APBH_CTRL1_RSVD1(v) BM_APBH_CTRL1_RSVD1 +#define BF_APBH_CTRL1_RSVD1_V(e) BF_APBH_CTRL1_RSVD1(BV_APBH_CTRL1_RSVD1__##e) +#define BFM_APBH_CTRL1_RSVD1_V(v) BM_APBH_CTRL1_RSVD1 +#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 16 +#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN 0xff0000 +#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) & 0xff) << 16) +#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(v) BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN +#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(e) BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN__##e) +#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_V(v) BM_APBH_CTRL1_CH_CMDCMPLT_IRQ_EN +#define BP_APBH_CTRL1_RSVD0 8 +#define BM_APBH_CTRL1_RSVD0 0xff00 +#define BF_APBH_CTRL1_RSVD0(v) (((v) & 0xff) << 8) +#define BFM_APBH_CTRL1_RSVD0(v) BM_APBH_CTRL1_RSVD0 +#define BF_APBH_CTRL1_RSVD0_V(e) BF_APBH_CTRL1_RSVD0(BV_APBH_CTRL1_RSVD0__##e) +#define BFM_APBH_CTRL1_RSVD0_V(v) BM_APBH_CTRL1_RSVD0 +#define BP_APBH_CTRL1_CH_CMDCMPLT_IRQ 0 +#define BM_APBH_CTRL1_CH_CMDCMPLT_IRQ 0xff +#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) & 0xff) << 0) +#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ(v) BM_APBH_CTRL1_CH_CMDCMPLT_IRQ +#define BF_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(e) BF_APBH_CTRL1_CH_CMDCMPLT_IRQ(BV_APBH_CTRL1_CH_CMDCMPLT_IRQ__##e) +#define BFM_APBH_CTRL1_CH_CMDCMPLT_IRQ_V(v) BM_APBH_CTRL1_CH_CMDCMPLT_IRQ + +#define HW_APBH_CTRL2 HW(APBH_CTRL2) +#define HWA_APBH_CTRL2 (0x80004000 + 0x20) +#define HWT_APBH_CTRL2 HWIO_32_RW +#define HWN_APBH_CTRL2 APBH_CTRL2 +#define HWI_APBH_CTRL2 +#define HW_APBH_CTRL2_SET HW(APBH_CTRL2_SET) +#define HWA_APBH_CTRL2_SET (HWA_APBH_CTRL2 + 0x4) +#define HWT_APBH_CTRL2_SET HWIO_32_WO +#define HWN_APBH_CTRL2_SET APBH_CTRL2 +#define HWI_APBH_CTRL2_SET +#define HW_APBH_CTRL2_CLR HW(APBH_CTRL2_CLR) +#define HWA_APBH_CTRL2_CLR (HWA_APBH_CTRL2 + 0x8) +#define HWT_APBH_CTRL2_CLR HWIO_32_WO +#define HWN_APBH_CTRL2_CLR APBH_CTRL2 +#define HWI_APBH_CTRL2_CLR +#define HW_APBH_CTRL2_TOG HW(APBH_CTRL2_TOG) +#define HWA_APBH_CTRL2_TOG (HWA_APBH_CTRL2 + 0xc) +#define HWT_APBH_CTRL2_TOG HWIO_32_WO +#define HWN_APBH_CTRL2_TOG APBH_CTRL2 +#define HWI_APBH_CTRL2_TOG +#define BP_APBH_CTRL2_RSVD1 24 +#define BM_APBH_CTRL2_RSVD1 0xff000000 +#define BF_APBH_CTRL2_RSVD1(v) (((v) & 0xff) << 24) +#define BFM_APBH_CTRL2_RSVD1(v) BM_APBH_CTRL2_RSVD1 +#define BF_APBH_CTRL2_RSVD1_V(e) BF_APBH_CTRL2_RSVD1(BV_APBH_CTRL2_RSVD1__##e) +#define BFM_APBH_CTRL2_RSVD1_V(v) BM_APBH_CTRL2_RSVD1 +#define BP_APBH_CTRL2_CH_ERROR_STATUS 16 +#define BM_APBH_CTRL2_CH_ERROR_STATUS 0xff0000 +#define BF_APBH_CTRL2_CH_ERROR_STATUS(v) (((v) & 0xff) << 16) +#define BFM_APBH_CTRL2_CH_ERROR_STATUS(v) BM_APBH_CTRL2_CH_ERROR_STATUS +#define BF_APBH_CTRL2_CH_ERROR_STATUS_V(e) BF_APBH_CTRL2_CH_ERROR_STATUS(BV_APBH_CTRL2_CH_ERROR_STATUS__##e) +#define BFM_APBH_CTRL2_CH_ERROR_STATUS_V(v) BM_APBH_CTRL2_CH_ERROR_STATUS +#define BP_APBH_CTRL2_RSVD0 8 +#define BM_APBH_CTRL2_RSVD0 0xff00 +#define BF_APBH_CTRL2_RSVD0(v) (((v) & 0xff) << 8) +#define BFM_APBH_CTRL2_RSVD0(v) BM_APBH_CTRL2_RSVD0 +#define BF_APBH_CTRL2_RSVD0_V(e) BF_APBH_CTRL2_RSVD0(BV_APBH_CTRL2_RSVD0__##e) +#define BFM_APBH_CTRL2_RSVD0_V(v) BM_APBH_CTRL2_RSVD0 +#define BP_APBH_CTRL2_CH_ERROR_IRQ 0 +#define BM_APBH_CTRL2_CH_ERROR_IRQ 0xff +#define BF_APBH_CTRL2_CH_ERROR_IRQ(v) (((v) & 0xff) << 0) +#define BFM_APBH_CTRL2_CH_ERROR_IRQ(v) BM_APBH_CTRL2_CH_ERROR_IRQ +#define BF_APBH_CTRL2_CH_ERROR_IRQ_V(e) BF_APBH_CTRL2_CH_ERROR_IRQ(BV_APBH_CTRL2_CH_ERROR_IRQ__##e) +#define BFM_APBH_CTRL2_CH_ERROR_IRQ_V(v) BM_APBH_CTRL2_CH_ERROR_IRQ + +#define HW_APBH_DEVSEL HW(APBH_DEVSEL) +#define HWA_APBH_DEVSEL (0x80004000 + 0x30) +#define HWT_APBH_DEVSEL HWIO_32_RW +#define HWN_APBH_DEVSEL APBH_DEVSEL +#define HWI_APBH_DEVSEL +#define BP_APBH_DEVSEL_CH7 28 +#define BM_APBH_DEVSEL_CH7 0xf0000000 +#define BF_APBH_DEVSEL_CH7(v) (((v) & 0xf) << 28) +#define BFM_APBH_DEVSEL_CH7(v) BM_APBH_DEVSEL_CH7 +#define BF_APBH_DEVSEL_CH7_V(e) BF_APBH_DEVSEL_CH7(BV_APBH_DEVSEL_CH7__##e) +#define BFM_APBH_DEVSEL_CH7_V(v) BM_APBH_DEVSEL_CH7 +#define BP_APBH_DEVSEL_CH6 24 +#define BM_APBH_DEVSEL_CH6 0xf000000 +#define BF_APBH_DEVSEL_CH6(v) (((v) & 0xf) << 24) +#define BFM_APBH_DEVSEL_CH6(v) BM_APBH_DEVSEL_CH6 +#define BF_APBH_DEVSEL_CH6_V(e) BF_APBH_DEVSEL_CH6(BV_APBH_DEVSEL_CH6__##e) +#define BFM_APBH_DEVSEL_CH6_V(v) BM_APBH_DEVSEL_CH6 +#define BP_APBH_DEVSEL_CH5 20 +#define BM_APBH_DEVSEL_CH5 0xf00000 +#define BF_APBH_DEVSEL_CH5(v) (((v) & 0xf) << 20) +#define BFM_APBH_DEVSEL_CH5(v) BM_APBH_DEVSEL_CH5 +#define BF_APBH_DEVSEL_CH5_V(e) BF_APBH_DEVSEL_CH5(BV_APBH_DEVSEL_CH5__##e) +#define BFM_APBH_DEVSEL_CH5_V(v) BM_APBH_DEVSEL_CH5 +#define BP_APBH_DEVSEL_CH4 16 +#define BM_APBH_DEVSEL_CH4 0xf0000 +#define BF_APBH_DEVSEL_CH4(v) (((v) & 0xf) << 16) +#define BFM_APBH_DEVSEL_CH4(v) BM_APBH_DEVSEL_CH4 +#define BF_APBH_DEVSEL_CH4_V(e) BF_APBH_DEVSEL_CH4(BV_APBH_DEVSEL_CH4__##e) +#define BFM_APBH_DEVSEL_CH4_V(v) BM_APBH_DEVSEL_CH4 +#define BP_APBH_DEVSEL_CH3 12 +#define BM_APBH_DEVSEL_CH3 0xf000 +#define BF_APBH_DEVSEL_CH3(v) (((v) & 0xf) << 12) +#define BFM_APBH_DEVSEL_CH3(v) BM_APBH_DEVSEL_CH3 +#define BF_APBH_DEVSEL_CH3_V(e) BF_APBH_DEVSEL_CH3(BV_APBH_DEVSEL_CH3__##e) +#define BFM_APBH_DEVSEL_CH3_V(v) BM_APBH_DEVSEL_CH3 +#define BP_APBH_DEVSEL_CH2 8 +#define BM_APBH_DEVSEL_CH2 0xf00 +#define BF_APBH_DEVSEL_CH2(v) (((v) & 0xf) << 8) +#define BFM_APBH_DEVSEL_CH2(v) BM_APBH_DEVSEL_CH2 +#define BF_APBH_DEVSEL_CH2_V(e) BF_APBH_DEVSEL_CH2(BV_APBH_DEVSEL_CH2__##e) +#define BFM_APBH_DEVSEL_CH2_V(v) BM_APBH_DEVSEL_CH2 +#define BP_APBH_DEVSEL_CH1 4 +#define BM_APBH_DEVSEL_CH1 0xf0 +#define BF_APBH_DEVSEL_CH1(v) (((v) & 0xf) << 4) +#define BFM_APBH_DEVSEL_CH1(v) BM_APBH_DEVSEL_CH1 +#define BF_APBH_DEVSEL_CH1_V(e) BF_APBH_DEVSEL_CH1(BV_APBH_DEVSEL_CH1__##e) +#define BFM_APBH_DEVSEL_CH1_V(v) BM_APBH_DEVSEL_CH1 +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0xf +#define BF_APBH_DEVSEL_CH0(v) (((v) & 0xf) << 0) +#define BFM_APBH_DEVSEL_CH0(v) BM_APBH_DEVSEL_CH0 +#define BF_APBH_DEVSEL_CH0_V(e) BF_APBH_DEVSEL_CH0(BV_APBH_DEVSEL_CH0__##e) +#define BFM_APBH_DEVSEL_CH0_V(v) BM_APBH_DEVSEL_CH0 + +#define HW_APBH_CHn_CURCMDAR(_n1) HW(APBH_CHn_CURCMDAR(_n1)) +#define HWA_APBH_CHn_CURCMDAR(_n1) (0x80004000 + 0x40 + (_n1) * 0x70) +#define HWT_APBH_CHn_CURCMDAR(_n1) HWIO_32_RW +#define HWN_APBH_CHn_CURCMDAR(_n1) APBH_CHn_CURCMDAR +#define HWI_APBH_CHn_CURCMDAR(_n1) (_n1) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xffffffff +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR(v) BM_APBH_CHn_CURCMDAR_CMD_ADDR +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR_V(e) BF_APBH_CHn_CURCMDAR_CMD_ADDR(BV_APBH_CHn_CURCMDAR_CMD_ADDR__##e) +#define BFM_APBH_CHn_CURCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_CURCMDAR_CMD_ADDR + +#define HW_APBH_CHn_NXTCMDAR(_n1) HW(APBH_CHn_NXTCMDAR(_n1)) +#define HWA_APBH_CHn_NXTCMDAR(_n1) (0x80004000 + 0x50 + (_n1) * 0x70) +#define HWT_APBH_CHn_NXTCMDAR(_n1) HWIO_32_RW +#define HWN_APBH_CHn_NXTCMDAR(_n1) APBH_CHn_NXTCMDAR +#define HWI_APBH_CHn_NXTCMDAR(_n1) (_n1) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xffffffff +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR(v) BM_APBH_CHn_NXTCMDAR_CMD_ADDR +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR_V(e) BF_APBH_CHn_NXTCMDAR_CMD_ADDR(BV_APBH_CHn_NXTCMDAR_CMD_ADDR__##e) +#define BFM_APBH_CHn_NXTCMDAR_CMD_ADDR_V(v) BM_APBH_CHn_NXTCMDAR_CMD_ADDR + +#define HW_APBH_CHn_CMD(_n1) HW(APBH_CHn_CMD(_n1)) +#define HWA_APBH_CHn_CMD(_n1) (0x80004000 + 0x60 + (_n1) * 0x70) +#define HWT_APBH_CHn_CMD(_n1) HWIO_32_RW +#define HWN_APBH_CHn_CMD(_n1) APBH_CHn_CMD +#define HWI_APBH_CHn_CMD(_n1) (_n1) +#define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xffff0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) (((v) & 0xffff) << 16) +#define BFM_APBH_CHn_CMD_XFER_COUNT(v) BM_APBH_CHn_CMD_XFER_COUNT +#define BF_APBH_CHn_CMD_XFER_COUNT_V(e) BF_APBH_CHn_CMD_XFER_COUNT(BV_APBH_CHn_CMD_XFER_COUNT__##e) +#define BFM_APBH_CHn_CMD_XFER_COUNT_V(v) BM_APBH_CHn_CMD_XFER_COUNT +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0xf000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) (((v) & 0xf) << 12) +#define BFM_APBH_CHn_CMD_CMDWORDS(v) BM_APBH_CHn_CMD_CMDWORDS +#define BF_APBH_CHn_CMD_CMDWORDS_V(e) BF_APBH_CHn_CMD_CMDWORDS(BV_APBH_CHn_CMD_CMDWORDS__##e) +#define BFM_APBH_CHn_CMD_CMDWORDS_V(v) BM_APBH_CHn_CMD_CMDWORDS +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0xe00 +#define BF_APBH_CHn_CMD_RSVD1(v) (((v) & 0x7) << 9) +#define BFM_APBH_CHn_CMD_RSVD1(v) BM_APBH_CHn_CMD_RSVD1 +#define BF_APBH_CHn_CMD_RSVD1_V(e) BF_APBH_CHn_CMD_RSVD1(BV_APBH_CHn_CMD_RSVD1__##e) +#define BFM_APBH_CHn_CMD_RSVD1_V(v) BM_APBH_CHn_CMD_RSVD1 +#define BP_APBH_CHn_CMD_HALTONTERMINATE 8 +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x100 +#define BF_APBH_CHn_CMD_HALTONTERMINATE(v) (((v) & 0x1) << 8) +#define BFM_APBH_CHn_CMD_HALTONTERMINATE(v) BM_APBH_CHn_CMD_HALTONTERMINATE +#define BF_APBH_CHn_CMD_HALTONTERMINATE_V(e) BF_APBH_CHn_CMD_HALTONTERMINATE(BV_APBH_CHn_CMD_HALTONTERMINATE__##e) +#define BFM_APBH_CHn_CMD_HALTONTERMINATE_V(v) BM_APBH_CHn_CMD_HALTONTERMINATE +#define BP_APBH_CHn_CMD_WAIT4ENDCMD 7 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x80 +#define BF_APBH_CHn_CMD_WAIT4ENDCMD(v) (((v) & 0x1) << 7) +#define BFM_APBH_CHn_CMD_WAIT4ENDCMD(v) BM_APBH_CHn_CMD_WAIT4ENDCMD +#define BF_APBH_CHn_CMD_WAIT4ENDCMD_V(e) BF_APBH_CHn_CMD_WAIT4ENDCMD(BV_APBH_CHn_CMD_WAIT4ENDCMD__##e) +#define BFM_APBH_CHn_CMD_WAIT4ENDCMD_V(v) BM_APBH_CHn_CMD_WAIT4ENDCMD +#define BP_APBH_CHn_CMD_SEMAPHORE 6 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x40 +#define BF_APBH_CHn_CMD_SEMAPHORE(v) (((v) & 0x1) << 6) +#define BFM_APBH_CHn_CMD_SEMAPHORE(v) BM_APBH_CHn_CMD_SEMAPHORE +#define BF_APBH_CHn_CMD_SEMAPHORE_V(e) BF_APBH_CHn_CMD_SEMAPHORE(BV_APBH_CHn_CMD_SEMAPHORE__##e) +#define BFM_APBH_CHn_CMD_SEMAPHORE_V(v) BM_APBH_CHn_CMD_SEMAPHORE +#define BP_APBH_CHn_CMD_NANDWAIT4READY 5 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x20 +#define BF_APBH_CHn_CMD_NANDWAIT4READY(v) (((v) & 0x1) << 5) +#define BFM_APBH_CHn_CMD_NANDWAIT4READY(v) BM_APBH_CHn_CMD_NANDWAIT4READY +#define BF_APBH_CHn_CMD_NANDWAIT4READY_V(e) BF_APBH_CHn_CMD_NANDWAIT4READY(BV_APBH_CHn_CMD_NANDWAIT4READY__##e) +#define BFM_APBH_CHn_CMD_NANDWAIT4READY_V(v) BM_APBH_CHn_CMD_NANDWAIT4READY +#define BP_APBH_CHn_CMD_NANDLOCK 4 +#define BM_APBH_CHn_CMD_NANDLOCK 0x10 +#define BF_APBH_CHn_CMD_NANDLOCK(v) (((v) & 0x1) << 4) +#define BFM_APBH_CHn_CMD_NANDLOCK(v) BM_APBH_CHn_CMD_NANDLOCK +#define BF_APBH_CHn_CMD_NANDLOCK_V(e) BF_APBH_CHn_CMD_NANDLOCK(BV_APBH_CHn_CMD_NANDLOCK__##e) +#define BFM_APBH_CHn_CMD_NANDLOCK_V(v) BM_APBH_CHn_CMD_NANDLOCK +#define BP_APBH_CHn_CMD_IRQONCMPLT 3 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x8 +#define BF_APBH_CHn_CMD_IRQONCMPLT(v) (((v) & 0x1) << 3) +#define BFM_APBH_CHn_CMD_IRQONCMPLT(v) BM_APBH_CHn_CMD_IRQONCMPLT +#define BF_APBH_CHn_CMD_IRQONCMPLT_V(e) BF_APBH_CHn_CMD_IRQONCMPLT(BV_APBH_CHn_CMD_IRQONCMPLT__##e) +#define BFM_APBH_CHn_CMD_IRQONCMPLT_V(v) BM_APBH_CHn_CMD_IRQONCMPLT +#define BP_APBH_CHn_CMD_CHAIN 2 +#define BM_APBH_CHn_CMD_CHAIN 0x4 +#define BF_APBH_CHn_CMD_CHAIN(v) (((v) & 0x1) << 2) +#define BFM_APBH_CHn_CMD_CHAIN(v) BM_APBH_CHn_CMD_CHAIN +#define BF_APBH_CHn_CMD_CHAIN_V(e) BF_APBH_CHn_CMD_CHAIN(BV_APBH_CHn_CMD_CHAIN__##e) +#define BFM_APBH_CHn_CMD_CHAIN_V(v) BM_APBH_CHn_CMD_CHAIN +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x3 +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 +#define BF_APBH_CHn_CMD_COMMAND(v) (((v) & 0x3) << 0) +#define BFM_APBH_CHn_CMD_COMMAND(v) BM_APBH_CHn_CMD_COMMAND +#define BF_APBH_CHn_CMD_COMMAND_V(e) BF_APBH_CHn_CMD_COMMAND(BV_APBH_CHn_CMD_COMMAND__##e) +#define BFM_APBH_CHn_CMD_COMMAND_V(v) BM_APBH_CHn_CMD_COMMAND + +#define HW_APBH_CHn_BAR(_n1) HW(APBH_CHn_BAR(_n1)) +#define HWA_APBH_CHn_BAR(_n1) (0x80004000 + 0x70 + (_n1) * 0x70) +#define HWT_APBH_CHn_BAR(_n1) HWIO_32_RW +#define HWN_APBH_CHn_BAR(_n1) APBH_CHn_BAR +#define HWI_APBH_CHn_BAR(_n1) (_n1) +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xffffffff +#define BF_APBH_CHn_BAR_ADDRESS(v) (((v) & 0xffffffff) << 0) +#define BFM_APBH_CHn_BAR_ADDRESS(v) BM_APBH_CHn_BAR_ADDRESS +#define BF_APBH_CHn_BAR_ADDRESS_V(e) BF_APBH_CHn_BAR_ADDRESS(BV_APBH_CHn_BAR_ADDRESS__##e) +#define BFM_APBH_CHn_BAR_ADDRESS_V(v) BM_APBH_CHn_BAR_ADDRESS + +#define HW_APBH_CHn_SEMA(_n1) HW(APBH_CHn_SEMA(_n1)) +#define HWA_APBH_CHn_SEMA(_n1) (0x80004000 + 0x80 + (_n1) * 0x70) +#define HWT_APBH_CHn_SEMA(_n1) HWIO_32_RW +#define HWN_APBH_CHn_SEMA(_n1) APBH_CHn_SEMA +#define HWI_APBH_CHn_SEMA(_n1) (_n1) +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xff000000 +#define BF_APBH_CHn_SEMA_RSVD2(v) (((v) & 0xff) << 24) +#define BFM_APBH_CHn_SEMA_RSVD2(v) BM_APBH_CHn_SEMA_RSVD2 +#define BF_APBH_CHn_SEMA_RSVD2_V(e) BF_APBH_CHn_SEMA_RSVD2(BV_APBH_CHn_SEMA_RSVD2__##e) +#define BFM_APBH_CHn_SEMA_RSVD2_V(v) BM_APBH_CHn_SEMA_RSVD2 +#define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0xff0000 +#define BF_APBH_CHn_SEMA_PHORE(v) (((v) & 0xff) << 16) +#define BFM_APBH_CHn_SEMA_PHORE(v) BM_APBH_CHn_SEMA_PHORE +#define BF_APBH_CHn_SEMA_PHORE_V(e) BF_APBH_CHn_SEMA_PHORE(BV_APBH_CHn_SEMA_PHORE__##e) +#define BFM_APBH_CHn_SEMA_PHORE_V(v) BM_APBH_CHn_SEMA_PHORE +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0xff00 +#define BF_APBH_CHn_SEMA_RSVD1(v) (((v) & 0xff) << 8) +#define BFM_APBH_CHn_SEMA_RSVD1(v) BM_APBH_CHn_SEMA_RSVD1 +#define BF_APBH_CHn_SEMA_RSVD1_V(e) BF_APBH_CHn_SEMA_RSVD1(BV_APBH_CHn_SEMA_RSVD1__##e) +#define BFM_APBH_CHn_SEMA_RSVD1_V(v) BM_APBH_CHn_SEMA_RSVD1 +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0xff +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) (((v) & 0xff) << 0) +#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA(v) BM_APBH_CHn_SEMA_INCREMENT_SEMA +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA_V(e) BF_APBH_CHn_SEMA_INCREMENT_SEMA(BV_APBH_CHn_SEMA_INCREMENT_SEMA__##e) +#define BFM_APBH_CHn_SEMA_INCREMENT_SEMA_V(v) BM_APBH_CHn_SEMA_INCREMENT_SEMA + +#define HW_APBH_CHn_DEBUG1(_n1) HW(APBH_CHn_DEBUG1(_n1)) +#define HWA_APBH_CHn_DEBUG1(_n1) (0x80004000 + 0x90 + (_n1) * 0x70) +#define HWT_APBH_CHn_DEBUG1(_n1) HWIO_32_RW +#define HWN_APBH_CHn_DEBUG1(_n1) APBH_CHn_DEBUG1 +#define HWI_APBH_CHn_DEBUG1(_n1) (_n1) +#define BP_APBH_CHn_DEBUG1_REQ 31 +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 +#define BF_APBH_CHn_DEBUG1_REQ(v) (((v) & 0x1) << 31) +#define BFM_APBH_CHn_DEBUG1_REQ(v) BM_APBH_CHn_DEBUG1_REQ +#define BF_APBH_CHn_DEBUG1_REQ_V(e) BF_APBH_CHn_DEBUG1_REQ(BV_APBH_CHn_DEBUG1_REQ__##e) +#define BFM_APBH_CHn_DEBUG1_REQ_V(v) BM_APBH_CHn_DEBUG1_REQ +#define BP_APBH_CHn_DEBUG1_BURST 30 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 +#define BF_APBH_CHn_DEBUG1_BURST(v) (((v) & 0x1) << 30) +#define BFM_APBH_CHn_DEBUG1_BURST(v) BM_APBH_CHn_DEBUG1_BURST +#define BF_APBH_CHn_DEBUG1_BURST_V(e) BF_APBH_CHn_DEBUG1_BURST(BV_APBH_CHn_DEBUG1_BURST__##e) +#define BFM_APBH_CHn_DEBUG1_BURST_V(v) BM_APBH_CHn_DEBUG1_BURST +#define BP_APBH_CHn_DEBUG1_KICK 29 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 +#define BF_APBH_CHn_DEBUG1_KICK(v) (((v) & 0x1) << 29) +#define BFM_APBH_CHn_DEBUG1_KICK(v) BM_APBH_CHn_DEBUG1_KICK +#define BF_APBH_CHn_DEBUG1_KICK_V(e) BF_APBH_CHn_DEBUG1_KICK(BV_APBH_CHn_DEBUG1_KICK__##e) +#define BFM_APBH_CHn_DEBUG1_KICK_V(v) BM_APBH_CHn_DEBUG1_KICK +#define BP_APBH_CHn_DEBUG1_END 28 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 +#define BF_APBH_CHn_DEBUG1_END(v) (((v) & 0x1) << 28) +#define BFM_APBH_CHn_DEBUG1_END(v) BM_APBH_CHn_DEBUG1_END +#define BF_APBH_CHn_DEBUG1_END_V(e) BF_APBH_CHn_DEBUG1_END(BV_APBH_CHn_DEBUG1_END__##e) +#define BFM_APBH_CHn_DEBUG1_END_V(v) BM_APBH_CHn_DEBUG1_END +#define BP_APBH_CHn_DEBUG1_SENSE 27 +#define BM_APBH_CHn_DEBUG1_SENSE 0x8000000 +#define BF_APBH_CHn_DEBUG1_SENSE(v) (((v) & 0x1) << 27) +#define BFM_APBH_CHn_DEBUG1_SENSE(v) BM_APBH_CHn_DEBUG1_SENSE +#define BF_APBH_CHn_DEBUG1_SENSE_V(e) BF_APBH_CHn_DEBUG1_SENSE(BV_APBH_CHn_DEBUG1_SENSE__##e) +#define BFM_APBH_CHn_DEBUG1_SENSE_V(v) BM_APBH_CHn_DEBUG1_SENSE +#define BP_APBH_CHn_DEBUG1_READY 26 +#define BM_APBH_CHn_DEBUG1_READY 0x4000000 +#define BF_APBH_CHn_DEBUG1_READY(v) (((v) & 0x1) << 26) +#define BFM_APBH_CHn_DEBUG1_READY(v) BM_APBH_CHn_DEBUG1_READY +#define BF_APBH_CHn_DEBUG1_READY_V(e) BF_APBH_CHn_DEBUG1_READY(BV_APBH_CHn_DEBUG1_READY__##e) +#define BFM_APBH_CHn_DEBUG1_READY_V(v) BM_APBH_CHn_DEBUG1_READY +#define BP_APBH_CHn_DEBUG1_LOCK 25 +#define BM_APBH_CHn_DEBUG1_LOCK 0x2000000 +#define BF_APBH_CHn_DEBUG1_LOCK(v) (((v) & 0x1) << 25) +#define BFM_APBH_CHn_DEBUG1_LOCK(v) BM_APBH_CHn_DEBUG1_LOCK +#define BF_APBH_CHn_DEBUG1_LOCK_V(e) BF_APBH_CHn_DEBUG1_LOCK(BV_APBH_CHn_DEBUG1_LOCK__##e) +#define BFM_APBH_CHn_DEBUG1_LOCK_V(v) BM_APBH_CHn_DEBUG1_LOCK +#define BP_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 24 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 +#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) & 0x1) << 24) +#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(v) BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID +#define BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(e) BF_APBH_CHn_DEBUG1_NEXTCMDADDRVALID(BV_APBH_CHn_DEBUG1_NEXTCMDADDRVALID__##e) +#define BFM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID_V(v) BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID +#define BP_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 23 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 +#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) & 0x1) << 23) +#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(v) BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY +#define BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(e) BF_APBH_CHn_DEBUG1_RD_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_RD_FIFO_EMPTY__##e) +#define BFM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY_V(v) BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY +#define BP_APBH_CHn_DEBUG1_RD_FIFO_FULL 22 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x400000 +#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) & 0x1) << 22) +#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL(v) BM_APBH_CHn_DEBUG1_RD_FIFO_FULL +#define BF_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(e) BF_APBH_CHn_DEBUG1_RD_FIFO_FULL(BV_APBH_CHn_DEBUG1_RD_FIFO_FULL__##e) +#define BFM_APBH_CHn_DEBUG1_RD_FIFO_FULL_V(v) BM_APBH_CHn_DEBUG1_RD_FIFO_FULL +#define BP_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 21 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 +#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) & 0x1) << 21) +#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(v) BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY +#define BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(e) BF_APBH_CHn_DEBUG1_WR_FIFO_EMPTY(BV_APBH_CHn_DEBUG1_WR_FIFO_EMPTY__##e) +#define BFM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY_V(v) BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY +#define BP_APBH_CHn_DEBUG1_WR_FIFO_FULL 20 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x100000 +#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) & 0x1) << 20) +#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL(v) BM_APBH_CHn_DEBUG1_WR_FIFO_FULL +#define BF_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(e) BF_APBH_CHn_DEBUG1_WR_FIFO_FULL(BV_APBH_CHn_DEBUG1_WR_FIFO_FULL__##e) +#define BFM_APBH_CHn_DEBUG1_WR_FIFO_FULL_V(v) BM_APBH_CHn_DEBUG1_WR_FIFO_FULL +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0xfffe0 +#define BF_APBH_CHn_DEBUG1_RSVD1(v) (((v) & 0x7fff) << 5) +#define BFM_APBH_CHn_DEBUG1_RSVD1(v) BM_APBH_CHn_DEBUG1_RSVD1 +#define BF_APBH_CHn_DEBUG1_RSVD1_V(e) BF_APBH_CHn_DEBUG1_RSVD1(BV_APBH_CHn_DEBUG1_RSVD1__##e) +#define BFM_APBH_CHn_DEBUG1_RSVD1_V(v) BM_APBH_CHn_DEBUG1_RSVD1 +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x1f +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0xc +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1d +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) (((v) & 0x1f) << 0) +#define BFM_APBH_CHn_DEBUG1_STATEMACHINE(v) BM_APBH_CHn_DEBUG1_STATEMACHINE +#define BF_APBH_CHn_DEBUG1_STATEMACHINE_V(e) BF_APBH_CHn_DEBUG1_STATEMACHINE(BV_APBH_CHn_DEBUG1_STATEMACHINE__##e) +#define BFM_APBH_CHn_DEBUG1_STATEMACHINE_V(v) BM_APBH_CHn_DEBUG1_STATEMACHINE + +#define HW_APBH_CHn_DEBUG2(_n1) HW(APBH_CHn_DEBUG2(_n1)) +#define HWA_APBH_CHn_DEBUG2(_n1) (0x80004000 + 0xa0 + (_n1) * 0x70) +#define HWT_APBH_CHn_DEBUG2(_n1) HWIO_32_RW +#define HWN_APBH_CHn_DEBUG2(_n1) APBH_CHn_DEBUG2 +#define HWI_APBH_CHn_DEBUG2(_n1) (_n1) +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xffff0000 +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) (((v) & 0xffff) << 16) +#define BFM_APBH_CHn_DEBUG2_APB_BYTES(v) BM_APBH_CHn_DEBUG2_APB_BYTES +#define BF_APBH_CHn_DEBUG2_APB_BYTES_V(e) BF_APBH_CHn_DEBUG2_APB_BYTES(BV_APBH_CHn_DEBUG2_APB_BYTES__##e) +#define BFM_APBH_CHn_DEBUG2_APB_BYTES_V(v) BM_APBH_CHn_DEBUG2_APB_BYTES +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0xffff +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) (((v) & 0xffff) << 0) +#define BFM_APBH_CHn_DEBUG2_AHB_BYTES(v) BM_APBH_CHn_DEBUG2_AHB_BYTES +#define BF_APBH_CHn_DEBUG2_AHB_BYTES_V(e) BF_APBH_CHn_DEBUG2_AHB_BYTES(BV_APBH_CHn_DEBUG2_AHB_BYTES__##e) +#define BFM_APBH_CHn_DEBUG2_AHB_BYTES_V(v) BM_APBH_CHn_DEBUG2_AHB_BYTES + +#define HW_APBH_VERSION HW(APBH_VERSION) +#define HWA_APBH_VERSION (0x80004000 + 0x3f0) +#define HWT_APBH_VERSION HWIO_32_RW +#define HWN_APBH_VERSION APBH_VERSION +#define HWI_APBH_VERSION +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xff000000 +#define BF_APBH_VERSION_MAJOR(v) (((v) & 0xff) << 24) +#define BFM_APBH_VERSION_MAJOR(v) BM_APBH_VERSION_MAJOR +#define BF_APBH_VERSION_MAJOR_V(e) BF_APBH_VERSION_MAJOR(BV_APBH_VERSION_MAJOR__##e) +#define BFM_APBH_VERSION_MAJOR_V(v) BM_APBH_VERSION_MAJOR +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0xff0000 +#define BF_APBH_VERSION_MINOR(v) (((v) & 0xff) << 16) +#define BFM_APBH_VERSION_MINOR(v) BM_APBH_VERSION_MINOR +#define BF_APBH_VERSION_MINOR_V(e) BF_APBH_VERSION_MINOR(BV_APBH_VERSION_MINOR__##e) +#define BFM_APBH_VERSION_MINOR_V(v) BM_APBH_VERSION_MINOR +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0xffff +#define BF_APBH_VERSION_STEP(v) (((v) & 0xffff) << 0) +#define BFM_APBH_VERSION_STEP(v) BM_APBH_VERSION_STEP +#define BF_APBH_VERSION_STEP_V(e) BF_APBH_VERSION_STEP(BV_APBH_VERSION_STEP__##e) +#define BFM_APBH_VERSION_STEP_V(v) BM_APBH_VERSION_STEP + +#endif /* __HEADERGEN_IMX233_APBH_H__*/ diff --git a/firmware/target/arm/imx233/regs/imx233/apbx.h b/firmware/target/arm/imx233/regs/imx233/apbx.h new file mode 100644 index 0000000000..c57ece23af --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/apbx.h @@ -0,0 +1,569 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * imx233 version: 2.4.0 + * imx233 authors: Amaury Pouly + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_IMX233_APBX_H__ +#define __HEADERGEN_IMX233_APBX_H__ + +#define HW_APBX_CTRL0 HW(APBX_CTRL0) +#define HWA_APBX_CTRL0 (0x80024000 + 0x0) +#define HWT_APBX_CTRL0 HWIO_32_RW +#define HWN_APBX_CTRL0 APBX_CTRL0 +#define HWI_APBX_CTRL0 +#define HW_APBX_CTRL0_SET HW(APBX_CTRL0_SET) +#define HWA_APBX_CTRL0_SET (HWA_APBX_CTRL0 + 0x4) +#define HWT_APBX_CTRL0_SET HWIO_32_WO +#define HWN_APBX_CTRL0_SET APBX_CTRL0 +#define HWI_APBX_CTRL0_SET +#define HW_APBX_CTRL0_CLR HW(APBX_CTRL0_CLR) +#define HWA_APBX_CTRL0_CLR (HWA_APBX_CTRL0 + 0x8) +#define HWT_APBX_CTRL0_CLR HWIO_32_WO +#define HWN_APBX_CTRL0_CLR APBX_CTRL0 +#define HWI_APBX_CTRL0_CLR +#define HW_APBX_CTRL0_TOG HW(APBX_CTRL0_TOG) +#define HWA_APBX_CTRL0_TOG (HWA_APBX_CTRL0 + 0xc) +#define HWT_APBX_CTRL0_TOG HWIO_32_WO +#define HWN_APBX_CTRL0_TOG APBX_CTRL0 +#define HWI_APBX_CTRL0_TOG +#define BP_APBX_CTRL0_SFTRST 31 +#define BM_APBX_CTRL0_SFTRST 0x80000000 +#define BF_APBX_CTRL0_SFTRST(v) (((v) & 0x1) << 31) +#define BFM_APBX_CTRL0_SFTRST(v) BM_APBX_CTRL0_SFTRST +#define BF_APBX_CTRL0_SFTRST_V(e) BF_APBX_CTRL0_SFTRST(BV_APBX_CTRL0_SFTRST__##e) +#define BFM_APBX_CTRL0_SFTRST_V(v) BM_APBX_CTRL0_SFTRST +#define BP_APBX_CTRL0_CLKGATE 30 +#define BM_APBX_CTRL0_CLKGATE 0x40000000 +#define BF_APBX_CTRL0_CLKGATE(v) (((v) & 0x1) << 30) +#define BFM_APBX_CTRL0_CLKGATE(v) BM_APBX_CTRL0_CLKGATE +#define BF_APBX_CTRL0_CLKGATE_V(e) BF_APBX_CTRL0_CLKGATE(BV_APBX_CTRL0_CLKGATE__##e) +#define BFM_APBX_CTRL0_CLKGATE_V(v) BM_APBX_CTRL0_CLKGATE +#define BP_APBX_CTRL0_RSVD0 0 +#define BM_APBX_CTRL0_RSVD0 0x3fffffff +#define BF_APBX_CTRL0_RSVD0(v) (((v) & 0x3fffffff) << 0) +#define BFM_APBX_CTRL0_RSVD0(v) BM_APBX_CTRL0_RSVD0 +#define BF_APBX_CTRL0_RSVD0_V(e) BF_APBX_CTRL0_RSVD0(BV_APBX_CTRL0_RSVD0__##e) +#define BFM_APBX_CTRL0_RSVD0_V(v) BM_APBX_CTRL0_RSVD0 + +#define HW_APBX_CTRL1 HW(APBX_CTRL1) +#define HWA_APBX_CTRL1 (0x80024000 + 0x10) +#define HWT_APBX_CTRL1 HWIO_32_RW +#define HWN_APBX_CTRL1 APBX_CTRL1 +#define HWI_APBX_CTRL1 +#define HW_APBX_CTRL1_SET HW(APBX_CTRL1_SET) +#define HWA_APBX_CTRL1_SET (HWA_APBX_CTRL1 + 0x4) +#define HWT_APBX_CTRL1_SET HWIO_32_WO +#define HWN_APBX_CTRL1_SET APBX_CTRL1 +#define HWI_APBX_CTRL1_SET +#define HW_APBX_CTRL1_CLR HW(APBX_CTRL1_CLR) +#define HWA_APBX_CTRL1_CLR (HWA_APBX_CTRL1 + 0x8) +#define HWT_APBX_CTRL1_CLR HWIO_32_WO +#define HWN_APBX_CTRL1_CLR APBX_CTRL1 +#define HWI_APBX_CTRL1_CLR +#define HW_APBX_CTRL1_TOG HW(APBX_CTRL1_TOG) +#define HWA_APBX_CTRL1_TOG (HWA_APBX_CTRL1 + 0xc) +#define HWT_APBX_CTRL1_TOG HWIO_32_WO +#define HWN_APBX_CTRL1_TOG APBX_CTRL1 +#define HWI_APBX_CTRL1_TOG +#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 16 +#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN 0xffff0000 +#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) (((v) & 0xffff) << 16) +#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(v) BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN +#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN_V(e) BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN(BV_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN__##e) +#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN_V(v) BM_APBX_CTRL1_CH_CMDCMPLT_IRQ_EN +#define BP_APBX_CTRL1_CH_CMDCMPLT_IRQ 0 +#define BM_APBX_CTRL1_CH_CMDCMPLT_IRQ 0xffff +#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(v) (((v) & 0xffff) << 0) +#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ(v) BM_APBX_CTRL1_CH_CMDCMPLT_IRQ +#define BF_APBX_CTRL1_CH_CMDCMPLT_IRQ_V(e) BF_APBX_CTRL1_CH_CMDCMPLT_IRQ(BV_APBX_CTRL1_CH_CMDCMPLT_IRQ__##e) +#define BFM_APBX_CTRL1_CH_CMDCMPLT_IRQ_V(v) BM_APBX_CTRL1_CH_CMDCMPLT_IRQ + +#define HW_APBX_CTRL2 HW(APBX_CTRL2) +#define HWA_APBX_CTRL2 (0x80024000 + 0x20) +#define HWT_APBX_CTRL2 HWIO_32_RW +#define HWN_APBX_CTRL2 APBX_CTRL2 +#define HWI_APBX_CTRL2 +#define HW_APBX_CTRL2_SET HW(APBX_CTRL2_SET) +#define HWA_APBX_CTRL2_SET (HWA_APBX_CTRL2 + 0x4) +#define HWT_APBX_CTRL2_SET HWIO_32_WO +#define HWN_APBX_CTRL2_SET APBX_CTRL2 +#define HWI_APBX_CTRL2_SET +#define HW_APBX_CTRL2_CLR HW(APBX_CTRL2_CLR) +#define HWA_APBX_CTRL2_CLR (HWA_APBX_CTRL2 + 0x8) +#define HWT_APBX_CTRL2_CLR HWIO_32_WO +#define HWN_APBX_CTRL2_CLR APBX_CTRL2 +#define HWI_APBX_CTRL2_CLR +#define HW_APBX_CTRL2_TOG HW(APBX_CTRL2_TOG) +#define HWA_APBX_CTRL2_TOG (HWA_APBX_CTRL2 + 0xc) +#define HWT_APBX_CTRL2_TOG HWIO_32_WO +#define HWN_APBX_CTRL2_TOG APBX_CTRL2 +#define HWI_APBX_CTRL2_TOG +#define BP_APBX_CTRL2_CH_ERROR_STATUS 16 +#define BM_APBX_CTRL2_CH_ERROR_STATUS 0xffff0000 +#define BF_APBX_CTRL2_CH_ERROR_STATUS(v) (((v) & 0xffff) << 16) +#define BFM_APBX_CTRL2_CH_ERROR_STATUS(v) BM_APBX_CTRL2_CH_ERROR_STATUS +#define BF_APBX_CTRL2_CH_ERROR_STATUS_V(e) BF_APBX_CTRL2_CH_ERROR_STATUS(BV_APBX_CTRL2_CH_ERROR_STATUS__##e) +#define BFM_APBX_CTRL2_CH_ERROR_STATUS_V(v) BM_APBX_CTRL2_CH_ERROR_STATUS +#define BP_APBX_CTRL2_CH_ERROR_IRQ 0 +#define BM_APBX_CTRL2_CH_ERROR_IRQ 0xffff +#define BF_APBX_CTRL2_CH_ERROR_IRQ(v) (((v) & 0xffff) << 0) +#define BFM_APBX_CTRL2_CH_ERROR_IRQ(v) BM_APBX_CTRL2_CH_ERROR_IRQ +#define BF_APBX_CTRL2_CH_ERROR_IRQ_V(e) BF_APBX_CTRL2_CH_ERROR_IRQ(BV_APBX_CTRL2_CH_ERROR_IRQ__##e) +#define BFM_APBX_CTRL2_CH_ERROR_IRQ_V(v) BM_APBX_CTRL2_CH_ERROR_IRQ + +#define HW_APBX_CHANNEL_CTRL HW(APBX_CHANNEL_CTRL) +#define HWA_APBX_CHANNEL_CTRL (0x80024000 + 0x30) +#define HWT_APBX_CHANNEL_CTRL HWIO_32_RW +#define HWN_APBX_CHANNEL_CTRL APBX_CHANNEL_CTRL +#define HWI_APBX_CHANNEL_CTRL +#define HW_APBX_CHANNEL_CTRL_SET HW(APBX_CHANNEL_CTRL_SET) +#define HWA_APBX_CHANNEL_CTRL_SET (HWA_APBX_CHANNEL_CTRL + 0x4) +#define HWT_APBX_CHANNEL_CTRL_SET HWIO_32_WO +#define HWN_APBX_CHANNEL_CTRL_SET APBX_CHANNEL_CTRL +#define HWI_APBX_CHANNEL_CTRL_SET +#define HW_APBX_CHANNEL_CTRL_CLR HW(APBX_CHANNEL_CTRL_CLR) +#define HWA_APBX_CHANNEL_CTRL_CLR (HWA_APBX_CHANNEL_CTRL + 0x8) +#define HWT_APBX_CHANNEL_CTRL_CLR HWIO_32_WO +#define HWN_APBX_CHANNEL_CTRL_CLR APBX_CHANNEL_CTRL +#define HWI_APBX_CHANNEL_CTRL_CLR +#define HW_APBX_CHANNEL_CTRL_TOG HW(APBX_CHANNEL_CTRL_TOG) +#define HWA_APBX_CHANNEL_CTRL_TOG (HWA_APBX_CHANNEL_CTRL + 0xc) +#define HWT_APBX_CHANNEL_CTRL_TOG HWIO_32_WO +#define HWN_APBX_CHANNEL_CTRL_TOG APBX_CHANNEL_CTRL +#define HWI_APBX_CHANNEL_CTRL_TOG +#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xffff0000 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOIN 0x1 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOOUT 0x2 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SPDIF_TX 0x4 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C 0x8 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF1 0x10 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__DRI 0x20 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_RX 0x40 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_RX 0x40 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_TX 0x80 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_TX 0x80 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_RX 0x100 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_TX 0x200 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF2 0x400 +#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) (((v) & 0xffff) << 16) +#define BFM_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) BM_APBX_CHANNEL_CTRL_RESET_CHANNEL +#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL_V(e) BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__##e) +#define BFM_APBX_CHANNEL_CTRL_RESET_CHANNEL_V(v) BM_APBX_CHANNEL_CTRL_RESET_CHANNEL +#define BP_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0xffff +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOIN 0x1 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOOUT 0x2 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SPDIF_TX 0x4 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C 0x8 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF1 0x10 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__DRI 0x20 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_RX 0x40 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_RX 0x40 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_TX 0x80 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_TX 0x80 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_RX 0x100 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_TX 0x200 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF2 0x400 +#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v) (((v) & 0xffff) << 0) +#define BFM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v) BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL +#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL_V(e) BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__##e) +#define BFM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL_V(v) BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL + +#define HW_APBX_DEVSEL HW(APBX_DEVSEL) +#define HWA_APBX_DEVSEL (0x80024000 + 0x40) +#define HWT_APBX_DEVSEL HWIO_32_RW +#define HWN_APBX_DEVSEL APBX_DEVSEL +#define HWI_APBX_DEVSEL +#define BP_APBX_DEVSEL_CH15 30 +#define BM_APBX_DEVSEL_CH15 0xc0000000 +#define BF_APBX_DEVSEL_CH15(v) (((v) & 0x3) << 30) +#define BFM_APBX_DEVSEL_CH15(v) BM_APBX_DEVSEL_CH15 +#define BF_APBX_DEVSEL_CH15_V(e) BF_APBX_DEVSEL_CH15(BV_APBX_DEVSEL_CH15__##e) +#define BFM_APBX_DEVSEL_CH15_V(v) BM_APBX_DEVSEL_CH15 +#define BP_APBX_DEVSEL_CH14 28 +#define BM_APBX_DEVSEL_CH14 0x30000000 +#define BF_APBX_DEVSEL_CH14(v) (((v) & 0x3) << 28) +#define BFM_APBX_DEVSEL_CH14(v) BM_APBX_DEVSEL_CH14 +#define BF_APBX_DEVSEL_CH14_V(e) BF_APBX_DEVSEL_CH14(BV_APBX_DEVSEL_CH14__##e) +#define BFM_APBX_DEVSEL_CH14_V(v) BM_APBX_DEVSEL_CH14 +#define BP_APBX_DEVSEL_CH13 26 +#define BM_APBX_DEVSEL_CH13 0xc000000 +#define BF_APBX_DEVSEL_CH13(v) (((v) & 0x3) << 26) +#define BFM_APBX_DEVSEL_CH13(v) BM_APBX_DEVSEL_CH13 +#define BF_APBX_DEVSEL_CH13_V(e) BF_APBX_DEVSEL_CH13(BV_APBX_DEVSEL_CH13__##e) +#define BFM_APBX_DEVSEL_CH13_V(v) BM_APBX_DEVSEL_CH13 +#define BP_APBX_DEVSEL_CH12 24 +#define BM_APBX_DEVSEL_CH12 0x3000000 +#define BF_APBX_DEVSEL_CH12(v) (((v) & 0x3) << 24) +#define BFM_APBX_DEVSEL_CH12(v) BM_APBX_DEVSEL_CH12 +#define BF_APBX_DEVSEL_CH12_V(e) BF_APBX_DEVSEL_CH12(BV_APBX_DEVSEL_CH12__##e) +#define BFM_APBX_DEVSEL_CH12_V(v) BM_APBX_DEVSEL_CH12 +#define BP_APBX_DEVSEL_CH11 22 +#define BM_APBX_DEVSEL_CH11 0xc00000 +#define BF_APBX_DEVSEL_CH11(v) (((v) & 0x3) << 22) +#define BFM_APBX_DEVSEL_CH11(v) BM_APBX_DEVSEL_CH11 +#define BF_APBX_DEVSEL_CH11_V(e) BF_APBX_DEVSEL_CH11(BV_APBX_DEVSEL_CH11__##e) +#define BFM_APBX_DEVSEL_CH11_V(v) BM_APBX_DEVSEL_CH11 +#define BP_APBX_DEVSEL_CH10 20 +#define BM_APBX_DEVSEL_CH10 0x300000 +#define BF_APBX_DEVSEL_CH10(v) (((v) & 0x3) << 20) +#define BFM_APBX_DEVSEL_CH10(v) BM_APBX_DEVSEL_CH10 +#define BF_APBX_DEVSEL_CH10_V(e) BF_APBX_DEVSEL_CH10(BV_APBX_DEVSEL_CH10__##e) +#define BFM_APBX_DEVSEL_CH10_V(v) BM_APBX_DEVSEL_CH10 +#define BP_APBX_DEVSEL_CH9 18 +#define BM_APBX_DEVSEL_CH9 0xc0000 +#define BF_APBX_DEVSEL_CH9(v) (((v) & 0x3) << 18) +#define BFM_APBX_DEVSEL_CH9(v) BM_APBX_DEVSEL_CH9 +#define BF_APBX_DEVSEL_CH9_V(e) BF_APBX_DEVSEL_CH9(BV_APBX_DEVSEL_CH9__##e) +#define BFM_APBX_DEVSEL_CH9_V(v) BM_APBX_DEVSEL_CH9 +#define BP_APBX_DEVSEL_CH8 16 +#define BM_APBX_DEVSEL_CH8 0x30000 +#define BF_APBX_DEVSEL_CH8(v) (((v) & 0x3) << 16) +#define BFM_APBX_DEVSEL_CH8(v) BM_APBX_DEVSEL_CH8 +#define BF_APBX_DEVSEL_CH8_V(e) BF_APBX_DEVSEL_CH8(BV_APBX_DEVSEL_CH8__##e) +#define BFM_APBX_DEVSEL_CH8_V(v) BM_APBX_DEVSEL_CH8 +#define BP_APBX_DEVSEL_CH7 14 +#define BM_APBX_DEVSEL_CH7 0xc000 +#define BV_APBX_DEVSEL_CH7__USE_I2C1 0x0 +#define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 +#define BF_APBX_DEVSEL_CH7(v) (((v) & 0x3) << 14) +#define BFM_APBX_DEVSEL_CH7(v) BM_APBX_DEVSEL_CH7 +#define BF_APBX_DEVSEL_CH7_V(e) BF_APBX_DEVSEL_CH7(BV_APBX_DEVSEL_CH7__##e) +#define BFM_APBX_DEVSEL_CH7_V(v) BM_APBX_DEVSEL_CH7 +#define BP_APBX_DEVSEL_CH6 12 +#define BM_APBX_DEVSEL_CH6 0x3000 +#define BV_APBX_DEVSEL_CH6__USE_SAIF1 0x0 +#define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 +#define BF_APBX_DEVSEL_CH6(v) (((v) & 0x3) << 12) +#define BFM_APBX_DEVSEL_CH6(v) BM_APBX_DEVSEL_CH6 +#define BF_APBX_DEVSEL_CH6_V(e) BF_APBX_DEVSEL_CH6(BV_APBX_DEVSEL_CH6__##e) +#define BFM_APBX_DEVSEL_CH6_V(v) BM_APBX_DEVSEL_CH6 +#define BP_APBX_DEVSEL_CH5 10 +#define BM_APBX_DEVSEL_CH5 0xc00 +#define BF_APBX_DEVSEL_CH5(v) (((v) & 0x3) << 10) +#define BFM_APBX_DEVSEL_CH5(v) BM_APBX_DEVSEL_CH5 +#define BF_APBX_DEVSEL_CH5_V(e) BF_APBX_DEVSEL_CH5(BV_APBX_DEVSEL_CH5__##e) +#define BFM_APBX_DEVSEL_CH5_V(v) BM_APBX_DEVSEL_CH5 +#define BP_APBX_DEVSEL_CH4 8 +#define BM_APBX_DEVSEL_CH4 0x300 +#define BF_APBX_DEVSEL_CH4(v) (((v) & 0x3) << 8) +#define BFM_APBX_DEVSEL_CH4(v) BM_APBX_DEVSEL_CH4 +#define BF_APBX_DEVSEL_CH4_V(e) BF_APBX_DEVSEL_CH4(BV_APBX_DEVSEL_CH4__##e) +#define BFM_APBX_DEVSEL_CH4_V(v) BM_APBX_DEVSEL_CH4 +#define BP_APBX_DEVSEL_CH3 6 +#define BM_APBX_DEVSEL_CH3 0xc0 +#define BF_APBX_DEVSEL_CH3(v) (((v) & 0x3) << 6) +#define BFM_APBX_DEVSEL_CH3(v) BM_APBX_DEVSEL_CH3 +#define BF_APBX_DEVSEL_CH3_V(e) BF_APBX_DEVSEL_CH3(BV_APBX_DEVSEL_CH3__##e) +#define BFM_APBX_DEVSEL_CH3_V(v) BM_APBX_DEVSEL_CH3 +#define BP_APBX_DEVSEL_CH2 4 +#define BM_APBX_DEVSEL_CH2 0x30 +#define BF_APBX_DEVSEL_CH2(v) (((v) & 0x3) << 4) +#define BFM_APBX_DEVSEL_CH2(v) BM_APBX_DEVSEL_CH2 +#define BF_APBX_DEVSEL_CH2_V(e) BF_APBX_DEVSEL_CH2(BV_APBX_DEVSEL_CH2__##e) +#define BFM_APBX_DEVSEL_CH2_V(v) BM_APBX_DEVSEL_CH2 +#define BP_APBX_DEVSEL_CH1 2 +#define BM_APBX_DEVSEL_CH1 0xc +#define BF_APBX_DEVSEL_CH1(v) (((v) & 0x3) << 2) +#define BFM_APBX_DEVSEL_CH1(v) BM_APBX_DEVSEL_CH1 +#define BF_APBX_DEVSEL_CH1_V(e) BF_APBX_DEVSEL_CH1(BV_APBX_DEVSEL_CH1__##e) +#define BFM_APBX_DEVSEL_CH1_V(v) BM_APBX_DEVSEL_CH1 +#define BP_APBX_DEVSEL_CH0 0 +#define BM_APBX_DEVSEL_CH0 0x3 +#define BF_APBX_DEVSEL_CH0(v) (((v) & 0x3) << 0) +#define BFM_APBX_DEVSEL_CH0(v) BM_APBX_DEVSEL_CH0 +#define BF_APBX_DEVSEL_CH0_V(e) BF_APBX_DEVSEL_CH0(BV_APBX_DEVSEL_CH0__##e) +#define BFM_APBX_DEVSEL_CH0_V(v) BM_APBX_DEVSEL_CH0 + +#define HW_APBX_CHn_CURCMDAR(_n1) HW(APBX_CHn_CURCMDAR(_n1)) +#define HWA_APBX_CHn_CURCMDAR(_n1) (0x80024000 + 0x100 + (_n1) * 0x70) +#define HWT_APBX_CHn_CURCMDAR(_n1) HWIO_32_RW +#define HWN_APBX_CHn_CURCMDAR(_n1) APBX_CHn_CURCMDAR +#define HWI_APBX_CHn_CURCMDAR(_n1) (_n1) +#define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xffffffff +#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_APBX_CHn_CURCMDAR_CMD_ADDR(v) BM_APBX_CHn_CURCMDAR_CMD_ADDR +#define BF_APBX_CHn_CURCMDAR_CMD_ADDR_V(e) BF_APBX_CHn_CURCMDAR_CMD_ADDR(BV_APBX_CHn_CURCMDAR_CMD_ADDR__##e) +#define BFM_APBX_CHn_CURCMDAR_CMD_ADDR_V(v) BM_APBX_CHn_CURCMDAR_CMD_ADDR + +#define HW_APBX_CHn_NXTCMDAR(_n1) HW(APBX_CHn_NXTCMDAR(_n1)) +#define HWA_APBX_CHn_NXTCMDAR(_n1) (0x80024000 + 0x110 + (_n1) * 0x70) +#define HWT_APBX_CHn_NXTCMDAR(_n1) HWIO_32_RW +#define HWN_APBX_CHn_NXTCMDAR(_n1) APBX_CHn_NXTCMDAR +#define HWI_APBX_CHn_NXTCMDAR(_n1) (_n1) +#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xffffffff +#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_APBX_CHn_NXTCMDAR_CMD_ADDR(v) BM_APBX_CHn_NXTCMDAR_CMD_ADDR +#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR_V(e) BF_APBX_CHn_NXTCMDAR_CMD_ADDR(BV_APBX_CHn_NXTCMDAR_CMD_ADDR__##e) +#define BFM_APBX_CHn_NXTCMDAR_CMD_ADDR_V(v) BM_APBX_CHn_NXTCMDAR_CMD_ADDR + +#define HW_APBX_CHn_CMD(_n1) HW(APBX_CHn_CMD(_n1)) +#define HWA_APBX_CHn_CMD(_n1) (0x80024000 + 0x120 + (_n1) * 0x70) +#define HWT_APBX_CHn_CMD(_n1) HWIO_32_RW +#define HWN_APBX_CHn_CMD(_n1) APBX_CHn_CMD +#define HWI_APBX_CHn_CMD(_n1) (_n1) +#define BP_APBX_CHn_CMD_XFER_COUNT 16 +#define BM_APBX_CHn_CMD_XFER_COUNT 0xffff0000 +#define BF_APBX_CHn_CMD_XFER_COUNT(v) (((v) & 0xffff) << 16) +#define BFM_APBX_CHn_CMD_XFER_COUNT(v) BM_APBX_CHn_CMD_XFER_COUNT +#define BF_APBX_CHn_CMD_XFER_COUNT_V(e) BF_APBX_CHn_CMD_XFER_COUNT(BV_APBX_CHn_CMD_XFER_COUNT__##e) +#define BFM_APBX_CHn_CMD_XFER_COUNT_V(v) BM_APBX_CHn_CMD_XFER_COUNT +#define BP_APBX_CHn_CMD_CMDWORDS 12 +#define BM_APBX_CHn_CMD_CMDWORDS 0xf000 +#define BF_APBX_CHn_CMD_CMDWORDS(v) (((v) & 0xf) << 12) +#define BFM_APBX_CHn_CMD_CMDWORDS(v) BM_APBX_CHn_CMD_CMDWORDS +#define BF_APBX_CHn_CMD_CMDWORDS_V(e) BF_APBX_CHn_CMD_CMDWORDS(BV_APBX_CHn_CMD_CMDWORDS__##e) +#define BFM_APBX_CHn_CMD_CMDWORDS_V(v) BM_APBX_CHn_CMD_CMDWORDS +#define BP_APBX_CHn_CMD_RSVD1 9 +#define BM_APBX_CHn_CMD_RSVD1 0xe00 +#define BF_APBX_CHn_CMD_RSVD1(v) (((v) & 0x7) << 9) +#define BFM_APBX_CHn_CMD_RSVD1(v) BM_APBX_CHn_CMD_RSVD1 +#define BF_APBX_CHn_CMD_RSVD1_V(e) BF_APBX_CHn_CMD_RSVD1(BV_APBX_CHn_CMD_RSVD1__##e) +#define BFM_APBX_CHn_CMD_RSVD1_V(v) BM_APBX_CHn_CMD_RSVD1 +#define BP_APBX_CHn_CMD_HALTONTERMINATE 8 +#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x100 +#define BF_APBX_CHn_CMD_HALTONTERMINATE(v) (((v) & 0x1) << 8) +#define BFM_APBX_CHn_CMD_HALTONTERMINATE(v) BM_APBX_CHn_CMD_HALTONTERMINATE +#define BF_APBX_CHn_CMD_HALTONTERMINATE_V(e) BF_APBX_CHn_CMD_HALTONTERMINATE(BV_APBX_CHn_CMD_HALTONTERMINATE__##e) +#define BFM_APBX_CHn_CMD_HALTONTERMINATE_V(v) BM_APBX_CHn_CMD_HALTONTERMINATE +#define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 +#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x80 +#define BF_APBX_CHn_CMD_WAIT4ENDCMD(v) (((v) & 0x1) << 7) +#define BFM_APBX_CHn_CMD_WAIT4ENDCMD(v) BM_APBX_CHn_CMD_WAIT4ENDCMD +#define BF_APBX_CHn_CMD_WAIT4ENDCMD_V(e) BF_APBX_CHn_CMD_WAIT4ENDCMD(BV_APBX_CHn_CMD_WAIT4ENDCMD__##e) +#define BFM_APBX_CHn_CMD_WAIT4ENDCMD_V(v) BM_APBX_CHn_CMD_WAIT4ENDCMD +#define BP_APBX_CHn_CMD_SEMAPHORE 6 +#define BM_APBX_CHn_CMD_SEMAPHORE 0x40 +#define BF_APBX_CHn_CMD_SEMAPHORE(v) (((v) & 0x1) << 6) +#define BFM_APBX_CHn_CMD_SEMAPHORE(v) BM_APBX_CHn_CMD_SEMAPHORE +#define BF_APBX_CHn_CMD_SEMAPHORE_V(e) BF_APBX_CHn_CMD_SEMAPHORE(BV_APBX_CHn_CMD_SEMAPHORE__##e) +#define BFM_APBX_CHn_CMD_SEMAPHORE_V(v) BM_APBX_CHn_CMD_SEMAPHORE +#define BP_APBX_CHn_CMD_RSVD0 4 +#define BM_APBX_CHn_CMD_RSVD0 0x30 +#define BF_APBX_CHn_CMD_RSVD0(v) (((v) & 0x3) << 4) +#define BFM_APBX_CHn_CMD_RSVD0(v) BM_APBX_CHn_CMD_RSVD0 +#define BF_APBX_CHn_CMD_RSVD0_V(e) BF_APBX_CHn_CMD_RSVD0(BV_APBX_CHn_CMD_RSVD0__##e) +#define BFM_APBX_CHn_CMD_RSVD0_V(v) BM_APBX_CHn_CMD_RSVD0 +#define BP_APBX_CHn_CMD_IRQONCMPLT 3 +#define BM_APBX_CHn_CMD_IRQONCMPLT 0x8 +#define BF_APBX_CHn_CMD_IRQONCMPLT(v) (((v) & 0x1) << 3) +#define BFM_APBX_CHn_CMD_IRQONCMPLT(v) BM_APBX_CHn_CMD_IRQONCMPLT +#define BF_APBX_CHn_CMD_IRQONCMPLT_V(e) BF_APBX_CHn_CMD_IRQONCMPLT(BV_APBX_CHn_CMD_IRQONCMPLT__##e) +#define BFM_APBX_CHn_CMD_IRQONCMPLT_V(v) BM_APBX_CHn_CMD_IRQONCMPLT +#define BP_APBX_CHn_CMD_CHAIN 2 +#define BM_APBX_CHn_CMD_CHAIN 0x4 +#define BF_APBX_CHn_CMD_CHAIN(v) (((v) & 0x1) << 2) +#define BFM_APBX_CHn_CMD_CHAIN(v) BM_APBX_CHn_CMD_CHAIN +#define BF_APBX_CHn_CMD_CHAIN_V(e) BF_APBX_CHn_CMD_CHAIN(BV_APBX_CHn_CMD_CHAIN__##e) +#define BFM_APBX_CHn_CMD_CHAIN_V(v) BM_APBX_CHn_CMD_CHAIN +#define BP_APBX_CHn_CMD_COMMAND 0 +#define BM_APBX_CHn_CMD_COMMAND 0x3 +#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BF_APBX_CHn_CMD_COMMAND(v) (((v) & 0x3) << 0) +#define BFM_APBX_CHn_CMD_COMMAND(v) BM_APBX_CHn_CMD_COMMAND +#define BF_APBX_CHn_CMD_COMMAND_V(e) BF_APBX_CHn_CMD_COMMAND(BV_APBX_CHn_CMD_COMMAND__##e) +#define BFM_APBX_CHn_CMD_COMMAND_V(v) BM_APBX_CHn_CMD_COMMAND + +#define HW_APBX_CHn_BAR(_n1) HW(APBX_CHn_BAR(_n1)) +#define HWA_APBX_CHn_BAR(_n1) (0x80024000 + 0x130 + (_n1) * 0x70) +#define HWT_APBX_CHn_BAR(_n1) HWIO_32_RW +#define HWN_APBX_CHn_BAR(_n1) APBX_CHn_BAR +#define HWI_APBX_CHn_BAR(_n1) (_n1) +#define BP_APBX_CHn_BAR_ADDRESS 0 +#define BM_APBX_CHn_BAR_ADDRESS 0xffffffff +#define BF_APBX_CHn_BAR_ADDRESS(v) (((v) & 0xffffffff) << 0) +#define BFM_APBX_CHn_BAR_ADDRESS(v) BM_APBX_CHn_BAR_ADDRESS +#define BF_APBX_CHn_BAR_ADDRESS_V(e) BF_APBX_CHn_BAR_ADDRESS(BV_APBX_CHn_BAR_ADDRESS__##e) +#define BFM_APBX_CHn_BAR_ADDRESS_V(v) BM_APBX_CHn_BAR_ADDRESS + +#define HW_APBX_CHn_SEMA(_n1) HW(APBX_CHn_SEMA(_n1)) +#define HWA_APBX_CHn_SEMA(_n1) (0x80024000 + 0x140 + (_n1) * 0x70) +#define HWT_APBX_CHn_SEMA(_n1) HWIO_32_RW +#define HWN_APBX_CHn_SEMA(_n1) APBX_CHn_SEMA +#define HWI_APBX_CHn_SEMA(_n1) (_n1) +#define BP_APBX_CHn_SEMA_RSVD2 24 +#define BM_APBX_CHn_SEMA_RSVD2 0xff000000 +#define BF_APBX_CHn_SEMA_RSVD2(v) (((v) & 0xff) << 24) +#define BFM_APBX_CHn_SEMA_RSVD2(v) BM_APBX_CHn_SEMA_RSVD2 +#define BF_APBX_CHn_SEMA_RSVD2_V(e) BF_APBX_CHn_SEMA_RSVD2(BV_APBX_CHn_SEMA_RSVD2__##e) +#define BFM_APBX_CHn_SEMA_RSVD2_V(v) BM_APBX_CHn_SEMA_RSVD2 +#define BP_APBX_CHn_SEMA_PHORE 16 +#define BM_APBX_CHn_SEMA_PHORE 0xff0000 +#define BF_APBX_CHn_SEMA_PHORE(v) (((v) & 0xff) << 16) +#define BFM_APBX_CHn_SEMA_PHORE(v) BM_APBX_CHn_SEMA_PHORE +#define BF_APBX_CHn_SEMA_PHORE_V(e) BF_APBX_CHn_SEMA_PHORE(BV_APBX_CHn_SEMA_PHORE__##e) +#define BFM_APBX_CHn_SEMA_PHORE_V(v) BM_APBX_CHn_SEMA_PHORE +#define BP_APBX_CHn_SEMA_RSVD1 8 +#define BM_APBX_CHn_SEMA_RSVD1 0xff00 +#define BF_APBX_CHn_SEMA_RSVD1(v) (((v) & 0xff) << 8) +#define BFM_APBX_CHn_SEMA_RSVD1(v) BM_APBX_CHn_SEMA_RSVD1 +#define BF_APBX_CHn_SEMA_RSVD1_V(e) BF_APBX_CHn_SEMA_RSVD1(BV_APBX_CHn_SEMA_RSVD1__##e) +#define BFM_APBX_CHn_SEMA_RSVD1_V(v) BM_APBX_CHn_SEMA_RSVD1 +#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0xff +#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) (((v) & 0xff) << 0) +#define BFM_APBX_CHn_SEMA_INCREMENT_SEMA(v) BM_APBX_CHn_SEMA_INCREMENT_SEMA +#define BF_APBX_CHn_SEMA_INCREMENT_SEMA_V(e) BF_APBX_CHn_SEMA_INCREMENT_SEMA(BV_APBX_CHn_SEMA_INCREMENT_SEMA__##e) +#define BFM_APBX_CHn_SEMA_INCREMENT_SEMA_V(v) BM_APBX_CHn_SEMA_INCREMENT_SEMA + +#define HW_APBX_CHn_DEBUG1(_n1) HW(APBX_CHn_DEBUG1(_n1)) +#define HWA_APBX_CHn_DEBUG1(_n1) (0x80024000 + 0x150 + (_n1) * 0x70) +#define HWT_APBX_CHn_DEBUG1(_n1) HWIO_32_RW +#define HWN_APBX_CHn_DEBUG1(_n1) APBX_CHn_DEBUG1 +#define HWI_APBX_CHn_DEBUG1(_n1) (_n1) +#define BP_APBX_CHn_DEBUG1_REQ 31 +#define BM_APBX_CHn_DEBUG1_REQ 0x80000000 +#define BF_APBX_CHn_DEBUG1_REQ(v) (((v) & 0x1) << 31) +#define BFM_APBX_CHn_DEBUG1_REQ(v) BM_APBX_CHn_DEBUG1_REQ +#define BF_APBX_CHn_DEBUG1_REQ_V(e) BF_APBX_CHn_DEBUG1_REQ(BV_APBX_CHn_DEBUG1_REQ__##e) +#define BFM_APBX_CHn_DEBUG1_REQ_V(v) BM_APBX_CHn_DEBUG1_REQ +#define BP_APBX_CHn_DEBUG1_BURST 30 +#define BM_APBX_CHn_DEBUG1_BURST 0x40000000 +#define BF_APBX_CHn_DEBUG1_BURST(v) (((v) & 0x1) << 30) +#define BFM_APBX_CHn_DEBUG1_BURST(v) BM_APBX_CHn_DEBUG1_BURST +#define BF_APBX_CHn_DEBUG1_BURST_V(e) BF_APBX_CHn_DEBUG1_BURST(BV_APBX_CHn_DEBUG1_BURST__##e) +#define BFM_APBX_CHn_DEBUG1_BURST_V(v) BM_APBX_CHn_DEBUG1_BURST +#define BP_APBX_CHn_DEBUG1_KICK 29 +#define BM_APBX_CHn_DEBUG1_KICK 0x20000000 +#define BF_APBX_CHn_DEBUG1_KICK(v) (((v) & 0x1) << 29) +#define BFM_APBX_CHn_DEBUG1_KICK(v) BM_APBX_CHn_DEBUG1_KICK +#define BF_APBX_CHn_DEBUG1_KICK_V(e) BF_APBX_CHn_DEBUG1_KICK(BV_APBX_CHn_DEBUG1_KICK__##e) +#define BFM_APBX_CHn_DEBUG1_KICK_V(v) BM_APBX_CHn_DEBUG1_KICK +#define BP_APBX_CHn_DEBUG1_END 28 +#define BM_APBX_CHn_DEBUG1_END 0x10000000 +#define BF_APBX_CHn_DEBUG1_END(v) (((v) & 0x1) << 28) +#define BFM_APBX_CHn_DEBUG1_END(v) BM_APBX_CHn_DEBUG1_END +#define BF_APBX_CHn_DEBUG1_END_V(e) BF_APBX_CHn_DEBUG1_END(BV_APBX_CHn_DEBUG1_END__##e) +#define BFM_APBX_CHn_DEBUG1_END_V(v) BM_APBX_CHn_DEBUG1_END +#define BP_APBX_CHn_DEBUG1_RSVD2 25 +#define BM_APBX_CHn_DEBUG1_RSVD2 0xe000000 +#define BF_APBX_CHn_DEBUG1_RSVD2(v) (((v) & 0x7) << 25) +#define BFM_APBX_CHn_DEBUG1_RSVD2(v) BM_APBX_CHn_DEBUG1_RSVD2 +#define BF_APBX_CHn_DEBUG1_RSVD2_V(e) BF_APBX_CHn_DEBUG1_RSVD2(BV_APBX_CHn_DEBUG1_RSVD2__##e) +#define BFM_APBX_CHn_DEBUG1_RSVD2_V(v) BM_APBX_CHn_DEBUG1_RSVD2 +#define BP_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 24 +#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x1000000 +#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v) (((v) & 0x1) << 24) +#define BFM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(v) BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID +#define BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID_V(e) BF_APBX_CHn_DEBUG1_NEXTCMDADDRVALID(BV_APBX_CHn_DEBUG1_NEXTCMDADDRVALID__##e) +#define BFM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID_V(v) BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID +#define BP_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 23 +#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x800000 +#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v) (((v) & 0x1) << 23) +#define BFM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(v) BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY +#define BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY_V(e) BF_APBX_CHn_DEBUG1_RD_FIFO_EMPTY(BV_APBX_CHn_DEBUG1_RD_FIFO_EMPTY__##e) +#define BFM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY_V(v) BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY +#define BP_APBX_CHn_DEBUG1_RD_FIFO_FULL 22 +#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x400000 +#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(v) (((v) & 0x1) << 22) +#define BFM_APBX_CHn_DEBUG1_RD_FIFO_FULL(v) BM_APBX_CHn_DEBUG1_RD_FIFO_FULL +#define BF_APBX_CHn_DEBUG1_RD_FIFO_FULL_V(e) BF_APBX_CHn_DEBUG1_RD_FIFO_FULL(BV_APBX_CHn_DEBUG1_RD_FIFO_FULL__##e) +#define BFM_APBX_CHn_DEBUG1_RD_FIFO_FULL_V(v) BM_APBX_CHn_DEBUG1_RD_FIFO_FULL +#define BP_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 21 +#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x200000 +#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v) (((v) & 0x1) << 21) +#define BFM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(v) BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY +#define BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY_V(e) BF_APBX_CHn_DEBUG1_WR_FIFO_EMPTY(BV_APBX_CHn_DEBUG1_WR_FIFO_EMPTY__##e) +#define BFM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY_V(v) BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY +#define BP_APBX_CHn_DEBUG1_WR_FIFO_FULL 20 +#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x100000 +#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(v) (((v) & 0x1) << 20) +#define BFM_APBX_CHn_DEBUG1_WR_FIFO_FULL(v) BM_APBX_CHn_DEBUG1_WR_FIFO_FULL +#define BF_APBX_CHn_DEBUG1_WR_FIFO_FULL_V(e) BF_APBX_CHn_DEBUG1_WR_FIFO_FULL(BV_APBX_CHn_DEBUG1_WR_FIFO_FULL__##e) +#define BFM_APBX_CHn_DEBUG1_WR_FIFO_FULL_V(v) BM_APBX_CHn_DEBUG1_WR_FIFO_FULL +#define BP_APBX_CHn_DEBUG1_RSVD1 5 +#define BM_APBX_CHn_DEBUG1_RSVD1 0xfffe0 +#define BF_APBX_CHn_DEBUG1_RSVD1(v) (((v) & 0x7fff) << 5) +#define BFM_APBX_CHn_DEBUG1_RSVD1(v) BM_APBX_CHn_DEBUG1_RSVD1 +#define BF_APBX_CHn_DEBUG1_RSVD1_V(e) BF_APBX_CHn_DEBUG1_RSVD1(BV_APBX_CHn_DEBUG1_RSVD1__##e) +#define BFM_APBX_CHn_DEBUG1_RSVD1_V(v) BM_APBX_CHn_DEBUG1_RSVD1 +#define BP_APBX_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x1f +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x0 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x1 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x2 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x3 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x4 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x5 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x6 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x7 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x8 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x9 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0xc +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0xd +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0xe +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0xf +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1c +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1e +#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) (((v) & 0x1f) << 0) +#define BFM_APBX_CHn_DEBUG1_STATEMACHINE(v) BM_APBX_CHn_DEBUG1_STATEMACHINE +#define BF_APBX_CHn_DEBUG1_STATEMACHINE_V(e) BF_APBX_CHn_DEBUG1_STATEMACHINE(BV_APBX_CHn_DEBUG1_STATEMACHINE__##e) +#define BFM_APBX_CHn_DEBUG1_STATEMACHINE_V(v) BM_APBX_CHn_DEBUG1_STATEMACHINE + +#define HW_APBX_CHn_DEBUG2(_n1) HW(APBX_CHn_DEBUG2(_n1)) +#define HWA_APBX_CHn_DEBUG2(_n1) (0x80024000 + 0x160 + (_n1) * 0x70) +#define HWT_APBX_CHn_DEBUG2(_n1) HWIO_32_RW +#define HWN_APBX_CHn_DEBUG2(_n1) APBX_CHn_DEBUG2 +#define HWI_APBX_CHn_DEBUG2(_n1) (_n1) +#define BP_APBX_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBX_CHn_DEBUG2_APB_BYTES 0xffff0000 +#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) (((v) & 0xffff) << 16) +#define BFM_APBX_CHn_DEBUG2_APB_BYTES(v) BM_APBX_CHn_DEBUG2_APB_BYTES +#define BF_APBX_CHn_DEBUG2_APB_BYTES_V(e) BF_APBX_CHn_DEBUG2_APB_BYTES(BV_APBX_CHn_DEBUG2_APB_BYTES__##e) +#define BFM_APBX_CHn_DEBUG2_APB_BYTES_V(v) BM_APBX_CHn_DEBUG2_APB_BYTES +#define BP_APBX_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBX_CHn_DEBUG2_AHB_BYTES 0xffff +#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) (((v) & 0xffff) << 0) +#define BFM_APBX_CHn_DEBUG2_AHB_BYTES(v) BM_APBX_CHn_DEBUG2_AHB_BYTES +#define BF_APBX_CHn_DEBUG2_AHB_BYTES_V(e) BF_APBX_CHn_DEBUG2_AHB_BYTES(BV_APBX_CHn_DEBUG2_AHB_BYTES__##e) +#define BFM_APBX_CHn_DEBUG2_AHB_BYTES_V(v) BM_APBX_CHn_DEBUG2_AHB_BYTES + +#define HW_APBX_VERSION HW(APBX_VERSION) +#define HWA_APBX_VERSION (0x80024000 + 0x800) +#define HWT_APBX_VERSION HWIO_32_RW +#define HWN_APBX_VERSION APBX_VERSION +#define HWI_APBX_VERSION +#define BP_APBX_VERSION_MAJOR 24 +#define BM_APBX_VERSION_MAJOR 0xff000000 +#define BF_APBX_VERSION_MAJOR(v) (((v) & 0xff) << 24) +#define BFM_APBX_VERSION_MAJOR(v) BM_APBX_VERSION_MAJOR +#define BF_APBX_VERSION_MAJOR_V(e) BF_APBX_VERSION_MAJOR(BV_APBX_VERSION_MAJOR__##e) +#define BFM_APBX_VERSION_MAJOR_V(v) BM_APBX_VERSION_MAJOR +#define BP_APBX_VERSION_MINOR 16 +#define BM_APBX_VERSION_MINOR 0xff0000 +#define BF_APBX_VERSION_MINOR(v) (((v) & 0xff) << 16) +#define BFM_APBX_VERSION_MINOR(v) BM_APBX_VERSION_MINOR +#define BF_APBX_VERSION_MINOR_V(e) BF_APBX_VERSION_MINOR(BV_APBX_VERSION_MINOR__##e) +#define BFM_APBX_VERSION_MINOR_V(v) BM_APBX_VERSION_MINOR +#define BP_APBX_VERSION_STEP 0 +#define BM_APBX_VERSION_STEP 0xffff +#define BF_APBX_VERSION_STEP(v) (((v) & 0xffff) << 0) +#define BFM_APBX_VERSION_STEP(v) BM_APBX_VERSION_STEP +#define BF_APBX_VERSION_STEP_V(e) BF_APBX_VERSION_STEP(BV_APBX_VERSION_STEP__##e) +#define BFM_APBX_VERSION_STEP_V(v) BM_APBX_VERSION_STEP + +#endif /* __HEADERGEN_IMX233_APBX_H__*/ diff --git a/firmware/target/arm/imx233/regs/imx233/audioin.h b/firmware/target/arm/imx233/regs/imx233/audioin.h new file mode 100644 index 0000000000..612568f8eb --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/audioin.h @@ -0,0 +1,691 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * imx233 version: 2.4.0 + * imx233 authors: Amaury Pouly + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_IMX233_AUDIOIN_H__ +#define __HEADERGEN_IMX233_AUDIOIN_H__ + +#define HW_AUDIOIN_CTRL HW(AUDIOIN_CTRL) +#define HWA_AUDIOIN_CTRL (0x8004c000 + 0x0) +#define HWT_AUDIOIN_CTRL HWIO_32_RW +#define HWN_AUDIOIN_CTRL AUDIOIN_CTRL +#define HWI_AUDIOIN_CTRL +#define HW_AUDIOIN_CTRL_SET HW(AUDIOIN_CTRL_SET) +#define HWA_AUDIOIN_CTRL_SET (HWA_AUDIOIN_CTRL + 0x4) +#define HWT_AUDIOIN_CTRL_SET HWIO_32_WO +#define HWN_AUDIOIN_CTRL_SET AUDIOIN_CTRL +#define HWI_AUDIOIN_CTRL_SET +#define HW_AUDIOIN_CTRL_CLR HW(AUDIOIN_CTRL_CLR) +#define HWA_AUDIOIN_CTRL_CLR (HWA_AUDIOIN_CTRL + 0x8) +#define HWT_AUDIOIN_CTRL_CLR HWIO_32_WO +#define HWN_AUDIOIN_CTRL_CLR AUDIOIN_CTRL +#define HWI_AUDIOIN_CTRL_CLR +#define HW_AUDIOIN_CTRL_TOG HW(AUDIOIN_CTRL_TOG) +#define HWA_AUDIOIN_CTRL_TOG (HWA_AUDIOIN_CTRL + 0xc) +#define HWT_AUDIOIN_CTRL_TOG HWIO_32_WO +#define HWN_AUDIOIN_CTRL_TOG AUDIOIN_CTRL +#define HWI_AUDIOIN_CTRL_TOG +#define BP_AUDIOIN_CTRL_SFTRST 31 +#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 +#define BF_AUDIOIN_CTRL_SFTRST(v) (((v) & 0x1) << 31) +#define BFM_AUDIOIN_CTRL_SFTRST(v) BM_AUDIOIN_CTRL_SFTRST +#define BF_AUDIOIN_CTRL_SFTRST_V(e) BF_AUDIOIN_CTRL_SFTRST(BV_AUDIOIN_CTRL_SFTRST__##e) +#define BFM_AUDIOIN_CTRL_SFTRST_V(v) BM_AUDIOIN_CTRL_SFTRST +#define BP_AUDIOIN_CTRL_CLKGATE 30 +#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 +#define BF_AUDIOIN_CTRL_CLKGATE(v) (((v) & 0x1) << 30) +#define BFM_AUDIOIN_CTRL_CLKGATE(v) BM_AUDIOIN_CTRL_CLKGATE +#define BF_AUDIOIN_CTRL_CLKGATE_V(e) BF_AUDIOIN_CTRL_CLKGATE(BV_AUDIOIN_CTRL_CLKGATE__##e) +#define BFM_AUDIOIN_CTRL_CLKGATE_V(v) BM_AUDIOIN_CTRL_CLKGATE +#define BP_AUDIOIN_CTRL_RSRVD3 21 +#define BM_AUDIOIN_CTRL_RSRVD3 0x3fe00000 +#define BF_AUDIOIN_CTRL_RSRVD3(v) (((v) & 0x1ff) << 21) +#define BFM_AUDIOIN_CTRL_RSRVD3(v) BM_AUDIOIN_CTRL_RSRVD3 +#define BF_AUDIOIN_CTRL_RSRVD3_V(e) BF_AUDIOIN_CTRL_RSRVD3(BV_AUDIOIN_CTRL_RSRVD3__##e) +#define BFM_AUDIOIN_CTRL_RSRVD3_V(v) BM_AUDIOIN_CTRL_RSRVD3 +#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16 +#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x1f0000 +#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) (((v) & 0x1f) << 16) +#define BFM_AUDIOIN_CTRL_DMAWAIT_COUNT(v) BM_AUDIOIN_CTRL_DMAWAIT_COUNT +#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT_V(e) BF_AUDIOIN_CTRL_DMAWAIT_COUNT(BV_AUDIOIN_CTRL_DMAWAIT_COUNT__##e) +#define BFM_AUDIOIN_CTRL_DMAWAIT_COUNT_V(v) BM_AUDIOIN_CTRL_DMAWAIT_COUNT +#define BP_AUDIOIN_CTRL_RSRVD1 11 +#define BM_AUDIOIN_CTRL_RSRVD1 0xf800 +#define BF_AUDIOIN_CTRL_RSRVD1(v) (((v) & 0x1f) << 11) +#define BFM_AUDIOIN_CTRL_RSRVD1(v) BM_AUDIOIN_CTRL_RSRVD1 +#define BF_AUDIOIN_CTRL_RSRVD1_V(e) BF_AUDIOIN_CTRL_RSRVD1(BV_AUDIOIN_CTRL_RSRVD1__##e) +#define BFM_AUDIOIN_CTRL_RSRVD1_V(v) BM_AUDIOIN_CTRL_RSRVD1 +#define BP_AUDIOIN_CTRL_LR_SWAP 10 +#define BM_AUDIOIN_CTRL_LR_SWAP 0x400 +#define BF_AUDIOIN_CTRL_LR_SWAP(v) (((v) & 0x1) << 10) +#define BFM_AUDIOIN_CTRL_LR_SWAP(v) BM_AUDIOIN_CTRL_LR_SWAP +#define BF_AUDIOIN_CTRL_LR_SWAP_V(e) BF_AUDIOIN_CTRL_LR_SWAP(BV_AUDIOIN_CTRL_LR_SWAP__##e) +#define BFM_AUDIOIN_CTRL_LR_SWAP_V(v) BM_AUDIOIN_CTRL_LR_SWAP +#define BP_AUDIOIN_CTRL_EDGE_SYNC 9 +#define BM_AUDIOIN_CTRL_EDGE_SYNC 0x200 +#define BF_AUDIOIN_CTRL_EDGE_SYNC(v) (((v) & 0x1) << 9) +#define BFM_AUDIOIN_CTRL_EDGE_SYNC(v) BM_AUDIOIN_CTRL_EDGE_SYNC +#define BF_AUDIOIN_CTRL_EDGE_SYNC_V(e) BF_AUDIOIN_CTRL_EDGE_SYNC(BV_AUDIOIN_CTRL_EDGE_SYNC__##e) +#define BFM_AUDIOIN_CTRL_EDGE_SYNC_V(v) BM_AUDIOIN_CTRL_EDGE_SYNC +#define BP_AUDIOIN_CTRL_INVERT_1BIT 8 +#define BM_AUDIOIN_CTRL_INVERT_1BIT 0x100 +#define BF_AUDIOIN_CTRL_INVERT_1BIT(v) (((v) & 0x1) << 8) +#define BFM_AUDIOIN_CTRL_INVERT_1BIT(v) BM_AUDIOIN_CTRL_INVERT_1BIT +#define BF_AUDIOIN_CTRL_INVERT_1BIT_V(e) BF_AUDIOIN_CTRL_INVERT_1BIT(BV_AUDIOIN_CTRL_INVERT_1BIT__##e) +#define BFM_AUDIOIN_CTRL_INVERT_1BIT_V(v) BM_AUDIOIN_CTRL_INVERT_1BIT +#define BP_AUDIOIN_CTRL_OFFSET_ENABLE 7 +#define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x80 +#define BF_AUDIOIN_CTRL_OFFSET_ENABLE(v) (((v) & 0x1) << 7) +#define BFM_AUDIOIN_CTRL_OFFSET_ENABLE(v) BM_AUDIOIN_CTRL_OFFSET_ENABLE +#define BF_AUDIOIN_CTRL_OFFSET_ENABLE_V(e) BF_AUDIOIN_CTRL_OFFSET_ENABLE(BV_AUDIOIN_CTRL_OFFSET_ENABLE__##e) +#define BFM_AUDIOIN_CTRL_OFFSET_ENABLE_V(v) BM_AUDIOIN_CTRL_OFFSET_ENABLE +#define BP_AUDIOIN_CTRL_HPF_ENABLE 6 +#define BM_AUDIOIN_CTRL_HPF_ENABLE 0x40 +#define BF_AUDIOIN_CTRL_HPF_ENABLE(v) (((v) & 0x1) << 6) +#define BFM_AUDIOIN_CTRL_HPF_ENABLE(v) BM_AUDIOIN_CTRL_HPF_ENABLE +#define BF_AUDIOIN_CTRL_HPF_ENABLE_V(e) BF_AUDIOIN_CTRL_HPF_ENABLE(BV_AUDIOIN_CTRL_HPF_ENABLE__##e) +#define BFM_AUDIOIN_CTRL_HPF_ENABLE_V(v) BM_AUDIOIN_CTRL_HPF_ENABLE +#define BP_AUDIOIN_CTRL_WORD_LENGTH 5 +#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x20 +#define BF_AUDIOIN_CTRL_WORD_LENGTH(v) (((v) & 0x1) << 5) +#define BFM_AUDIOIN_CTRL_WORD_LENGTH(v) BM_AUDIOIN_CTRL_WORD_LENGTH +#define BF_AUDIOIN_CTRL_WORD_LENGTH_V(e) BF_AUDIOIN_CTRL_WORD_LENGTH(BV_AUDIOIN_CTRL_WORD_LENGTH__##e) +#define BFM_AUDIOIN_CTRL_WORD_LENGTH_V(v) BM_AUDIOIN_CTRL_WORD_LENGTH +#define BP_AUDIOIN_CTRL_LOOPBACK 4 +#define BM_AUDIOIN_CTRL_LOOPBACK 0x10 +#define BF_AUDIOIN_CTRL_LOOPBACK(v) (((v) & 0x1) << 4) +#define BFM_AUDIOIN_CTRL_LOOPBACK(v) BM_AUDIOIN_CTRL_LOOPBACK +#define BF_AUDIOIN_CTRL_LOOPBACK_V(e) BF_AUDIOIN_CTRL_LOOPBACK(BV_AUDIOIN_CTRL_LOOPBACK__##e) +#define BFM_AUDIOIN_CTRL_LOOPBACK_V(v) BM_AUDIOIN_CTRL_LOOPBACK +#define BP_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 3 +#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x8 +#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) & 0x1) << 3) +#define BFM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(v) BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ +#define BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ_V(e) BF_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ(BV_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ__##e) +#define BFM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ_V(v) BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ +#define BP_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 2 +#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x4 +#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) & 0x1) << 2) +#define BFM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(v) BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ +#define BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ_V(e) BF_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ(BV_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ__##e) +#define BFM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ_V(v) BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ +#define BP_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 1 +#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x2 +#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) & 0x1) << 1) +#define BFM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(v) BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN +#define BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN_V(e) BF_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN(BV_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN__##e) +#define BFM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN_V(v) BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN +#define BP_AUDIOIN_CTRL_RUN 0 +#define BM_AUDIOIN_CTRL_RUN 0x1 +#define BF_AUDIOIN_CTRL_RUN(v) (((v) & 0x1) << 0) +#define BFM_AUDIOIN_CTRL_RUN(v) BM_AUDIOIN_CTRL_RUN +#define BF_AUDIOIN_CTRL_RUN_V(e) BF_AUDIOIN_CTRL_RUN(BV_AUDIOIN_CTRL_RUN__##e) +#define BFM_AUDIOIN_CTRL_RUN_V(v) BM_AUDIOIN_CTRL_RUN + +#define HW_AUDIOIN_STAT HW(AUDIOIN_STAT) +#define HWA_AUDIOIN_STAT (0x8004c000 + 0x10) +#define HWT_AUDIOIN_STAT HWIO_32_RW +#define HWN_AUDIOIN_STAT AUDIOIN_STAT +#define HWI_AUDIOIN_STAT +#define HW_AUDIOIN_STAT_SET HW(AUDIOIN_STAT_SET) +#define HWA_AUDIOIN_STAT_SET (HWA_AUDIOIN_STAT + 0x4) +#define HWT_AUDIOIN_STAT_SET HWIO_32_WO +#define HWN_AUDIOIN_STAT_SET AUDIOIN_STAT +#define HWI_AUDIOIN_STAT_SET +#define HW_AUDIOIN_STAT_CLR HW(AUDIOIN_STAT_CLR) +#define HWA_AUDIOIN_STAT_CLR (HWA_AUDIOIN_STAT + 0x8) +#define HWT_AUDIOIN_STAT_CLR HWIO_32_WO +#define HWN_AUDIOIN_STAT_CLR AUDIOIN_STAT +#define HWI_AUDIOIN_STAT_CLR +#define HW_AUDIOIN_STAT_TOG HW(AUDIOIN_STAT_TOG) +#define HWA_AUDIOIN_STAT_TOG (HWA_AUDIOIN_STAT + 0xc) +#define HWT_AUDIOIN_STAT_TOG HWIO_32_WO +#define HWN_AUDIOIN_STAT_TOG AUDIOIN_STAT +#define HWI_AUDIOIN_STAT_TOG +#define BP_AUDIOIN_STAT_ADC_PRESENT 31 +#define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000 +#define BF_AUDIOIN_STAT_ADC_PRESENT(v) (((v) & 0x1) << 31) +#define BFM_AUDIOIN_STAT_ADC_PRESENT(v) BM_AUDIOIN_STAT_ADC_PRESENT +#define BF_AUDIOIN_STAT_ADC_PRESENT_V(e) BF_AUDIOIN_STAT_ADC_PRESENT(BV_AUDIOIN_STAT_ADC_PRESENT__##e) +#define BFM_AUDIOIN_STAT_ADC_PRESENT_V(v) BM_AUDIOIN_STAT_ADC_PRESENT +#define BP_AUDIOIN_STAT_RSRVD3 0 +#define BM_AUDIOIN_STAT_RSRVD3 0x7fffffff +#define BF_AUDIOIN_STAT_RSRVD3(v) (((v) & 0x7fffffff) << 0) +#define BFM_AUDIOIN_STAT_RSRVD3(v) BM_AUDIOIN_STAT_RSRVD3 +#define BF_AUDIOIN_STAT_RSRVD3_V(e) BF_AUDIOIN_STAT_RSRVD3(BV_AUDIOIN_STAT_RSRVD3__##e) +#define BFM_AUDIOIN_STAT_RSRVD3_V(v) BM_AUDIOIN_STAT_RSRVD3 + +#define HW_AUDIOIN_ADCSRR HW(AUDIOIN_ADCSRR) +#define HWA_AUDIOIN_ADCSRR (0x8004c000 + 0x20) +#define HWT_AUDIOIN_ADCSRR HWIO_32_RW +#define HWN_AUDIOIN_ADCSRR AUDIOIN_ADCSRR +#define HWI_AUDIOIN_ADCSRR +#define HW_AUDIOIN_ADCSRR_SET HW(AUDIOIN_ADCSRR_SET) +#define HWA_AUDIOIN_ADCSRR_SET (HWA_AUDIOIN_ADCSRR + 0x4) +#define HWT_AUDIOIN_ADCSRR_SET HWIO_32_WO +#define HWN_AUDIOIN_ADCSRR_SET AUDIOIN_ADCSRR +#define HWI_AUDIOIN_ADCSRR_SET +#define HW_AUDIOIN_ADCSRR_CLR HW(AUDIOIN_ADCSRR_CLR) +#define HWA_AUDIOIN_ADCSRR_CLR (HWA_AUDIOIN_ADCSRR + 0x8) +#define HWT_AUDIOIN_ADCSRR_CLR HWIO_32_WO +#define HWN_AUDIOIN_ADCSRR_CLR AUDIOIN_ADCSRR +#define HWI_AUDIOIN_ADCSRR_CLR +#define HW_AUDIOIN_ADCSRR_TOG HW(AUDIOIN_ADCSRR_TOG) +#define HWA_AUDIOIN_ADCSRR_TOG (HWA_AUDIOIN_ADCSRR + 0xc) +#define HWT_AUDIOIN_ADCSRR_TOG HWIO_32_WO +#define HWN_AUDIOIN_ADCSRR_TOG AUDIOIN_ADCSRR +#define HWI_AUDIOIN_ADCSRR_TOG +#define BP_AUDIOIN_ADCSRR_OSR 31 +#define BM_AUDIOIN_ADCSRR_OSR 0x80000000 +#define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0 +#define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1 +#define BF_AUDIOIN_ADCSRR_OSR(v) (((v) & 0x1) << 31) +#define BFM_AUDIOIN_ADCSRR_OSR(v) BM_AUDIOIN_ADCSRR_OSR +#define BF_AUDIOIN_ADCSRR_OSR_V(e) BF_AUDIOIN_ADCSRR_OSR(BV_AUDIOIN_ADCSRR_OSR__##e) +#define BFM_AUDIOIN_ADCSRR_OSR_V(v) BM_AUDIOIN_ADCSRR_OSR +#define BP_AUDIOIN_ADCSRR_BASEMULT 28 +#define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000 +#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1 +#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2 +#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4 +#define BF_AUDIOIN_ADCSRR_BASEMULT(v) (((v) & 0x7) << 28) +#define BFM_AUDIOIN_ADCSRR_BASEMULT(v) BM_AUDIOIN_ADCSRR_BASEMULT +#define BF_AUDIOIN_ADCSRR_BASEMULT_V(e) BF_AUDIOIN_ADCSRR_BASEMULT(BV_AUDIOIN_ADCSRR_BASEMULT__##e) +#define BFM_AUDIOIN_ADCSRR_BASEMULT_V(v) BM_AUDIOIN_ADCSRR_BASEMULT +#define BP_AUDIOIN_ADCSRR_RSRVD2 27 +#define BM_AUDIOIN_ADCSRR_RSRVD2 0x8000000 +#define BF_AUDIOIN_ADCSRR_RSRVD2(v) (((v) & 0x1) << 27) +#define BFM_AUDIOIN_ADCSRR_RSRVD2(v) BM_AUDIOIN_ADCSRR_RSRVD2 +#define BF_AUDIOIN_ADCSRR_RSRVD2_V(e) BF_AUDIOIN_ADCSRR_RSRVD2(BV_AUDIOIN_ADCSRR_RSRVD2__##e) +#define BFM_AUDIOIN_ADCSRR_RSRVD2_V(v) BM_AUDIOIN_ADCSRR_RSRVD2 +#define BP_AUDIOIN_ADCSRR_SRC_HOLD 24 +#define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x7000000 +#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) (((v) & 0x7) << 24) +#define BFM_AUDIOIN_ADCSRR_SRC_HOLD(v) BM_AUDIOIN_ADCSRR_SRC_HOLD +#define BF_AUDIOIN_ADCSRR_SRC_HOLD_V(e) BF_AUDIOIN_ADCSRR_SRC_HOLD(BV_AUDIOIN_ADCSRR_SRC_HOLD__##e) +#define BFM_AUDIOIN_ADCSRR_SRC_HOLD_V(v) BM_AUDIOIN_ADCSRR_SRC_HOLD +#define BP_AUDIOIN_ADCSRR_RSRVD1 21 +#define BM_AUDIOIN_ADCSRR_RSRVD1 0xe00000 +#define BF_AUDIOIN_ADCSRR_RSRVD1(v) (((v) & 0x7) << 21) +#define BFM_AUDIOIN_ADCSRR_RSRVD1(v) BM_AUDIOIN_ADCSRR_RSRVD1 +#define BF_AUDIOIN_ADCSRR_RSRVD1_V(e) BF_AUDIOIN_ADCSRR_RSRVD1(BV_AUDIOIN_ADCSRR_RSRVD1__##e) +#define BFM_AUDIOIN_ADCSRR_RSRVD1_V(v) BM_AUDIOIN_ADCSRR_RSRVD1 +#define BP_AUDIOIN_ADCSRR_SRC_INT 16 +#define BM_AUDIOIN_ADCSRR_SRC_INT 0x1f0000 +#define BF_AUDIOIN_ADCSRR_SRC_INT(v) (((v) & 0x1f) << 16) +#define BFM_AUDIOIN_ADCSRR_SRC_INT(v) BM_AUDIOIN_ADCSRR_SRC_INT +#define BF_AUDIOIN_ADCSRR_SRC_INT_V(e) BF_AUDIOIN_ADCSRR_SRC_INT(BV_AUDIOIN_ADCSRR_SRC_INT__##e) +#define BFM_AUDIOIN_ADCSRR_SRC_INT_V(v) BM_AUDIOIN_ADCSRR_SRC_INT +#define BP_AUDIOIN_ADCSRR_RSRVD0 13 +#define BM_AUDIOIN_ADCSRR_RSRVD0 0xe000 +#define BF_AUDIOIN_ADCSRR_RSRVD0(v) (((v) & 0x7) << 13) +#define BFM_AUDIOIN_ADCSRR_RSRVD0(v) BM_AUDIOIN_ADCSRR_RSRVD0 +#define BF_AUDIOIN_ADCSRR_RSRVD0_V(e) BF_AUDIOIN_ADCSRR_RSRVD0(BV_AUDIOIN_ADCSRR_RSRVD0__##e) +#define BFM_AUDIOIN_ADCSRR_RSRVD0_V(v) BM_AUDIOIN_ADCSRR_RSRVD0 +#define BP_AUDIOIN_ADCSRR_SRC_FRAC 0 +#define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x1fff +#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) (((v) & 0x1fff) << 0) +#define BFM_AUDIOIN_ADCSRR_SRC_FRAC(v) BM_AUDIOIN_ADCSRR_SRC_FRAC +#define BF_AUDIOIN_ADCSRR_SRC_FRAC_V(e) BF_AUDIOIN_ADCSRR_SRC_FRAC(BV_AUDIOIN_ADCSRR_SRC_FRAC__##e) +#define BFM_AUDIOIN_ADCSRR_SRC_FRAC_V(v) BM_AUDIOIN_ADCSRR_SRC_FRAC + +#define HW_AUDIOIN_ADCVOLUME HW(AUDIOIN_ADCVOLUME) +#define HWA_AUDIOIN_ADCVOLUME (0x8004c000 + 0x30) +#define HWT_AUDIOIN_ADCVOLUME HWIO_32_RW +#define HWN_AUDIOIN_ADCVOLUME AUDIOIN_ADCVOLUME +#define HWI_AUDIOIN_ADCVOLUME +#define HW_AUDIOIN_ADCVOLUME_SET HW(AUDIOIN_ADCVOLUME_SET) +#define HWA_AUDIOIN_ADCVOLUME_SET (HWA_AUDIOIN_ADCVOLUME + 0x4) +#define HWT_AUDIOIN_ADCVOLUME_SET HWIO_32_WO +#define HWN_AUDIOIN_ADCVOLUME_SET AUDIOIN_ADCVOLUME +#define HWI_AUDIOIN_ADCVOLUME_SET +#define HW_AUDIOIN_ADCVOLUME_CLR HW(AUDIOIN_ADCVOLUME_CLR) +#define HWA_AUDIOIN_ADCVOLUME_CLR (HWA_AUDIOIN_ADCVOLUME + 0x8) +#define HWT_AUDIOIN_ADCVOLUME_CLR HWIO_32_WO +#define HWN_AUDIOIN_ADCVOLUME_CLR AUDIOIN_ADCVOLUME +#define HWI_AUDIOIN_ADCVOLUME_CLR +#define HW_AUDIOIN_ADCVOLUME_TOG HW(AUDIOIN_ADCVOLUME_TOG) +#define HWA_AUDIOIN_ADCVOLUME_TOG (HWA_AUDIOIN_ADCVOLUME + 0xc) +#define HWT_AUDIOIN_ADCVOLUME_TOG HWIO_32_WO +#define HWN_AUDIOIN_ADCVOLUME_TOG AUDIOIN_ADCVOLUME +#define HWI_AUDIOIN_ADCVOLUME_TOG +#define BP_AUDIOIN_ADCVOLUME_RSRVD5 29 +#define BM_AUDIOIN_ADCVOLUME_RSRVD5 0xe0000000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v) (((v) & 0x7) << 29) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD5(v) BM_AUDIOIN_ADCVOLUME_RSRVD5 +#define BF_AUDIOIN_ADCVOLUME_RSRVD5_V(e) BF_AUDIOIN_ADCVOLUME_RSRVD5(BV_AUDIOIN_ADCVOLUME_RSRVD5__##e) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD5_V(v) BM_AUDIOIN_ADCVOLUME_RSRVD5 +#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 28 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000 +#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v) (((v) & 0x1) << 28) +#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(v) BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT +#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT_V(e) BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT(BV_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT__##e) +#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT_V(v) BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT +#define BP_AUDIOIN_ADCVOLUME_RSRVD4 26 +#define BM_AUDIOIN_ADCVOLUME_RSRVD4 0xc000000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v) (((v) & 0x3) << 26) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD4(v) BM_AUDIOIN_ADCVOLUME_RSRVD4 +#define BF_AUDIOIN_ADCVOLUME_RSRVD4_V(e) BF_AUDIOIN_ADCVOLUME_RSRVD4(BV_AUDIOIN_ADCVOLUME_RSRVD4__##e) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD4_V(v) BM_AUDIOIN_ADCVOLUME_RSRVD4 +#define BP_AUDIOIN_ADCVOLUME_EN_ZCD 25 +#define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x2000000 +#define BF_AUDIOIN_ADCVOLUME_EN_ZCD(v) (((v) & 0x1) << 25) +#define BFM_AUDIOIN_ADCVOLUME_EN_ZCD(v) BM_AUDIOIN_ADCVOLUME_EN_ZCD +#define BF_AUDIOIN_ADCVOLUME_EN_ZCD_V(e) BF_AUDIOIN_ADCVOLUME_EN_ZCD(BV_AUDIOIN_ADCVOLUME_EN_ZCD__##e) +#define BFM_AUDIOIN_ADCVOLUME_EN_ZCD_V(v) BM_AUDIOIN_ADCVOLUME_EN_ZCD +#define BP_AUDIOIN_ADCVOLUME_RSRVD3 24 +#define BM_AUDIOIN_ADCVOLUME_RSRVD3 0x1000000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD3(v) (((v) & 0x1) << 24) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD3(v) BM_AUDIOIN_ADCVOLUME_RSRVD3 +#define BF_AUDIOIN_ADCVOLUME_RSRVD3_V(e) BF_AUDIOIN_ADCVOLUME_RSRVD3(BV_AUDIOIN_ADCVOLUME_RSRVD3__##e) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD3_V(v) BM_AUDIOIN_ADCVOLUME_RSRVD3 +#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0xff0000 +#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) (((v) & 0xff) << 16) +#define BFM_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT +#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT_V(e) BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(BV_AUDIOIN_ADCVOLUME_VOLUME_LEFT__##e) +#define BFM_AUDIOIN_ADCVOLUME_VOLUME_LEFT_V(v) BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT +#define BP_AUDIOIN_ADCVOLUME_RSRVD2 13 +#define BM_AUDIOIN_ADCVOLUME_RSRVD2 0xe000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v) (((v) & 0x7) << 13) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD2(v) BM_AUDIOIN_ADCVOLUME_RSRVD2 +#define BF_AUDIOIN_ADCVOLUME_RSRVD2_V(e) BF_AUDIOIN_ADCVOLUME_RSRVD2(BV_AUDIOIN_ADCVOLUME_RSRVD2__##e) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD2_V(v) BM_AUDIOIN_ADCVOLUME_RSRVD2 +#define BP_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 12 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x1000 +#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) & 0x1) << 12) +#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(v) BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT +#define BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT_V(e) BF_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT(BV_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT__##e) +#define BFM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT_V(v) BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT +#define BP_AUDIOIN_ADCVOLUME_RSRVD1 8 +#define BM_AUDIOIN_ADCVOLUME_RSRVD1 0xf00 +#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v) (((v) & 0xf) << 8) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD1(v) BM_AUDIOIN_ADCVOLUME_RSRVD1 +#define BF_AUDIOIN_ADCVOLUME_RSRVD1_V(e) BF_AUDIOIN_ADCVOLUME_RSRVD1(BV_AUDIOIN_ADCVOLUME_RSRVD1__##e) +#define BFM_AUDIOIN_ADCVOLUME_RSRVD1_V(v) BM_AUDIOIN_ADCVOLUME_RSRVD1 +#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0xff +#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) (((v) & 0xff) << 0) +#define BFM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT +#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT_V(e) BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(BV_AUDIOIN_ADCVOLUME_VOLUME_RIGHT__##e) +#define BFM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT_V(v) BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT + +#define HW_AUDIOIN_ADCDEBUG HW(AUDIOIN_ADCDEBUG) +#define HWA_AUDIOIN_ADCDEBUG (0x8004c000 + 0x40) +#define HWT_AUDIOIN_ADCDEBUG HWIO_32_RW +#define HWN_AUDIOIN_ADCDEBUG AUDIOIN_ADCDEBUG +#define HWI_AUDIOIN_ADCDEBUG +#define HW_AUDIOIN_ADCDEBUG_SET HW(AUDIOIN_ADCDEBUG_SET) +#define HWA_AUDIOIN_ADCDEBUG_SET (HWA_AUDIOIN_ADCDEBUG + 0x4) +#define HWT_AUDIOIN_ADCDEBUG_SET HWIO_32_WO +#define HWN_AUDIOIN_ADCDEBUG_SET AUDIOIN_ADCDEBUG +#define HWI_AUDIOIN_ADCDEBUG_SET +#define HW_AUDIOIN_ADCDEBUG_CLR HW(AUDIOIN_ADCDEBUG_CLR) +#define HWA_AUDIOIN_ADCDEBUG_CLR (HWA_AUDIOIN_ADCDEBUG + 0x8) +#define HWT_AUDIOIN_ADCDEBUG_CLR HWIO_32_WO +#define HWN_AUDIOIN_ADCDEBUG_CLR AUDIOIN_ADCDEBUG +#define HWI_AUDIOIN_ADCDEBUG_CLR +#define HW_AUDIOIN_ADCDEBUG_TOG HW(AUDIOIN_ADCDEBUG_TOG) +#define HWA_AUDIOIN_ADCDEBUG_TOG (HWA_AUDIOIN_ADCDEBUG + 0xc) +#define HWT_AUDIOIN_ADCDEBUG_TOG HWIO_32_WO +#define HWN_AUDIOIN_ADCDEBUG_TOG AUDIOIN_ADCDEBUG +#define HWI_AUDIOIN_ADCDEBUG_TOG +#define BP_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 31 +#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000 +#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v) (((v) & 0x1) << 31) +#define BFM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(v) BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA +#define BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA_V(e) BF_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA(BV_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA__##e) +#define BFM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA_V(v) BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA +#define BP_AUDIOIN_ADCDEBUG_RSRVD1 4 +#define BM_AUDIOIN_ADCDEBUG_RSRVD1 0x7ffffff0 +#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v) (((v) & 0x7ffffff) << 4) +#define BFM_AUDIOIN_ADCDEBUG_RSRVD1(v) BM_AUDIOIN_ADCDEBUG_RSRVD1 +#define BF_AUDIOIN_ADCDEBUG_RSRVD1_V(e) BF_AUDIOIN_ADCDEBUG_RSRVD1(BV_AUDIOIN_ADCDEBUG_RSRVD1__##e) +#define BFM_AUDIOIN_ADCDEBUG_RSRVD1_V(v) BM_AUDIOIN_ADCDEBUG_RSRVD1 +#define BP_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 3 +#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x8 +#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) (((v) & 0x1) << 3) +#define BFM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(v) BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS +#define BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS_V(e) BF_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS(BV_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS__##e) +#define BFM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS_V(v) BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS +#define BP_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 2 +#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x4 +#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v) (((v) & 0x1) << 2) +#define BFM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(v) BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE +#define BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE_V(e) BF_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE(BV_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE__##e) +#define BFM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE_V(v) BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE +#define BP_AUDIOIN_ADCDEBUG_DMA_PREQ 1 +#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x2 +#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ(v) (((v) & 0x1) << 1) +#define BFM_AUDIOIN_ADCDEBUG_DMA_PREQ(v) BM_AUDIOIN_ADCDEBUG_DMA_PREQ +#define BF_AUDIOIN_ADCDEBUG_DMA_PREQ_V(e) BF_AUDIOIN_ADCDEBUG_DMA_PREQ(BV_AUDIOIN_ADCDEBUG_DMA_PREQ__##e) +#define BFM_AUDIOIN_ADCDEBUG_DMA_PREQ_V(v) BM_AUDIOIN_ADCDEBUG_DMA_PREQ +#define BP_AUDIOIN_ADCDEBUG_FIFO_STATUS 0 +#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x1 +#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(v) (((v) & 0x1) << 0) +#define BFM_AUDIOIN_ADCDEBUG_FIFO_STATUS(v) BM_AUDIOIN_ADCDEBUG_FIFO_STATUS +#define BF_AUDIOIN_ADCDEBUG_FIFO_STATUS_V(e) BF_AUDIOIN_ADCDEBUG_FIFO_STATUS(BV_AUDIOIN_ADCDEBUG_FIFO_STATUS__##e) +#define BFM_AUDIOIN_ADCDEBUG_FIFO_STATUS_V(v) BM_AUDIOIN_ADCDEBUG_FIFO_STATUS + +#define HW_AUDIOIN_ADCVOL HW(AUDIOIN_ADCVOL) +#define HWA_AUDIOIN_ADCVOL (0x8004c000 + 0x50) +#define HWT_AUDIOIN_ADCVOL HWIO_32_RW +#define HWN_AUDIOIN_ADCVOL AUDIOIN_ADCVOL +#define HWI_AUDIOIN_ADCVOL +#define HW_AUDIOIN_ADCVOL_SET HW(AUDIOIN_ADCVOL_SET) +#define HWA_AUDIOIN_ADCVOL_SET (HWA_AUDIOIN_ADCVOL + 0x4) +#define HWT_AUDIOIN_ADCVOL_SET HWIO_32_WO +#define HWN_AUDIOIN_ADCVOL_SET AUDIOIN_ADCVOL +#define HWI_AUDIOIN_ADCVOL_SET +#define HW_AUDIOIN_ADCVOL_CLR HW(AUDIOIN_ADCVOL_CLR) +#define HWA_AUDIOIN_ADCVOL_CLR (HWA_AUDIOIN_ADCVOL + 0x8) +#define HWT_AUDIOIN_ADCVOL_CLR HWIO_32_WO +#define HWN_AUDIOIN_ADCVOL_CLR AUDIOIN_ADCVOL +#define HWI_AUDIOIN_ADCVOL_CLR +#define HW_AUDIOIN_ADCVOL_TOG HW(AUDIOIN_ADCVOL_TOG) +#define HWA_AUDIOIN_ADCVOL_TOG (HWA_AUDIOIN_ADCVOL + 0xc) +#define HWT_AUDIOIN_ADCVOL_TOG HWIO_32_WO +#define HWN_AUDIOIN_ADCVOL_TOG AUDIOIN_ADCVOL +#define HWI_AUDIOIN_ADCVOL_TOG +#define BP_AUDIOIN_ADCVOL_RSRVD4 29 +#define BM_AUDIOIN_ADCVOL_RSRVD4 0xe0000000 +#define BF_AUDIOIN_ADCVOL_RSRVD4(v) (((v) & 0x7) << 29) +#define BFM_AUDIOIN_ADCVOL_RSRVD4(v) BM_AUDIOIN_ADCVOL_RSRVD4 +#define BF_AUDIOIN_ADCVOL_RSRVD4_V(e) BF_AUDIOIN_ADCVOL_RSRVD4(BV_AUDIOIN_ADCVOL_RSRVD4__##e) +#define BFM_AUDIOIN_ADCVOL_RSRVD4_V(v) BM_AUDIOIN_ADCVOL_RSRVD4 +#define BP_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 28 +#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000 +#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v) (((v) & 0x1) << 28) +#define BFM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(v) BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING +#define BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING_V(e) BF_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING(BV_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING__##e) +#define BFM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING_V(v) BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING +#define BP_AUDIOIN_ADCVOL_RSRVD3 26 +#define BM_AUDIOIN_ADCVOL_RSRVD3 0xc000000 +#define BF_AUDIOIN_ADCVOL_RSRVD3(v) (((v) & 0x3) << 26) +#define BFM_AUDIOIN_ADCVOL_RSRVD3(v) BM_AUDIOIN_ADCVOL_RSRVD3 +#define BF_AUDIOIN_ADCVOL_RSRVD3_V(e) BF_AUDIOIN_ADCVOL_RSRVD3(BV_AUDIOIN_ADCVOL_RSRVD3__##e) +#define BFM_AUDIOIN_ADCVOL_RSRVD3_V(v) BM_AUDIOIN_ADCVOL_RSRVD3 +#define BP_AUDIOIN_ADCVOL_EN_ADC_ZCD 25 +#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x2000000 +#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(v) (((v) & 0x1) << 25) +#define BFM_AUDIOIN_ADCVOL_EN_ADC_ZCD(v) BM_AUDIOIN_ADCVOL_EN_ADC_ZCD +#define BF_AUDIOIN_ADCVOL_EN_ADC_ZCD_V(e) BF_AUDIOIN_ADCVOL_EN_ADC_ZCD(BV_AUDIOIN_ADCVOL_EN_ADC_ZCD__##e) +#define BFM_AUDIOIN_ADCVOL_EN_ADC_ZCD_V(v) BM_AUDIOIN_ADCVOL_EN_ADC_ZCD +#define BP_AUDIOIN_ADCVOL_MUTE 24 +#define BM_AUDIOIN_ADCVOL_MUTE 0x1000000 +#define BF_AUDIOIN_ADCVOL_MUTE(v) (((v) & 0x1) << 24) +#define BFM_AUDIOIN_ADCVOL_MUTE(v) BM_AUDIOIN_ADCVOL_MUTE +#define BF_AUDIOIN_ADCVOL_MUTE_V(e) BF_AUDIOIN_ADCVOL_MUTE(BV_AUDIOIN_ADCVOL_MUTE__##e) +#define BFM_AUDIOIN_ADCVOL_MUTE_V(v) BM_AUDIOIN_ADCVOL_MUTE +#define BP_AUDIOIN_ADCVOL_RSRVD2 14 +#define BM_AUDIOIN_ADCVOL_RSRVD2 0xffc000 +#define BF_AUDIOIN_ADCVOL_RSRVD2(v) (((v) & 0x3ff) << 14) +#define BFM_AUDIOIN_ADCVOL_RSRVD2(v) BM_AUDIOIN_ADCVOL_RSRVD2 +#define BF_AUDIOIN_ADCVOL_RSRVD2_V(e) BF_AUDIOIN_ADCVOL_RSRVD2(BV_AUDIOIN_ADCVOL_RSRVD2__##e) +#define BFM_AUDIOIN_ADCVOL_RSRVD2_V(v) BM_AUDIOIN_ADCVOL_RSRVD2 +#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 +#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x3000 +#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) (((v) & 0x3) << 12) +#define BFM_AUDIOIN_ADCVOL_SELECT_LEFT(v) BM_AUDIOIN_ADCVOL_SELECT_LEFT +#define BF_AUDIOIN_ADCVOL_SELECT_LEFT_V(e) BF_AUDIOIN_ADCVOL_SELECT_LEFT(BV_AUDIOIN_ADCVOL_SELECT_LEFT__##e) +#define BFM_AUDIOIN_ADCVOL_SELECT_LEFT_V(v) BM_AUDIOIN_ADCVOL_SELECT_LEFT +#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 +#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0xf00 +#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) (((v) & 0xf) << 8) +#define BFM_AUDIOIN_ADCVOL_GAIN_LEFT(v) BM_AUDIOIN_ADCVOL_GAIN_LEFT +#define BF_AUDIOIN_ADCVOL_GAIN_LEFT_V(e) BF_AUDIOIN_ADCVOL_GAIN_LEFT(BV_AUDIOIN_ADCVOL_GAIN_LEFT__##e) +#define BFM_AUDIOIN_ADCVOL_GAIN_LEFT_V(v) BM_AUDIOIN_ADCVOL_GAIN_LEFT +#define BP_AUDIOIN_ADCVOL_RSRVD1 6 +#define BM_AUDIOIN_ADCVOL_RSRVD1 0xc0 +#define BF_AUDIOIN_ADCVOL_RSRVD1(v) (((v) & 0x3) << 6) +#define BFM_AUDIOIN_ADCVOL_RSRVD1(v) BM_AUDIOIN_ADCVOL_RSRVD1 +#define BF_AUDIOIN_ADCVOL_RSRVD1_V(e) BF_AUDIOIN_ADCVOL_RSRVD1(BV_AUDIOIN_ADCVOL_RSRVD1__##e) +#define BFM_AUDIOIN_ADCVOL_RSRVD1_V(v) BM_AUDIOIN_ADCVOL_RSRVD1 +#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 +#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x30 +#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) (((v) & 0x3) << 4) +#define BFM_AUDIOIN_ADCVOL_SELECT_RIGHT(v) BM_AUDIOIN_ADCVOL_SELECT_RIGHT +#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT_V(e) BF_AUDIOIN_ADCVOL_SELECT_RIGHT(BV_AUDIOIN_ADCVOL_SELECT_RIGHT__##e) +#define BFM_AUDIOIN_ADCVOL_SELECT_RIGHT_V(v) BM_AUDIOIN_ADCVOL_SELECT_RIGHT +#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 +#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0xf +#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) (((v) & 0xf) << 0) +#define BFM_AUDIOIN_ADCVOL_GAIN_RIGHT(v) BM_AUDIOIN_ADCVOL_GAIN_RIGHT +#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT_V(e) BF_AUDIOIN_ADCVOL_GAIN_RIGHT(BV_AUDIOIN_ADCVOL_GAIN_RIGHT__##e) +#define BFM_AUDIOIN_ADCVOL_GAIN_RIGHT_V(v) BM_AUDIOIN_ADCVOL_GAIN_RIGHT + +#define HW_AUDIOIN_MICLINE HW(AUDIOIN_MICLINE) +#define HWA_AUDIOIN_MICLINE (0x8004c000 + 0x60) +#define HWT_AUDIOIN_MICLINE HWIO_32_RW +#define HWN_AUDIOIN_MICLINE AUDIOIN_MICLINE +#define HWI_AUDIOIN_MICLINE +#define HW_AUDIOIN_MICLINE_SET HW(AUDIOIN_MICLINE_SET) +#define HWA_AUDIOIN_MICLINE_SET (HWA_AUDIOIN_MICLINE + 0x4) +#define HWT_AUDIOIN_MICLINE_SET HWIO_32_WO +#define HWN_AUDIOIN_MICLINE_SET AUDIOIN_MICLINE +#define HWI_AUDIOIN_MICLINE_SET +#define HW_AUDIOIN_MICLINE_CLR HW(AUDIOIN_MICLINE_CLR) +#define HWA_AUDIOIN_MICLINE_CLR (HWA_AUDIOIN_MICLINE + 0x8) +#define HWT_AUDIOIN_MICLINE_CLR HWIO_32_WO +#define HWN_AUDIOIN_MICLINE_CLR AUDIOIN_MICLINE +#define HWI_AUDIOIN_MICLINE_CLR +#define HW_AUDIOIN_MICLINE_TOG HW(AUDIOIN_MICLINE_TOG) +#define HWA_AUDIOIN_MICLINE_TOG (HWA_AUDIOIN_MICLINE + 0xc) +#define HWT_AUDIOIN_MICLINE_TOG HWIO_32_WO +#define HWN_AUDIOIN_MICLINE_TOG AUDIOIN_MICLINE +#define HWI_AUDIOIN_MICLINE_TOG +#define BP_AUDIOIN_MICLINE_RSRVD6 30 +#define BM_AUDIOIN_MICLINE_RSRVD6 0xc0000000 +#define BF_AUDIOIN_MICLINE_RSRVD6(v) (((v) & 0x3) << 30) +#define BFM_AUDIOIN_MICLINE_RSRVD6(v) BM_AUDIOIN_MICLINE_RSRVD6 +#define BF_AUDIOIN_MICLINE_RSRVD6_V(e) BF_AUDIOIN_MICLINE_RSRVD6(BV_AUDIOIN_MICLINE_RSRVD6__##e) +#define BFM_AUDIOIN_MICLINE_RSRVD6_V(v) BM_AUDIOIN_MICLINE_RSRVD6 +#define BP_AUDIOIN_MICLINE_DIVIDE_LINE1 29 +#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000 +#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1(v) (((v) & 0x1) << 29) +#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE1(v) BM_AUDIOIN_MICLINE_DIVIDE_LINE1 +#define BF_AUDIOIN_MICLINE_DIVIDE_LINE1_V(e) BF_AUDIOIN_MICLINE_DIVIDE_LINE1(BV_AUDIOIN_MICLINE_DIVIDE_LINE1__##e) +#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE1_V(v) BM_AUDIOIN_MICLINE_DIVIDE_LINE1 +#define BP_AUDIOIN_MICLINE_DIVIDE_LINE2 28 +#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000 +#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2(v) (((v) & 0x1) << 28) +#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE2(v) BM_AUDIOIN_MICLINE_DIVIDE_LINE2 +#define BF_AUDIOIN_MICLINE_DIVIDE_LINE2_V(e) BF_AUDIOIN_MICLINE_DIVIDE_LINE2(BV_AUDIOIN_MICLINE_DIVIDE_LINE2__##e) +#define BFM_AUDIOIN_MICLINE_DIVIDE_LINE2_V(v) BM_AUDIOIN_MICLINE_DIVIDE_LINE2 +#define BP_AUDIOIN_MICLINE_RSRVD5 25 +#define BM_AUDIOIN_MICLINE_RSRVD5 0xe000000 +#define BF_AUDIOIN_MICLINE_RSRVD5(v) (((v) & 0x7) << 25) +#define BFM_AUDIOIN_MICLINE_RSRVD5(v) BM_AUDIOIN_MICLINE_RSRVD5 +#define BF_AUDIOIN_MICLINE_RSRVD5_V(e) BF_AUDIOIN_MICLINE_RSRVD5(BV_AUDIOIN_MICLINE_RSRVD5__##e) +#define BFM_AUDIOIN_MICLINE_RSRVD5_V(v) BM_AUDIOIN_MICLINE_RSRVD5 +#define BP_AUDIOIN_MICLINE_MIC_SELECT 24 +#define BM_AUDIOIN_MICLINE_MIC_SELECT 0x1000000 +#define BF_AUDIOIN_MICLINE_MIC_SELECT(v) (((v) & 0x1) << 24) +#define BFM_AUDIOIN_MICLINE_MIC_SELECT(v) BM_AUDIOIN_MICLINE_MIC_SELECT +#define BF_AUDIOIN_MICLINE_MIC_SELECT_V(e) BF_AUDIOIN_MICLINE_MIC_SELECT(BV_AUDIOIN_MICLINE_MIC_SELECT__##e) +#define BFM_AUDIOIN_MICLINE_MIC_SELECT_V(v) BM_AUDIOIN_MICLINE_MIC_SELECT +#define BP_AUDIOIN_MICLINE_RSRVD4 22 +#define BM_AUDIOIN_MICLINE_RSRVD4 0xc00000 +#define BF_AUDIOIN_MICLINE_RSRVD4(v) (((v) & 0x3) << 22) +#define BFM_AUDIOIN_MICLINE_RSRVD4(v) BM_AUDIOIN_MICLINE_RSRVD4 +#define BF_AUDIOIN_MICLINE_RSRVD4_V(e) BF_AUDIOIN_MICLINE_RSRVD4(BV_AUDIOIN_MICLINE_RSRVD4__##e) +#define BFM_AUDIOIN_MICLINE_RSRVD4_V(v) BM_AUDIOIN_MICLINE_RSRVD4 +#define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20 +#define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x300000 +#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__Off 0x0 +#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__2KOhm 0x1 +#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__4KOhm 0x2 +#define BV_AUDIOIN_MICLINE_MIC_RESISTOR__8KOhm 0x3 +#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) (((v) & 0x3) << 20) +#define BFM_AUDIOIN_MICLINE_MIC_RESISTOR(v) BM_AUDIOIN_MICLINE_MIC_RESISTOR +#define BF_AUDIOIN_MICLINE_MIC_RESISTOR_V(e) BF_AUDIOIN_MICLINE_MIC_RESISTOR(BV_AUDIOIN_MICLINE_MIC_RESISTOR__##e) +#define BFM_AUDIOIN_MICLINE_MIC_RESISTOR_V(v) BM_AUDIOIN_MICLINE_MIC_RESISTOR +#define BP_AUDIOIN_MICLINE_RSRVD3 19 +#define BM_AUDIOIN_MICLINE_RSRVD3 0x80000 +#define BF_AUDIOIN_MICLINE_RSRVD3(v) (((v) & 0x1) << 19) +#define BFM_AUDIOIN_MICLINE_RSRVD3(v) BM_AUDIOIN_MICLINE_RSRVD3 +#define BF_AUDIOIN_MICLINE_RSRVD3_V(e) BF_AUDIOIN_MICLINE_RSRVD3(BV_AUDIOIN_MICLINE_RSRVD3__##e) +#define BFM_AUDIOIN_MICLINE_RSRVD3_V(v) BM_AUDIOIN_MICLINE_RSRVD3 +#define BP_AUDIOIN_MICLINE_MIC_BIAS 16 +#define BM_AUDIOIN_MICLINE_MIC_BIAS 0x70000 +#define BF_AUDIOIN_MICLINE_MIC_BIAS(v) (((v) & 0x7) << 16) +#define BFM_AUDIOIN_MICLINE_MIC_BIAS(v) BM_AUDIOIN_MICLINE_MIC_BIAS +#define BF_AUDIOIN_MICLINE_MIC_BIAS_V(e) BF_AUDIOIN_MICLINE_MIC_BIAS(BV_AUDIOIN_MICLINE_MIC_BIAS__##e) +#define BFM_AUDIOIN_MICLINE_MIC_BIAS_V(v) BM_AUDIOIN_MICLINE_MIC_BIAS +#define BP_AUDIOIN_MICLINE_RSRVD2 6 +#define BM_AUDIOIN_MICLINE_RSRVD2 0xffc0 +#define BF_AUDIOIN_MICLINE_RSRVD2(v) (((v) & 0x3ff) << 6) +#define BFM_AUDIOIN_MICLINE_RSRVD2(v) BM_AUDIOIN_MICLINE_RSRVD2 +#define BF_AUDIOIN_MICLINE_RSRVD2_V(e) BF_AUDIOIN_MICLINE_RSRVD2(BV_AUDIOIN_MICLINE_RSRVD2__##e) +#define BFM_AUDIOIN_MICLINE_RSRVD2_V(v) BM_AUDIOIN_MICLINE_RSRVD2 +#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4 +#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x30 +#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) (((v) & 0x3) << 4) +#define BFM_AUDIOIN_MICLINE_MIC_CHOPCLK(v) BM_AUDIOIN_MICLINE_MIC_CHOPCLK +#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK_V(e) BF_AUDIOIN_MICLINE_MIC_CHOPCLK(BV_AUDIOIN_MICLINE_MIC_CHOPCLK__##e) +#define BFM_AUDIOIN_MICLINE_MIC_CHOPCLK_V(v) BM_AUDIOIN_MICLINE_MIC_CHOPCLK +#define BP_AUDIOIN_MICLINE_RSRVD1 2 +#define BM_AUDIOIN_MICLINE_RSRVD1 0xc +#define BF_AUDIOIN_MICLINE_RSRVD1(v) (((v) & 0x3) << 2) +#define BFM_AUDIOIN_MICLINE_RSRVD1(v) BM_AUDIOIN_MICLINE_RSRVD1 +#define BF_AUDIOIN_MICLINE_RSRVD1_V(e) BF_AUDIOIN_MICLINE_RSRVD1(BV_AUDIOIN_MICLINE_RSRVD1__##e) +#define BFM_AUDIOIN_MICLINE_RSRVD1_V(v) BM_AUDIOIN_MICLINE_RSRVD1 +#define BP_AUDIOIN_MICLINE_MIC_GAIN 0 +#define BM_AUDIOIN_MICLINE_MIC_GAIN 0x3 +#define BV_AUDIOIN_MICLINE_MIC_GAIN__0dB 0x0 +#define BV_AUDIOIN_MICLINE_MIC_GAIN__20dB 0x1 +#define BV_AUDIOIN_MICLINE_MIC_GAIN__30dB 0x2 +#define BV_AUDIOIN_MICLINE_MIC_GAIN__40dB 0x3 +#define BF_AUDIOIN_MICLINE_MIC_GAIN(v) (((v) & 0x3) << 0) +#define BFM_AUDIOIN_MICLINE_MIC_GAIN(v) BM_AUDIOIN_MICLINE_MIC_GAIN +#define BF_AUDIOIN_MICLINE_MIC_GAIN_V(e) BF_AUDIOIN_MICLINE_MIC_GAIN(BV_AUDIOIN_MICLINE_MIC_GAIN__##e) +#define BFM_AUDIOIN_MICLINE_MIC_GAIN_V(v) BM_AUDIOIN_MICLINE_MIC_GAIN + +#define HW_AUDIOIN_ANACLKCTRL HW(AUDIOIN_ANACLKCTRL) +#define HWA_AUDIOIN_ANACLKCTRL (0x8004c000 + 0x70) +#define HWT_AUDIOIN_ANACLKCTRL HWIO_32_RW +#define HWN_AUDIOIN_ANACLKCTRL AUDIOIN_ANACLKCTRL +#define HWI_AUDIOIN_ANACLKCTRL +#define HW_AUDIOIN_ANACLKCTRL_SET HW(AUDIOIN_ANACLKCTRL_SET) +#define HWA_AUDIOIN_ANACLKCTRL_SET (HWA_AUDIOIN_ANACLKCTRL + 0x4) +#define HWT_AUDIOIN_ANACLKCTRL_SET HWIO_32_WO +#define HWN_AUDIOIN_ANACLKCTRL_SET AUDIOIN_ANACLKCTRL +#define HWI_AUDIOIN_ANACLKCTRL_SET +#define HW_AUDIOIN_ANACLKCTRL_CLR HW(AUDIOIN_ANACLKCTRL_CLR) +#define HWA_AUDIOIN_ANACLKCTRL_CLR (HWA_AUDIOIN_ANACLKCTRL + 0x8) +#define HWT_AUDIOIN_ANACLKCTRL_CLR HWIO_32_WO +#define HWN_AUDIOIN_ANACLKCTRL_CLR AUDIOIN_ANACLKCTRL +#define HWI_AUDIOIN_ANACLKCTRL_CLR +#define HW_AUDIOIN_ANACLKCTRL_TOG HW(AUDIOIN_ANACLKCTRL_TOG) +#define HWA_AUDIOIN_ANACLKCTRL_TOG (HWA_AUDIOIN_ANACLKCTRL + 0xc) +#define HWT_AUDIOIN_ANACLKCTRL_TOG HWIO_32_WO +#define HWN_AUDIOIN_ANACLKCTRL_TOG AUDIOIN_ANACLKCTRL +#define HWI_AUDIOIN_ANACLKCTRL_TOG +#define BP_AUDIOIN_ANACLKCTRL_CLKGATE 31 +#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 +#define BF_AUDIOIN_ANACLKCTRL_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_AUDIOIN_ANACLKCTRL_CLKGATE(v) BM_AUDIOIN_ANACLKCTRL_CLKGATE +#define BF_AUDIOIN_ANACLKCTRL_CLKGATE_V(e) BF_AUDIOIN_ANACLKCTRL_CLKGATE(BV_AUDIOIN_ANACLKCTRL_CLKGATE__##e) +#define BFM_AUDIOIN_ANACLKCTRL_CLKGATE_V(v) BM_AUDIOIN_ANACLKCTRL_CLKGATE +#define BP_AUDIOIN_ANACLKCTRL_RSRVD4 11 +#define BM_AUDIOIN_ANACLKCTRL_RSRVD4 0x7ffff800 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v) (((v) & 0xfffff) << 11) +#define BFM_AUDIOIN_ANACLKCTRL_RSRVD4(v) BM_AUDIOIN_ANACLKCTRL_RSRVD4 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD4_V(e) BF_AUDIOIN_ANACLKCTRL_RSRVD4(BV_AUDIOIN_ANACLKCTRL_RSRVD4__##e) +#define BFM_AUDIOIN_ANACLKCTRL_RSRVD4_V(v) BM_AUDIOIN_ANACLKCTRL_RSRVD4 +#define BP_AUDIOIN_ANACLKCTRL_DITHER_OFF 10 +#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x400 +#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(v) (((v) & 0x1) << 10) +#define BFM_AUDIOIN_ANACLKCTRL_DITHER_OFF(v) BM_AUDIOIN_ANACLKCTRL_DITHER_OFF +#define BF_AUDIOIN_ANACLKCTRL_DITHER_OFF_V(e) BF_AUDIOIN_ANACLKCTRL_DITHER_OFF(BV_AUDIOIN_ANACLKCTRL_DITHER_OFF__##e) +#define BFM_AUDIOIN_ANACLKCTRL_DITHER_OFF_V(v) BM_AUDIOIN_ANACLKCTRL_DITHER_OFF +#define BP_AUDIOIN_ANACLKCTRL_SLOW_DITHER 9 +#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x200 +#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v) (((v) & 0x1) << 9) +#define BFM_AUDIOIN_ANACLKCTRL_SLOW_DITHER(v) BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER +#define BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER_V(e) BF_AUDIOIN_ANACLKCTRL_SLOW_DITHER(BV_AUDIOIN_ANACLKCTRL_SLOW_DITHER__##e) +#define BFM_AUDIOIN_ANACLKCTRL_SLOW_DITHER_V(v) BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER +#define BP_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 8 +#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x100 +#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v) (((v) & 0x1) << 8) +#define BFM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(v) BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK +#define BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK_V(e) BF_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK(BV_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK__##e) +#define BFM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK_V(v) BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK +#define BP_AUDIOIN_ANACLKCTRL_RSRVD3 6 +#define BM_AUDIOIN_ANACLKCTRL_RSRVD3 0xc0 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v) (((v) & 0x3) << 6) +#define BFM_AUDIOIN_ANACLKCTRL_RSRVD3(v) BM_AUDIOIN_ANACLKCTRL_RSRVD3 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD3_V(e) BF_AUDIOIN_ANACLKCTRL_RSRVD3(BV_AUDIOIN_ANACLKCTRL_RSRVD3__##e) +#define BFM_AUDIOIN_ANACLKCTRL_RSRVD3_V(v) BM_AUDIOIN_ANACLKCTRL_RSRVD3 +#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 4 +#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 0x30 +#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v) (((v) & 0x3) << 4) +#define BFM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v) BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT +#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT_V(e) BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(BV_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT__##e) +#define BFM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT_V(v) BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT +#define BP_AUDIOIN_ANACLKCTRL_RSRVD2 3 +#define BM_AUDIOIN_ANACLKCTRL_RSRVD2 0x8 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD2(v) (((v) & 0x1) << 3) +#define BFM_AUDIOIN_ANACLKCTRL_RSRVD2(v) BM_AUDIOIN_ANACLKCTRL_RSRVD2 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD2_V(e) BF_AUDIOIN_ANACLKCTRL_RSRVD2(BV_AUDIOIN_ANACLKCTRL_RSRVD2__##e) +#define BFM_AUDIOIN_ANACLKCTRL_RSRVD2_V(v) BM_AUDIOIN_ANACLKCTRL_RSRVD2 +#define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0 +#define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x7 +#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) (((v) & 0x7) << 0) +#define BFM_AUDIOIN_ANACLKCTRL_ADCDIV(v) BM_AUDIOIN_ANACLKCTRL_ADCDIV +#define BF_AUDIOIN_ANACLKCTRL_ADCDIV_V(e) BF_AUDIOIN_ANACLKCTRL_ADCDIV(BV_AUDIOIN_ANACLKCTRL_ADCDIV__##e) +#define BFM_AUDIOIN_ANACLKCTRL_ADCDIV_V(v) BM_AUDIOIN_ANACLKCTRL_ADCDIV + +#define HW_AUDIOIN_DATA HW(AUDIOIN_DATA) +#define HWA_AUDIOIN_DATA (0x8004c000 + 0x80) +#define HWT_AUDIOIN_DATA HWIO_32_RW +#define HWN_AUDIOIN_DATA AUDIOIN_DATA +#define HWI_AUDIOIN_DATA +#define HW_AUDIOIN_DATA_SET HW(AUDIOIN_DATA_SET) +#define HWA_AUDIOIN_DATA_SET (HWA_AUDIOIN_DATA + 0x4) +#define HWT_AUDIOIN_DATA_SET HWIO_32_WO +#define HWN_AUDIOIN_DATA_SET AUDIOIN_DATA +#define HWI_AUDIOIN_DATA_SET +#define HW_AUDIOIN_DATA_CLR HW(AUDIOIN_DATA_CLR) +#define HWA_AUDIOIN_DATA_CLR (HWA_AUDIOIN_DATA + 0x8) +#define HWT_AUDIOIN_DATA_CLR HWIO_32_WO +#define HWN_AUDIOIN_DATA_CLR AUDIOIN_DATA +#define HWI_AUDIOIN_DATA_CLR +#define HW_AUDIOIN_DATA_TOG HW(AUDIOIN_DATA_TOG) +#define HWA_AUDIOIN_DATA_TOG (HWA_AUDIOIN_DATA + 0xc) +#define HWT_AUDIOIN_DATA_TOG HWIO_32_WO +#define HWN_AUDIOIN_DATA_TOG AUDIOIN_DATA +#define HWI_AUDIOIN_DATA_TOG +#define BP_AUDIOIN_DATA_HIGH 16 +#define BM_AUDIOIN_DATA_HIGH 0xffff0000 +#define BF_AUDIOIN_DATA_HIGH(v) (((v) & 0xffff) << 16) +#define BFM_AUDIOIN_DATA_HIGH(v) BM_AUDIOIN_DATA_HIGH +#define BF_AUDIOIN_DATA_HIGH_V(e) BF_AUDIOIN_DATA_HIGH(BV_AUDIOIN_DATA_HIGH__##e) +#define BFM_AUDIOIN_DATA_HIGH_V(v) BM_AUDIOIN_DATA_HIGH +#define BP_AUDIOIN_DATA_LOW 0 +#define BM_AUDIOIN_DATA_LOW 0xffff +#define BF_AUDIOIN_DATA_LOW(v) (((v) & 0xffff) << 0) +#define BFM_AUDIOIN_DATA_LOW(v) BM_AUDIOIN_DATA_LOW +#define BF_AUDIOIN_DATA_LOW_V(e) BF_AUDIOIN_DATA_LOW(BV_AUDIOIN_DATA_LOW__##e) +#define BFM_AUDIOIN_DATA_LOW_V(v) BM_AUDIOIN_DATA_LOW + +#endif /* __HEADERGEN_IMX233_AUDIOIN_H__*/ diff --git a/firmware/target/arm/imx233/regs/imx233/audioout.h b/firmware/target/arm/imx233/regs/imx233/audioout.h new file mode 100644 index 0000000000..9b7d9ba119 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/audioout.h @@ -0,0 +1,1313 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * imx233 version: 2.4.0 + * imx233 authors: Amaury Pouly + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_IMX233_AUDIOOUT_H__ +#define __HEADERGEN_IMX233_AUDIOOUT_H__ + +#define HW_AUDIOOUT_CTRL HW(AUDIOOUT_CTRL) +#define HWA_AUDIOOUT_CTRL (0x80048000 + 0x0) +#define HWT_AUDIOOUT_CTRL HWIO_32_RW +#define HWN_AUDIOOUT_CTRL AUDIOOUT_CTRL +#define HWI_AUDIOOUT_CTRL +#define HW_AUDIOOUT_CTRL_SET HW(AUDIOOUT_CTRL_SET) +#define HWA_AUDIOOUT_CTRL_SET (HWA_AUDIOOUT_CTRL + 0x4) +#define HWT_AUDIOOUT_CTRL_SET HWIO_32_WO +#define HWN_AUDIOOUT_CTRL_SET AUDIOOUT_CTRL +#define HWI_AUDIOOUT_CTRL_SET +#define HW_AUDIOOUT_CTRL_CLR HW(AUDIOOUT_CTRL_CLR) +#define HWA_AUDIOOUT_CTRL_CLR (HWA_AUDIOOUT_CTRL + 0x8) +#define HWT_AUDIOOUT_CTRL_CLR HWIO_32_WO +#define HWN_AUDIOOUT_CTRL_CLR AUDIOOUT_CTRL +#define HWI_AUDIOOUT_CTRL_CLR +#define HW_AUDIOOUT_CTRL_TOG HW(AUDIOOUT_CTRL_TOG) +#define HWA_AUDIOOUT_CTRL_TOG (HWA_AUDIOOUT_CTRL + 0xc) +#define HWT_AUDIOOUT_CTRL_TOG HWIO_32_WO +#define HWN_AUDIOOUT_CTRL_TOG AUDIOOUT_CTRL +#define HWI_AUDIOOUT_CTRL_TOG +#define BP_AUDIOOUT_CTRL_SFTRST 31 +#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 +#define BF_AUDIOOUT_CTRL_SFTRST(v) (((v) & 0x1) << 31) +#define BFM_AUDIOOUT_CTRL_SFTRST(v) BM_AUDIOOUT_CTRL_SFTRST +#define BF_AUDIOOUT_CTRL_SFTRST_V(e) BF_AUDIOOUT_CTRL_SFTRST(BV_AUDIOOUT_CTRL_SFTRST__##e) +#define BFM_AUDIOOUT_CTRL_SFTRST_V(v) BM_AUDIOOUT_CTRL_SFTRST +#define BP_AUDIOOUT_CTRL_CLKGATE 30 +#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 +#define BF_AUDIOOUT_CTRL_CLKGATE(v) (((v) & 0x1) << 30) +#define BFM_AUDIOOUT_CTRL_CLKGATE(v) BM_AUDIOOUT_CTRL_CLKGATE +#define BF_AUDIOOUT_CTRL_CLKGATE_V(e) BF_AUDIOOUT_CTRL_CLKGATE(BV_AUDIOOUT_CTRL_CLKGATE__##e) +#define BFM_AUDIOOUT_CTRL_CLKGATE_V(v) BM_AUDIOOUT_CTRL_CLKGATE +#define BP_AUDIOOUT_CTRL_RSRVD4 21 +#define BM_AUDIOOUT_CTRL_RSRVD4 0x3fe00000 +#define BF_AUDIOOUT_CTRL_RSRVD4(v) (((v) & 0x1ff) << 21) +#define BFM_AUDIOOUT_CTRL_RSRVD4(v) BM_AUDIOOUT_CTRL_RSRVD4 +#define BF_AUDIOOUT_CTRL_RSRVD4_V(e) BF_AUDIOOUT_CTRL_RSRVD4(BV_AUDIOOUT_CTRL_RSRVD4__##e) +#define BFM_AUDIOOUT_CTRL_RSRVD4_V(v) BM_AUDIOOUT_CTRL_RSRVD4 +#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16 +#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x1f0000 +#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) (((v) & 0x1f) << 16) +#define BFM_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) BM_AUDIOOUT_CTRL_DMAWAIT_COUNT +#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT_V(e) BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(BV_AUDIOOUT_CTRL_DMAWAIT_COUNT__##e) +#define BFM_AUDIOOUT_CTRL_DMAWAIT_COUNT_V(v) BM_AUDIOOUT_CTRL_DMAWAIT_COUNT +#define BP_AUDIOOUT_CTRL_RSRVD3 15 +#define BM_AUDIOOUT_CTRL_RSRVD3 0x8000 +#define BF_AUDIOOUT_CTRL_RSRVD3(v) (((v) & 0x1) << 15) +#define BFM_AUDIOOUT_CTRL_RSRVD3(v) BM_AUDIOOUT_CTRL_RSRVD3 +#define BF_AUDIOOUT_CTRL_RSRVD3_V(e) BF_AUDIOOUT_CTRL_RSRVD3(BV_AUDIOOUT_CTRL_RSRVD3__##e) +#define BFM_AUDIOOUT_CTRL_RSRVD3_V(v) BM_AUDIOOUT_CTRL_RSRVD3 +#define BP_AUDIOOUT_CTRL_LR_SWAP 14 +#define BM_AUDIOOUT_CTRL_LR_SWAP 0x4000 +#define BF_AUDIOOUT_CTRL_LR_SWAP(v) (((v) & 0x1) << 14) +#define BFM_AUDIOOUT_CTRL_LR_SWAP(v) BM_AUDIOOUT_CTRL_LR_SWAP +#define BF_AUDIOOUT_CTRL_LR_SWAP_V(e) BF_AUDIOOUT_CTRL_LR_SWAP(BV_AUDIOOUT_CTRL_LR_SWAP__##e) +#define BFM_AUDIOOUT_CTRL_LR_SWAP_V(v) BM_AUDIOOUT_CTRL_LR_SWAP +#define BP_AUDIOOUT_CTRL_EDGE_SYNC 13 +#define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x2000 +#define BF_AUDIOOUT_CTRL_EDGE_SYNC(v) (((v) & 0x1) << 13) +#define BFM_AUDIOOUT_CTRL_EDGE_SYNC(v) BM_AUDIOOUT_CTRL_EDGE_SYNC +#define BF_AUDIOOUT_CTRL_EDGE_SYNC_V(e) BF_AUDIOOUT_CTRL_EDGE_SYNC(BV_AUDIOOUT_CTRL_EDGE_SYNC__##e) +#define BFM_AUDIOOUT_CTRL_EDGE_SYNC_V(v) BM_AUDIOOUT_CTRL_EDGE_SYNC +#define BP_AUDIOOUT_CTRL_INVERT_1BIT 12 +#define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x1000 +#define BF_AUDIOOUT_CTRL_INVERT_1BIT(v) (((v) & 0x1) << 12) +#define BFM_AUDIOOUT_CTRL_INVERT_1BIT(v) BM_AUDIOOUT_CTRL_INVERT_1BIT +#define BF_AUDIOOUT_CTRL_INVERT_1BIT_V(e) BF_AUDIOOUT_CTRL_INVERT_1BIT(BV_AUDIOOUT_CTRL_INVERT_1BIT__##e) +#define BFM_AUDIOOUT_CTRL_INVERT_1BIT_V(v) BM_AUDIOOUT_CTRL_INVERT_1BIT +#define BP_AUDIOOUT_CTRL_RSRVD2 10 +#define BM_AUDIOOUT_CTRL_RSRVD2 0xc00 +#define BF_AUDIOOUT_CTRL_RSRVD2(v) (((v) & 0x3) << 10) +#define BFM_AUDIOOUT_CTRL_RSRVD2(v) BM_AUDIOOUT_CTRL_RSRVD2 +#define BF_AUDIOOUT_CTRL_RSRVD2_V(e) BF_AUDIOOUT_CTRL_RSRVD2(BV_AUDIOOUT_CTRL_RSRVD2__##e) +#define BFM_AUDIOOUT_CTRL_RSRVD2_V(v) BM_AUDIOOUT_CTRL_RSRVD2 +#define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8 +#define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x300 +#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) (((v) & 0x3) << 8) +#define BFM_AUDIOOUT_CTRL_SS3D_EFFECT(v) BM_AUDIOOUT_CTRL_SS3D_EFFECT +#define BF_AUDIOOUT_CTRL_SS3D_EFFECT_V(e) BF_AUDIOOUT_CTRL_SS3D_EFFECT(BV_AUDIOOUT_CTRL_SS3D_EFFECT__##e) +#define BFM_AUDIOOUT_CTRL_SS3D_EFFECT_V(v) BM_AUDIOOUT_CTRL_SS3D_EFFECT +#define BP_AUDIOOUT_CTRL_RSRVD1 7 +#define BM_AUDIOOUT_CTRL_RSRVD1 0x80 +#define BF_AUDIOOUT_CTRL_RSRVD1(v) (((v) & 0x1) << 7) +#define BFM_AUDIOOUT_CTRL_RSRVD1(v) BM_AUDIOOUT_CTRL_RSRVD1 +#define BF_AUDIOOUT_CTRL_RSRVD1_V(e) BF_AUDIOOUT_CTRL_RSRVD1(BV_AUDIOOUT_CTRL_RSRVD1__##e) +#define BFM_AUDIOOUT_CTRL_RSRVD1_V(v) BM_AUDIOOUT_CTRL_RSRVD1 +#define BP_AUDIOOUT_CTRL_WORD_LENGTH 6 +#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x40 +#define BF_AUDIOOUT_CTRL_WORD_LENGTH(v) (((v) & 0x1) << 6) +#define BFM_AUDIOOUT_CTRL_WORD_LENGTH(v) BM_AUDIOOUT_CTRL_WORD_LENGTH +#define BF_AUDIOOUT_CTRL_WORD_LENGTH_V(e) BF_AUDIOOUT_CTRL_WORD_LENGTH(BV_AUDIOOUT_CTRL_WORD_LENGTH__##e) +#define BFM_AUDIOOUT_CTRL_WORD_LENGTH_V(v) BM_AUDIOOUT_CTRL_WORD_LENGTH +#define BP_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 5 +#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x20 +#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v) (((v) & 0x1) << 5) +#define BFM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(v) BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE +#define BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE_V(e) BF_AUDIOOUT_CTRL_DAC_ZERO_ENABLE(BV_AUDIOOUT_CTRL_DAC_ZERO_ENABLE__##e) +#define BFM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE_V(v) BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE +#define BP_AUDIOOUT_CTRL_LOOPBACK 4 +#define BM_AUDIOOUT_CTRL_LOOPBACK 0x10 +#define BF_AUDIOOUT_CTRL_LOOPBACK(v) (((v) & 0x1) << 4) +#define BFM_AUDIOOUT_CTRL_LOOPBACK(v) BM_AUDIOOUT_CTRL_LOOPBACK +#define BF_AUDIOOUT_CTRL_LOOPBACK_V(e) BF_AUDIOOUT_CTRL_LOOPBACK(BV_AUDIOOUT_CTRL_LOOPBACK__##e) +#define BFM_AUDIOOUT_CTRL_LOOPBACK_V(v) BM_AUDIOOUT_CTRL_LOOPBACK +#define BP_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 3 +#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x8 +#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v) (((v) & 0x1) << 3) +#define BFM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(v) BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ +#define BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ_V(e) BF_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ(BV_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ__##e) +#define BFM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ_V(v) BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ +#define BP_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 2 +#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x4 +#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v) (((v) & 0x1) << 2) +#define BFM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(v) BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ +#define BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ_V(e) BF_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ(BV_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ__##e) +#define BFM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ_V(v) BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ +#define BP_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 1 +#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x2 +#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v) (((v) & 0x1) << 1) +#define BFM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(v) BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN +#define BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN_V(e) BF_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN(BV_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN__##e) +#define BFM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN_V(v) BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN +#define BP_AUDIOOUT_CTRL_RUN 0 +#define BM_AUDIOOUT_CTRL_RUN 0x1 +#define BF_AUDIOOUT_CTRL_RUN(v) (((v) & 0x1) << 0) +#define BFM_AUDIOOUT_CTRL_RUN(v) BM_AUDIOOUT_CTRL_RUN +#define BF_AUDIOOUT_CTRL_RUN_V(e) BF_AUDIOOUT_CTRL_RUN(BV_AUDIOOUT_CTRL_RUN__##e) +#define BFM_AUDIOOUT_CTRL_RUN_V(v) BM_AUDIOOUT_CTRL_RUN + +#define HW_AUDIOOUT_STAT HW(AUDIOOUT_STAT) +#define HWA_AUDIOOUT_STAT (0x80048000 + 0x10) +#define HWT_AUDIOOUT_STAT HWIO_32_RW +#define HWN_AUDIOOUT_STAT AUDIOOUT_STAT +#define HWI_AUDIOOUT_STAT +#define HW_AUDIOOUT_STAT_SET HW(AUDIOOUT_STAT_SET) +#define HWA_AUDIOOUT_STAT_SET (HWA_AUDIOOUT_STAT + 0x4) +#define HWT_AUDIOOUT_STAT_SET HWIO_32_WO +#define HWN_AUDIOOUT_STAT_SET AUDIOOUT_STAT +#define HWI_AUDIOOUT_STAT_SET +#define HW_AUDIOOUT_STAT_CLR HW(AUDIOOUT_STAT_CLR) +#define HWA_AUDIOOUT_STAT_CLR (HWA_AUDIOOUT_STAT + 0x8) +#define HWT_AUDIOOUT_STAT_CLR HWIO_32_WO +#define HWN_AUDIOOUT_STAT_CLR AUDIOOUT_STAT +#define HWI_AUDIOOUT_STAT_CLR +#define HW_AUDIOOUT_STAT_TOG HW(AUDIOOUT_STAT_TOG) +#define HWA_AUDIOOUT_STAT_TOG (HWA_AUDIOOUT_STAT + 0xc) +#define HWT_AUDIOOUT_STAT_TOG HWIO_32_WO +#define HWN_AUDIOOUT_STAT_TOG AUDIOOUT_STAT +#define HWI_AUDIOOUT_STAT_TOG +#define BP_AUDIOOUT_STAT_DAC_PRESENT 31 +#define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000 +#define BF_AUDIOOUT_STAT_DAC_PRESENT(v) (((v) & 0x1) << 31) +#define BFM_AUDIOOUT_STAT_DAC_PRESENT(v) BM_AUDIOOUT_STAT_DAC_PRESENT +#define BF_AUDIOOUT_STAT_DAC_PRESENT_V(e) BF_AUDIOOUT_STAT_DAC_PRESENT(BV_AUDIOOUT_STAT_DAC_PRESENT__##e) +#define BFM_AUDIOOUT_STAT_DAC_PRESENT_V(v) BM_AUDIOOUT_STAT_DAC_PRESENT +#define BP_AUDIOOUT_STAT_RSRVD1 0 +#define BM_AUDIOOUT_STAT_RSRVD1 0x7fffffff +#define BF_AUDIOOUT_STAT_RSRVD1(v) (((v) & 0x7fffffff) << 0) +#define BFM_AUDIOOUT_STAT_RSRVD1(v) BM_AUDIOOUT_STAT_RSRVD1 +#define BF_AUDIOOUT_STAT_RSRVD1_V(e) BF_AUDIOOUT_STAT_RSRVD1(BV_AUDIOOUT_STAT_RSRVD1__##e) +#define BFM_AUDIOOUT_STAT_RSRVD1_V(v) BM_AUDIOOUT_STAT_RSRVD1 + +#define HW_AUDIOOUT_DACSRR HW(AUDIOOUT_DACSRR) +#define HWA_AUDIOOUT_DACSRR (0x80048000 + 0x20) +#define HWT_AUDIOOUT_DACSRR HWIO_32_RW +#define HWN_AUDIOOUT_DACSRR AUDIOOUT_DACSRR +#define HWI_AUDIOOUT_DACSRR +#define HW_AUDIOOUT_DACSRR_SET HW(AUDIOOUT_DACSRR_SET) +#define HWA_AUDIOOUT_DACSRR_SET (HWA_AUDIOOUT_DACSRR + 0x4) +#define HWT_AUDIOOUT_DACSRR_SET HWIO_32_WO +#define HWN_AUDIOOUT_DACSRR_SET AUDIOOUT_DACSRR +#define HWI_AUDIOOUT_DACSRR_SET +#define HW_AUDIOOUT_DACSRR_CLR HW(AUDIOOUT_DACSRR_CLR) +#define HWA_AUDIOOUT_DACSRR_CLR (HWA_AUDIOOUT_DACSRR + 0x8) +#define HWT_AUDIOOUT_DACSRR_CLR HWIO_32_WO +#define HWN_AUDIOOUT_DACSRR_CLR AUDIOOUT_DACSRR +#define HWI_AUDIOOUT_DACSRR_CLR +#define HW_AUDIOOUT_DACSRR_TOG HW(AUDIOOUT_DACSRR_TOG) +#define HWA_AUDIOOUT_DACSRR_TOG (HWA_AUDIOOUT_DACSRR + 0xc) +#define HWT_AUDIOOUT_DACSRR_TOG HWIO_32_WO +#define HWN_AUDIOOUT_DACSRR_TOG AUDIOOUT_DACSRR +#define HWI_AUDIOOUT_DACSRR_TOG +#define BP_AUDIOOUT_DACSRR_OSR 31 +#define BM_AUDIOOUT_DACSRR_OSR 0x80000000 +#define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0 +#define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1 +#define BF_AUDIOOUT_DACSRR_OSR(v) (((v) & 0x1) << 31) +#define BFM_AUDIOOUT_DACSRR_OSR(v) BM_AUDIOOUT_DACSRR_OSR +#define BF_AUDIOOUT_DACSRR_OSR_V(e) BF_AUDIOOUT_DACSRR_OSR(BV_AUDIOOUT_DACSRR_OSR__##e) +#define BFM_AUDIOOUT_DACSRR_OSR_V(v) BM_AUDIOOUT_DACSRR_OSR +#define BP_AUDIOOUT_DACSRR_BASEMULT 28 +#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 +#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1 +#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2 +#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4 +#define BF_AUDIOOUT_DACSRR_BASEMULT(v) (((v) & 0x7) << 28) +#define BFM_AUDIOOUT_DACSRR_BASEMULT(v) BM_AUDIOOUT_DACSRR_BASEMULT +#define BF_AUDIOOUT_DACSRR_BASEMULT_V(e) BF_AUDIOOUT_DACSRR_BASEMULT(BV_AUDIOOUT_DACSRR_BASEMULT__##e) +#define BFM_AUDIOOUT_DACSRR_BASEMULT_V(v) BM_AUDIOOUT_DACSRR_BASEMULT +#define BP_AUDIOOUT_DACSRR_RSRVD2 27 +#define BM_AUDIOOUT_DACSRR_RSRVD2 0x8000000 +#define BF_AUDIOOUT_DACSRR_RSRVD2(v) (((v) & 0x1) << 27) +#define BFM_AUDIOOUT_DACSRR_RSRVD2(v) BM_AUDIOOUT_DACSRR_RSRVD2 +#define BF_AUDIOOUT_DACSRR_RSRVD2_V(e) BF_AUDIOOUT_DACSRR_RSRVD2(BV_AUDIOOUT_DACSRR_RSRVD2__##e) +#define BFM_AUDIOOUT_DACSRR_RSRVD2_V(v) BM_AUDIOOUT_DACSRR_RSRVD2 +#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 +#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x7000000 +#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) (((v) & 0x7) << 24) +#define BFM_AUDIOOUT_DACSRR_SRC_HOLD(v) BM_AUDIOOUT_DACSRR_SRC_HOLD +#define BF_AUDIOOUT_DACSRR_SRC_HOLD_V(e) BF_AUDIOOUT_DACSRR_SRC_HOLD(BV_AUDIOOUT_DACSRR_SRC_HOLD__##e) +#define BFM_AUDIOOUT_DACSRR_SRC_HOLD_V(v) BM_AUDIOOUT_DACSRR_SRC_HOLD +#define BP_AUDIOOUT_DACSRR_RSRVD1 21 +#define BM_AUDIOOUT_DACSRR_RSRVD1 0xe00000 +#define BF_AUDIOOUT_DACSRR_RSRVD1(v) (((v) & 0x7) << 21) +#define BFM_AUDIOOUT_DACSRR_RSRVD1(v) BM_AUDIOOUT_DACSRR_RSRVD1 +#define BF_AUDIOOUT_DACSRR_RSRVD1_V(e) BF_AUDIOOUT_DACSRR_RSRVD1(BV_AUDIOOUT_DACSRR_RSRVD1__##e) +#define BFM_AUDIOOUT_DACSRR_RSRVD1_V(v) BM_AUDIOOUT_DACSRR_RSRVD1 +#define BP_AUDIOOUT_DACSRR_SRC_INT 16 +#define BM_AUDIOOUT_DACSRR_SRC_INT 0x1f0000 +#define BF_AUDIOOUT_DACSRR_SRC_INT(v) (((v) & 0x1f) << 16) +#define BFM_AUDIOOUT_DACSRR_SRC_INT(v) BM_AUDIOOUT_DACSRR_SRC_INT +#define BF_AUDIOOUT_DACSRR_SRC_INT_V(e) BF_AUDIOOUT_DACSRR_SRC_INT(BV_AUDIOOUT_DACSRR_SRC_INT__##e) +#define BFM_AUDIOOUT_DACSRR_SRC_INT_V(v) BM_AUDIOOUT_DACSRR_SRC_INT +#define BP_AUDIOOUT_DACSRR_RSRVD0 13 +#define BM_AUDIOOUT_DACSRR_RSRVD0 0xe000 +#define BF_AUDIOOUT_DACSRR_RSRVD0(v) (((v) & 0x7) << 13) +#define BFM_AUDIOOUT_DACSRR_RSRVD0(v) BM_AUDIOOUT_DACSRR_RSRVD0 +#define BF_AUDIOOUT_DACSRR_RSRVD0_V(e) BF_AUDIOOUT_DACSRR_RSRVD0(BV_AUDIOOUT_DACSRR_RSRVD0__##e) +#define BFM_AUDIOOUT_DACSRR_RSRVD0_V(v) BM_AUDIOOUT_DACSRR_RSRVD0 +#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 +#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x1fff +#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) (((v) & 0x1fff) << 0) +#define BFM_AUDIOOUT_DACSRR_SRC_FRAC(v) BM_AUDIOOUT_DACSRR_SRC_FRAC +#define BF_AUDIOOUT_DACSRR_SRC_FRAC_V(e) BF_AUDIOOUT_DACSRR_SRC_FRAC(BV_AUDIOOUT_DACSRR_SRC_FRAC__##e) +#define BFM_AUDIOOUT_DACSRR_SRC_FRAC_V(v) BM_AUDIOOUT_DACSRR_SRC_FRAC + +#define HW_AUDIOOUT_DACVOLUME HW(AUDIOOUT_DACVOLUME) +#define HWA_AUDIOOUT_DACVOLUME (0x80048000 + 0x30) +#define HWT_AUDIOOUT_DACVOLUME HWIO_32_RW +#define HWN_AUDIOOUT_DACVOLUME AUDIOOUT_DACVOLUME +#define HWI_AUDIOOUT_DACVOLUME +#define HW_AUDIOOUT_DACVOLUME_SET HW(AUDIOOUT_DACVOLUME_SET) +#define HWA_AUDIOOUT_DACVOLUME_SET (HWA_AUDIOOUT_DACVOLUME + 0x4) +#define HWT_AUDIOOUT_DACVOLUME_SET HWIO_32_WO +#define HWN_AUDIOOUT_DACVOLUME_SET AUDIOOUT_DACVOLUME +#define HWI_AUDIOOUT_DACVOLUME_SET +#define HW_AUDIOOUT_DACVOLUME_CLR HW(AUDIOOUT_DACVOLUME_CLR) +#define HWA_AUDIOOUT_DACVOLUME_CLR (HWA_AUDIOOUT_DACVOLUME + 0x8) +#define HWT_AUDIOOUT_DACVOLUME_CLR HWIO_32_WO +#define HWN_AUDIOOUT_DACVOLUME_CLR AUDIOOUT_DACVOLUME +#define HWI_AUDIOOUT_DACVOLUME_CLR +#define HW_AUDIOOUT_DACVOLUME_TOG HW(AUDIOOUT_DACVOLUME_TOG) +#define HWA_AUDIOOUT_DACVOLUME_TOG (HWA_AUDIOOUT_DACVOLUME + 0xc) +#define HWT_AUDIOOUT_DACVOLUME_TOG HWIO_32_WO +#define HWN_AUDIOOUT_DACVOLUME_TOG AUDIOOUT_DACVOLUME +#define HWI_AUDIOOUT_DACVOLUME_TOG +#define BP_AUDIOOUT_DACVOLUME_RSRVD4 29 +#define BM_AUDIOOUT_DACVOLUME_RSRVD4 0xe0000000 +#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v) (((v) & 0x7) << 29) +#define BFM_AUDIOOUT_DACVOLUME_RSRVD4(v) BM_AUDIOOUT_DACVOLUME_RSRVD4 +#define BF_AUDIOOUT_DACVOLUME_RSRVD4_V(e) BF_AUDIOOUT_DACVOLUME_RSRVD4(BV_AUDIOOUT_DACVOLUME_RSRVD4__##e) +#define BFM_AUDIOOUT_DACVOLUME_RSRVD4_V(v) BM_AUDIOOUT_DACVOLUME_RSRVD4 +#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 28 +#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000 +#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v) (((v) & 0x1) << 28) +#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(v) BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT +#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT_V(e) BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT(BV_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT__##e) +#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT_V(v) BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT +#define BP_AUDIOOUT_DACVOLUME_RSRVD3 26 +#define BM_AUDIOOUT_DACVOLUME_RSRVD3 0xc000000 +#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v) (((v) & 0x3) << 26) +#define BFM_AUDIOOUT_DACVOLUME_RSRVD3(v) BM_AUDIOOUT_DACVOLUME_RSRVD3 +#define BF_AUDIOOUT_DACVOLUME_RSRVD3_V(e) BF_AUDIOOUT_DACVOLUME_RSRVD3(BV_AUDIOOUT_DACVOLUME_RSRVD3__##e) +#define BFM_AUDIOOUT_DACVOLUME_RSRVD3_V(v) BM_AUDIOOUT_DACVOLUME_RSRVD3 +#define BP_AUDIOOUT_DACVOLUME_EN_ZCD 25 +#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x2000000 +#define BF_AUDIOOUT_DACVOLUME_EN_ZCD(v) (((v) & 0x1) << 25) +#define BFM_AUDIOOUT_DACVOLUME_EN_ZCD(v) BM_AUDIOOUT_DACVOLUME_EN_ZCD +#define BF_AUDIOOUT_DACVOLUME_EN_ZCD_V(e) BF_AUDIOOUT_DACVOLUME_EN_ZCD(BV_AUDIOOUT_DACVOLUME_EN_ZCD__##e) +#define BFM_AUDIOOUT_DACVOLUME_EN_ZCD_V(v) BM_AUDIOOUT_DACVOLUME_EN_ZCD +#define BP_AUDIOOUT_DACVOLUME_MUTE_LEFT 24 +#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x1000000 +#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(v) (((v) & 0x1) << 24) +#define BFM_AUDIOOUT_DACVOLUME_MUTE_LEFT(v) BM_AUDIOOUT_DACVOLUME_MUTE_LEFT +#define BF_AUDIOOUT_DACVOLUME_MUTE_LEFT_V(e) BF_AUDIOOUT_DACVOLUME_MUTE_LEFT(BV_AUDIOOUT_DACVOLUME_MUTE_LEFT__##e) +#define BFM_AUDIOOUT_DACVOLUME_MUTE_LEFT_V(v) BM_AUDIOOUT_DACVOLUME_MUTE_LEFT +#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16 +#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0xff0000 +#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) (((v) & 0xff) << 16) +#define BFM_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT +#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT_V(e) BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(BV_AUDIOOUT_DACVOLUME_VOLUME_LEFT__##e) +#define BFM_AUDIOOUT_DACVOLUME_VOLUME_LEFT_V(v) BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT +#define BP_AUDIOOUT_DACVOLUME_RSRVD2 13 +#define BM_AUDIOOUT_DACVOLUME_RSRVD2 0xe000 +#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v) (((v) & 0x7) << 13) +#define BFM_AUDIOOUT_DACVOLUME_RSRVD2(v) BM_AUDIOOUT_DACVOLUME_RSRVD2 +#define BF_AUDIOOUT_DACVOLUME_RSRVD2_V(e) BF_AUDIOOUT_DACVOLUME_RSRVD2(BV_AUDIOOUT_DACVOLUME_RSRVD2__##e) +#define BFM_AUDIOOUT_DACVOLUME_RSRVD2_V(v) BM_AUDIOOUT_DACVOLUME_RSRVD2 +#define BP_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 12 +#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x1000 +#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v) (((v) & 0x1) << 12) +#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(v) BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT +#define BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT_V(e) BF_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT(BV_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT__##e) +#define BFM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT_V(v) BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT +#define BP_AUDIOOUT_DACVOLUME_RSRVD1 9 +#define BM_AUDIOOUT_DACVOLUME_RSRVD1 0xe00 +#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v) (((v) & 0x7) << 9) +#define BFM_AUDIOOUT_DACVOLUME_RSRVD1(v) BM_AUDIOOUT_DACVOLUME_RSRVD1 +#define BF_AUDIOOUT_DACVOLUME_RSRVD1_V(e) BF_AUDIOOUT_DACVOLUME_RSRVD1(BV_AUDIOOUT_DACVOLUME_RSRVD1__##e) +#define BFM_AUDIOOUT_DACVOLUME_RSRVD1_V(v) BM_AUDIOOUT_DACVOLUME_RSRVD1 +#define BP_AUDIOOUT_DACVOLUME_MUTE_RIGHT 8 +#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x100 +#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v) (((v) & 0x1) << 8) +#define BFM_AUDIOOUT_DACVOLUME_MUTE_RIGHT(v) BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT +#define BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT_V(e) BF_AUDIOOUT_DACVOLUME_MUTE_RIGHT(BV_AUDIOOUT_DACVOLUME_MUTE_RIGHT__##e) +#define BFM_AUDIOOUT_DACVOLUME_MUTE_RIGHT_V(v) BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT +#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0 +#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0xff +#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) (((v) & 0xff) << 0) +#define BFM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT +#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT_V(e) BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(BV_AUDIOOUT_DACVOLUME_VOLUME_RIGHT__##e) +#define BFM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT_V(v) BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT + +#define HW_AUDIOOUT_DACDEBUG HW(AUDIOOUT_DACDEBUG) +#define HWA_AUDIOOUT_DACDEBUG (0x80048000 + 0x40) +#define HWT_AUDIOOUT_DACDEBUG HWIO_32_RW +#define HWN_AUDIOOUT_DACDEBUG AUDIOOUT_DACDEBUG +#define HWI_AUDIOOUT_DACDEBUG +#define HW_AUDIOOUT_DACDEBUG_SET HW(AUDIOOUT_DACDEBUG_SET) +#define HWA_AUDIOOUT_DACDEBUG_SET (HWA_AUDIOOUT_DACDEBUG + 0x4) +#define HWT_AUDIOOUT_DACDEBUG_SET HWIO_32_WO +#define HWN_AUDIOOUT_DACDEBUG_SET AUDIOOUT_DACDEBUG +#define HWI_AUDIOOUT_DACDEBUG_SET +#define HW_AUDIOOUT_DACDEBUG_CLR HW(AUDIOOUT_DACDEBUG_CLR) +#define HWA_AUDIOOUT_DACDEBUG_CLR (HWA_AUDIOOUT_DACDEBUG + 0x8) +#define HWT_AUDIOOUT_DACDEBUG_CLR HWIO_32_WO +#define HWN_AUDIOOUT_DACDEBUG_CLR AUDIOOUT_DACDEBUG +#define HWI_AUDIOOUT_DACDEBUG_CLR +#define HW_AUDIOOUT_DACDEBUG_TOG HW(AUDIOOUT_DACDEBUG_TOG) +#define HWA_AUDIOOUT_DACDEBUG_TOG (HWA_AUDIOOUT_DACDEBUG + 0xc) +#define HWT_AUDIOOUT_DACDEBUG_TOG HWIO_32_WO +#define HWN_AUDIOOUT_DACDEBUG_TOG AUDIOOUT_DACDEBUG +#define HWI_AUDIOOUT_DACDEBUG_TOG +#define BP_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 31 +#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000 +#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v) (((v) & 0x1) << 31) +#define BFM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(v) BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA +#define BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA_V(e) BF_AUDIOOUT_DACDEBUG_ENABLE_DACDMA(BV_AUDIOOUT_DACDEBUG_ENABLE_DACDMA__##e) +#define BFM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA_V(v) BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA +#define BP_AUDIOOUT_DACDEBUG_RSRVD2 12 +#define BM_AUDIOOUT_DACDEBUG_RSRVD2 0x7ffff000 +#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v) (((v) & 0x7ffff) << 12) +#define BFM_AUDIOOUT_DACDEBUG_RSRVD2(v) BM_AUDIOOUT_DACDEBUG_RSRVD2 +#define BF_AUDIOOUT_DACDEBUG_RSRVD2_V(e) BF_AUDIOOUT_DACDEBUG_RSRVD2(BV_AUDIOOUT_DACDEBUG_RSRVD2__##e) +#define BFM_AUDIOOUT_DACDEBUG_RSRVD2_V(v) BM_AUDIOOUT_DACDEBUG_RSRVD2 +#define BP_AUDIOOUT_DACDEBUG_RAM_SS 8 +#define BM_AUDIOOUT_DACDEBUG_RAM_SS 0xf00 +#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) (((v) & 0xf) << 8) +#define BFM_AUDIOOUT_DACDEBUG_RAM_SS(v) BM_AUDIOOUT_DACDEBUG_RAM_SS +#define BF_AUDIOOUT_DACDEBUG_RAM_SS_V(e) BF_AUDIOOUT_DACDEBUG_RAM_SS(BV_AUDIOOUT_DACDEBUG_RAM_SS__##e) +#define BFM_AUDIOOUT_DACDEBUG_RAM_SS_V(v) BM_AUDIOOUT_DACDEBUG_RAM_SS +#define BP_AUDIOOUT_DACDEBUG_RSRVD1 6 +#define BM_AUDIOOUT_DACDEBUG_RSRVD1 0xc0 +#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v) (((v) & 0x3) << 6) +#define BFM_AUDIOOUT_DACDEBUG_RSRVD1(v) BM_AUDIOOUT_DACDEBUG_RSRVD1 +#define BF_AUDIOOUT_DACDEBUG_RSRVD1_V(e) BF_AUDIOOUT_DACDEBUG_RSRVD1(BV_AUDIOOUT_DACDEBUG_RSRVD1__##e) +#define BFM_AUDIOOUT_DACDEBUG_RSRVD1_V(v) BM_AUDIOOUT_DACDEBUG_RSRVD1 +#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 5 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x20 +#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v) (((v) & 0x1) << 5) +#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(v) BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS +#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS_V(e) BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS__##e) +#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS_V(v) BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS +#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 4 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x10 +#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v) (((v) & 0x1) << 4) +#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(v) BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS +#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS_V(e) BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS__##e) +#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS_V(v) BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS +#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 3 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x8 +#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v) (((v) & 0x1) << 3) +#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(v) BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE +#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE_V(e) BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE__##e) +#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE_V(v) BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE +#define BP_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 2 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x4 +#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v) (((v) & 0x1) << 2) +#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(v) BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE +#define BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE_V(e) BF_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE(BV_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE__##e) +#define BFM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE_V(v) BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE +#define BP_AUDIOOUT_DACDEBUG_DMA_PREQ 1 +#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x2 +#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ(v) (((v) & 0x1) << 1) +#define BFM_AUDIOOUT_DACDEBUG_DMA_PREQ(v) BM_AUDIOOUT_DACDEBUG_DMA_PREQ +#define BF_AUDIOOUT_DACDEBUG_DMA_PREQ_V(e) BF_AUDIOOUT_DACDEBUG_DMA_PREQ(BV_AUDIOOUT_DACDEBUG_DMA_PREQ__##e) +#define BFM_AUDIOOUT_DACDEBUG_DMA_PREQ_V(v) BM_AUDIOOUT_DACDEBUG_DMA_PREQ +#define BP_AUDIOOUT_DACDEBUG_FIFO_STATUS 0 +#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x1 +#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(v) (((v) & 0x1) << 0) +#define BFM_AUDIOOUT_DACDEBUG_FIFO_STATUS(v) BM_AUDIOOUT_DACDEBUG_FIFO_STATUS +#define BF_AUDIOOUT_DACDEBUG_FIFO_STATUS_V(e) BF_AUDIOOUT_DACDEBUG_FIFO_STATUS(BV_AUDIOOUT_DACDEBUG_FIFO_STATUS__##e) +#define BFM_AUDIOOUT_DACDEBUG_FIFO_STATUS_V(v) BM_AUDIOOUT_DACDEBUG_FIFO_STATUS + +#define HW_AUDIOOUT_HPVOL HW(AUDIOOUT_HPVOL) +#define HWA_AUDIOOUT_HPVOL (0x80048000 + 0x50) +#define HWT_AUDIOOUT_HPVOL HWIO_32_RW +#define HWN_AUDIOOUT_HPVOL AUDIOOUT_HPVOL +#define HWI_AUDIOOUT_HPVOL +#define HW_AUDIOOUT_HPVOL_SET HW(AUDIOOUT_HPVOL_SET) +#define HWA_AUDIOOUT_HPVOL_SET (HWA_AUDIOOUT_HPVOL + 0x4) +#define HWT_AUDIOOUT_HPVOL_SET HWIO_32_WO +#define HWN_AUDIOOUT_HPVOL_SET AUDIOOUT_HPVOL +#define HWI_AUDIOOUT_HPVOL_SET +#define HW_AUDIOOUT_HPVOL_CLR HW(AUDIOOUT_HPVOL_CLR) +#define HWA_AUDIOOUT_HPVOL_CLR (HWA_AUDIOOUT_HPVOL + 0x8) +#define HWT_AUDIOOUT_HPVOL_CLR HWIO_32_WO +#define HWN_AUDIOOUT_HPVOL_CLR AUDIOOUT_HPVOL +#define HWI_AUDIOOUT_HPVOL_CLR +#define HW_AUDIOOUT_HPVOL_TOG HW(AUDIOOUT_HPVOL_TOG) +#define HWA_AUDIOOUT_HPVOL_TOG (HWA_AUDIOOUT_HPVOL + 0xc) +#define HWT_AUDIOOUT_HPVOL_TOG HWIO_32_WO +#define HWN_AUDIOOUT_HPVOL_TOG AUDIOOUT_HPVOL +#define HWI_AUDIOOUT_HPVOL_TOG +#define BP_AUDIOOUT_HPVOL_RSRVD5 29 +#define BM_AUDIOOUT_HPVOL_RSRVD5 0xe0000000 +#define BF_AUDIOOUT_HPVOL_RSRVD5(v) (((v) & 0x7) << 29) +#define BFM_AUDIOOUT_HPVOL_RSRVD5(v) BM_AUDIOOUT_HPVOL_RSRVD5 +#define BF_AUDIOOUT_HPVOL_RSRVD5_V(e) BF_AUDIOOUT_HPVOL_RSRVD5(BV_AUDIOOUT_HPVOL_RSRVD5__##e) +#define BFM_AUDIOOUT_HPVOL_RSRVD5_V(v) BM_AUDIOOUT_HPVOL_RSRVD5 +#define BP_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 28 +#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000 +#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v) (((v) & 0x1) << 28) +#define BFM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(v) BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING +#define BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING_V(e) BF_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING(BV_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING__##e) +#define BFM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING_V(v) BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING +#define BP_AUDIOOUT_HPVOL_RSRVD4 26 +#define BM_AUDIOOUT_HPVOL_RSRVD4 0xc000000 +#define BF_AUDIOOUT_HPVOL_RSRVD4(v) (((v) & 0x3) << 26) +#define BFM_AUDIOOUT_HPVOL_RSRVD4(v) BM_AUDIOOUT_HPVOL_RSRVD4 +#define BF_AUDIOOUT_HPVOL_RSRVD4_V(e) BF_AUDIOOUT_HPVOL_RSRVD4(BV_AUDIOOUT_HPVOL_RSRVD4__##e) +#define BFM_AUDIOOUT_HPVOL_RSRVD4_V(v) BM_AUDIOOUT_HPVOL_RSRVD4 +#define BP_AUDIOOUT_HPVOL_EN_MSTR_ZCD 25 +#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x2000000 +#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v) (((v) & 0x1) << 25) +#define BFM_AUDIOOUT_HPVOL_EN_MSTR_ZCD(v) BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD +#define BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD_V(e) BF_AUDIOOUT_HPVOL_EN_MSTR_ZCD(BV_AUDIOOUT_HPVOL_EN_MSTR_ZCD__##e) +#define BFM_AUDIOOUT_HPVOL_EN_MSTR_ZCD_V(v) BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD +#define BP_AUDIOOUT_HPVOL_MUTE 24 +#define BM_AUDIOOUT_HPVOL_MUTE 0x1000000 +#define BF_AUDIOOUT_HPVOL_MUTE(v) (((v) & 0x1) << 24) +#define BFM_AUDIOOUT_HPVOL_MUTE(v) BM_AUDIOOUT_HPVOL_MUTE +#define BF_AUDIOOUT_HPVOL_MUTE_V(e) BF_AUDIOOUT_HPVOL_MUTE(BV_AUDIOOUT_HPVOL_MUTE__##e) +#define BFM_AUDIOOUT_HPVOL_MUTE_V(v) BM_AUDIOOUT_HPVOL_MUTE +#define BP_AUDIOOUT_HPVOL_RSRVD3 17 +#define BM_AUDIOOUT_HPVOL_RSRVD3 0xfe0000 +#define BF_AUDIOOUT_HPVOL_RSRVD3(v) (((v) & 0x7f) << 17) +#define BFM_AUDIOOUT_HPVOL_RSRVD3(v) BM_AUDIOOUT_HPVOL_RSRVD3 +#define BF_AUDIOOUT_HPVOL_RSRVD3_V(e) BF_AUDIOOUT_HPVOL_RSRVD3(BV_AUDIOOUT_HPVOL_RSRVD3__##e) +#define BFM_AUDIOOUT_HPVOL_RSRVD3_V(v) BM_AUDIOOUT_HPVOL_RSRVD3 +#define BP_AUDIOOUT_HPVOL_SELECT 16 +#define BM_AUDIOOUT_HPVOL_SELECT 0x10000 +#define BF_AUDIOOUT_HPVOL_SELECT(v) (((v) & 0x1) << 16) +#define BFM_AUDIOOUT_HPVOL_SELECT(v) BM_AUDIOOUT_HPVOL_SELECT +#define BF_AUDIOOUT_HPVOL_SELECT_V(e) BF_AUDIOOUT_HPVOL_SELECT(BV_AUDIOOUT_HPVOL_SELECT__##e) +#define BFM_AUDIOOUT_HPVOL_SELECT_V(v) BM_AUDIOOUT_HPVOL_SELECT +#define BP_AUDIOOUT_HPVOL_RSRVD2 15 +#define BM_AUDIOOUT_HPVOL_RSRVD2 0x8000 +#define BF_AUDIOOUT_HPVOL_RSRVD2(v) (((v) & 0x1) << 15) +#define BFM_AUDIOOUT_HPVOL_RSRVD2(v) BM_AUDIOOUT_HPVOL_RSRVD2 +#define BF_AUDIOOUT_HPVOL_RSRVD2_V(e) BF_AUDIOOUT_HPVOL_RSRVD2(BV_AUDIOOUT_HPVOL_RSRVD2__##e) +#define BFM_AUDIOOUT_HPVOL_RSRVD2_V(v) BM_AUDIOOUT_HPVOL_RSRVD2 +#define BP_AUDIOOUT_HPVOL_VOL_LEFT 8 +#define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x7f00 +#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) (((v) & 0x7f) << 8) +#define BFM_AUDIOOUT_HPVOL_VOL_LEFT(v) BM_AUDIOOUT_HPVOL_VOL_LEFT +#define BF_AUDIOOUT_HPVOL_VOL_LEFT_V(e) BF_AUDIOOUT_HPVOL_VOL_LEFT(BV_AUDIOOUT_HPVOL_VOL_LEFT__##e) +#define BFM_AUDIOOUT_HPVOL_VOL_LEFT_V(v) BM_AUDIOOUT_HPVOL_VOL_LEFT +#define BP_AUDIOOUT_HPVOL_RSRVD1 7 +#define BM_AUDIOOUT_HPVOL_RSRVD1 0x80 +#define BF_AUDIOOUT_HPVOL_RSRVD1(v) (((v) & 0x1) << 7) +#define BFM_AUDIOOUT_HPVOL_RSRVD1(v) BM_AUDIOOUT_HPVOL_RSRVD1 +#define BF_AUDIOOUT_HPVOL_RSRVD1_V(e) BF_AUDIOOUT_HPVOL_RSRVD1(BV_AUDIOOUT_HPVOL_RSRVD1__##e) +#define BFM_AUDIOOUT_HPVOL_RSRVD1_V(v) BM_AUDIOOUT_HPVOL_RSRVD1 +#define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0 +#define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x7f +#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) (((v) & 0x7f) << 0) +#define BFM_AUDIOOUT_HPVOL_VOL_RIGHT(v) BM_AUDIOOUT_HPVOL_VOL_RIGHT +#define BF_AUDIOOUT_HPVOL_VOL_RIGHT_V(e) BF_AUDIOOUT_HPVOL_VOL_RIGHT(BV_AUDIOOUT_HPVOL_VOL_RIGHT__##e) +#define BFM_AUDIOOUT_HPVOL_VOL_RIGHT_V(v) BM_AUDIOOUT_HPVOL_VOL_RIGHT + +#define HW_AUDIOOUT_RESERVED HW(AUDIOOUT_RESERVED) +#define HWA_AUDIOOUT_RESERVED (0x80048000 + 0x60) +#define HWT_AUDIOOUT_RESERVED HWIO_32_RW +#define HWN_AUDIOOUT_RESERVED AUDIOOUT_RESERVED +#define HWI_AUDIOOUT_RESERVED +#define HW_AUDIOOUT_RESERVED_SET HW(AUDIOOUT_RESERVED_SET) +#define HWA_AUDIOOUT_RESERVED_SET (HWA_AUDIOOUT_RESERVED + 0x4) +#define HWT_AUDIOOUT_RESERVED_SET HWIO_32_WO +#define HWN_AUDIOOUT_RESERVED_SET AUDIOOUT_RESERVED +#define HWI_AUDIOOUT_RESERVED_SET +#define HW_AUDIOOUT_RESERVED_CLR HW(AUDIOOUT_RESERVED_CLR) +#define HWA_AUDIOOUT_RESERVED_CLR (HWA_AUDIOOUT_RESERVED + 0x8) +#define HWT_AUDIOOUT_RESERVED_CLR HWIO_32_WO +#define HWN_AUDIOOUT_RESERVED_CLR AUDIOOUT_RESERVED +#define HWI_AUDIOOUT_RESERVED_CLR +#define HW_AUDIOOUT_RESERVED_TOG HW(AUDIOOUT_RESERVED_TOG) +#define HWA_AUDIOOUT_RESERVED_TOG (HWA_AUDIOOUT_RESERVED + 0xc) +#define HWT_AUDIOOUT_RESERVED_TOG HWIO_32_WO +#define HWN_AUDIOOUT_RESERVED_TOG AUDIOOUT_RESERVED +#define HWI_AUDIOOUT_RESERVED_TOG +#define BP_AUDIOOUT_RESERVED_RSRVD1 0 +#define BM_AUDIOOUT_RESERVED_RSRVD1 0xffffffff +#define BF_AUDIOOUT_RESERVED_RSRVD1(v) (((v) & 0xffffffff) << 0) +#define BFM_AUDIOOUT_RESERVED_RSRVD1(v) BM_AUDIOOUT_RESERVED_RSRVD1 +#define BF_AUDIOOUT_RESERVED_RSRVD1_V(e) BF_AUDIOOUT_RESERVED_RSRVD1(BV_AUDIOOUT_RESERVED_RSRVD1__##e) +#define BFM_AUDIOOUT_RESERVED_RSRVD1_V(v) BM_AUDIOOUT_RESERVED_RSRVD1 + +#define HW_AUDIOOUT_PWRDN HW(AUDIOOUT_PWRDN) +#define HWA_AUDIOOUT_PWRDN (0x80048000 + 0x70) +#define HWT_AUDIOOUT_PWRDN HWIO_32_RW +#define HWN_AUDIOOUT_PWRDN AUDIOOUT_PWRDN +#define HWI_AUDIOOUT_PWRDN +#define HW_AUDIOOUT_PWRDN_SET HW(AUDIOOUT_PWRDN_SET) +#define HWA_AUDIOOUT_PWRDN_SET (HWA_AUDIOOUT_PWRDN + 0x4) +#define HWT_AUDIOOUT_PWRDN_SET HWIO_32_WO +#define HWN_AUDIOOUT_PWRDN_SET AUDIOOUT_PWRDN +#define HWI_AUDIOOUT_PWRDN_SET +#define HW_AUDIOOUT_PWRDN_CLR HW(AUDIOOUT_PWRDN_CLR) +#define HWA_AUDIOOUT_PWRDN_CLR (HWA_AUDIOOUT_PWRDN + 0x8) +#define HWT_AUDIOOUT_PWRDN_CLR HWIO_32_WO +#define HWN_AUDIOOUT_PWRDN_CLR AUDIOOUT_PWRDN +#define HWI_AUDIOOUT_PWRDN_CLR +#define HW_AUDIOOUT_PWRDN_TOG HW(AUDIOOUT_PWRDN_TOG) +#define HWA_AUDIOOUT_PWRDN_TOG (HWA_AUDIOOUT_PWRDN + 0xc) +#define HWT_AUDIOOUT_PWRDN_TOG HWIO_32_WO +#define HWN_AUDIOOUT_PWRDN_TOG AUDIOOUT_PWRDN +#define HWI_AUDIOOUT_PWRDN_TOG +#define BP_AUDIOOUT_PWRDN_RSRVD7 25 +#define BM_AUDIOOUT_PWRDN_RSRVD7 0xfe000000 +#define BF_AUDIOOUT_PWRDN_RSRVD7(v) (((v) & 0x7f) << 25) +#define BFM_AUDIOOUT_PWRDN_RSRVD7(v) BM_AUDIOOUT_PWRDN_RSRVD7 +#define BF_AUDIOOUT_PWRDN_RSRVD7_V(e) BF_AUDIOOUT_PWRDN_RSRVD7(BV_AUDIOOUT_PWRDN_RSRVD7__##e) +#define BFM_AUDIOOUT_PWRDN_RSRVD7_V(v) BM_AUDIOOUT_PWRDN_RSRVD7 +#define BP_AUDIOOUT_PWRDN_SPEAKER 24 +#define BM_AUDIOOUT_PWRDN_SPEAKER 0x1000000 +#define BF_AUDIOOUT_PWRDN_SPEAKER(v) (((v) & 0x1) << 24) +#define BFM_AUDIOOUT_PWRDN_SPEAKER(v) BM_AUDIOOUT_PWRDN_SPEAKER +#define BF_AUDIOOUT_PWRDN_SPEAKER_V(e) BF_AUDIOOUT_PWRDN_SPEAKER(BV_AUDIOOUT_PWRDN_SPEAKER__##e) +#define BFM_AUDIOOUT_PWRDN_SPEAKER_V(v) BM_AUDIOOUT_PWRDN_SPEAKER +#define BP_AUDIOOUT_PWRDN_RSRVD6 21 +#define BM_AUDIOOUT_PWRDN_RSRVD6 0xe00000 +#define BF_AUDIOOUT_PWRDN_RSRVD6(v) (((v) & 0x7) << 21) +#define BFM_AUDIOOUT_PWRDN_RSRVD6(v) BM_AUDIOOUT_PWRDN_RSRVD6 +#define BF_AUDIOOUT_PWRDN_RSRVD6_V(e) BF_AUDIOOUT_PWRDN_RSRVD6(BV_AUDIOOUT_PWRDN_RSRVD6__##e) +#define BFM_AUDIOOUT_PWRDN_RSRVD6_V(v) BM_AUDIOOUT_PWRDN_RSRVD6 +#define BP_AUDIOOUT_PWRDN_SELFBIAS 20 +#define BM_AUDIOOUT_PWRDN_SELFBIAS 0x100000 +#define BF_AUDIOOUT_PWRDN_SELFBIAS(v) (((v) & 0x1) << 20) +#define BFM_AUDIOOUT_PWRDN_SELFBIAS(v) BM_AUDIOOUT_PWRDN_SELFBIAS +#define BF_AUDIOOUT_PWRDN_SELFBIAS_V(e) BF_AUDIOOUT_PWRDN_SELFBIAS(BV_AUDIOOUT_PWRDN_SELFBIAS__##e) +#define BFM_AUDIOOUT_PWRDN_SELFBIAS_V(v) BM_AUDIOOUT_PWRDN_SELFBIAS +#define BP_AUDIOOUT_PWRDN_RSRVD5 17 +#define BM_AUDIOOUT_PWRDN_RSRVD5 0xe0000 +#define BF_AUDIOOUT_PWRDN_RSRVD5(v) (((v) & 0x7) << 17) +#define BFM_AUDIOOUT_PWRDN_RSRVD5(v) BM_AUDIOOUT_PWRDN_RSRVD5 +#define BF_AUDIOOUT_PWRDN_RSRVD5_V(e) BF_AUDIOOUT_PWRDN_RSRVD5(BV_AUDIOOUT_PWRDN_RSRVD5__##e) +#define BFM_AUDIOOUT_PWRDN_RSRVD5_V(v) BM_AUDIOOUT_PWRDN_RSRVD5 +#define BP_AUDIOOUT_PWRDN_RIGHT_ADC 16 +#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x10000 +#define BF_AUDIOOUT_PWRDN_RIGHT_ADC(v) (((v) & 0x1) << 16) +#define BFM_AUDIOOUT_PWRDN_RIGHT_ADC(v) BM_AUDIOOUT_PWRDN_RIGHT_ADC +#define BF_AUDIOOUT_PWRDN_RIGHT_ADC_V(e) BF_AUDIOOUT_PWRDN_RIGHT_ADC(BV_AUDIOOUT_PWRDN_RIGHT_ADC__##e) +#define BFM_AUDIOOUT_PWRDN_RIGHT_ADC_V(v) BM_AUDIOOUT_PWRDN_RIGHT_ADC +#define BP_AUDIOOUT_PWRDN_RSRVD4 13 +#define BM_AUDIOOUT_PWRDN_RSRVD4 0xe000 +#define BF_AUDIOOUT_PWRDN_RSRVD4(v) (((v) & 0x7) << 13) +#define BFM_AUDIOOUT_PWRDN_RSRVD4(v) BM_AUDIOOUT_PWRDN_RSRVD4 +#define BF_AUDIOOUT_PWRDN_RSRVD4_V(e) BF_AUDIOOUT_PWRDN_RSRVD4(BV_AUDIOOUT_PWRDN_RSRVD4__##e) +#define BFM_AUDIOOUT_PWRDN_RSRVD4_V(v) BM_AUDIOOUT_PWRDN_RSRVD4 +#define BP_AUDIOOUT_PWRDN_DAC 12 +#define BM_AUDIOOUT_PWRDN_DAC 0x1000 +#define BF_AUDIOOUT_PWRDN_DAC(v) (((v) & 0x1) << 12) +#define BFM_AUDIOOUT_PWRDN_DAC(v) BM_AUDIOOUT_PWRDN_DAC +#define BF_AUDIOOUT_PWRDN_DAC_V(e) BF_AUDIOOUT_PWRDN_DAC(BV_AUDIOOUT_PWRDN_DAC__##e) +#define BFM_AUDIOOUT_PWRDN_DAC_V(v) BM_AUDIOOUT_PWRDN_DAC +#define BP_AUDIOOUT_PWRDN_RSRVD3 9 +#define BM_AUDIOOUT_PWRDN_RSRVD3 0xe00 +#define BF_AUDIOOUT_PWRDN_RSRVD3(v) (((v) & 0x7) << 9) +#define BFM_AUDIOOUT_PWRDN_RSRVD3(v) BM_AUDIOOUT_PWRDN_RSRVD3 +#define BF_AUDIOOUT_PWRDN_RSRVD3_V(e) BF_AUDIOOUT_PWRDN_RSRVD3(BV_AUDIOOUT_PWRDN_RSRVD3__##e) +#define BFM_AUDIOOUT_PWRDN_RSRVD3_V(v) BM_AUDIOOUT_PWRDN_RSRVD3 +#define BP_AUDIOOUT_PWRDN_ADC 8 +#define BM_AUDIOOUT_PWRDN_ADC 0x100 +#define BF_AUDIOOUT_PWRDN_ADC(v) (((v) & 0x1) << 8) +#define BFM_AUDIOOUT_PWRDN_ADC(v) BM_AUDIOOUT_PWRDN_ADC +#define BF_AUDIOOUT_PWRDN_ADC_V(e) BF_AUDIOOUT_PWRDN_ADC(BV_AUDIOOUT_PWRDN_ADC__##e) +#define BFM_AUDIOOUT_PWRDN_ADC_V(v) BM_AUDIOOUT_PWRDN_ADC +#define BP_AUDIOOUT_PWRDN_RSRVD2 5 +#define BM_AUDIOOUT_PWRDN_RSRVD2 0xe0 +#define BF_AUDIOOUT_PWRDN_RSRVD2(v) (((v) & 0x7) << 5) +#define BFM_AUDIOOUT_PWRDN_RSRVD2(v) BM_AUDIOOUT_PWRDN_RSRVD2 +#define BF_AUDIOOUT_PWRDN_RSRVD2_V(e) BF_AUDIOOUT_PWRDN_RSRVD2(BV_AUDIOOUT_PWRDN_RSRVD2__##e) +#define BFM_AUDIOOUT_PWRDN_RSRVD2_V(v) BM_AUDIOOUT_PWRDN_RSRVD2 +#define BP_AUDIOOUT_PWRDN_CAPLESS 4 +#define BM_AUDIOOUT_PWRDN_CAPLESS 0x10 +#define BF_AUDIOOUT_PWRDN_CAPLESS(v) (((v) & 0x1) << 4) +#define BFM_AUDIOOUT_PWRDN_CAPLESS(v) BM_AUDIOOUT_PWRDN_CAPLESS +#define BF_AUDIOOUT_PWRDN_CAPLESS_V(e) BF_AUDIOOUT_PWRDN_CAPLESS(BV_AUDIOOUT_PWRDN_CAPLESS__##e) +#define BFM_AUDIOOUT_PWRDN_CAPLESS_V(v) BM_AUDIOOUT_PWRDN_CAPLESS +#define BP_AUDIOOUT_PWRDN_RSRVD1 1 +#define BM_AUDIOOUT_PWRDN_RSRVD1 0xe +#define BF_AUDIOOUT_PWRDN_RSRVD1(v) (((v) & 0x7) << 1) +#define BFM_AUDIOOUT_PWRDN_RSRVD1(v) BM_AUDIOOUT_PWRDN_RSRVD1 +#define BF_AUDIOOUT_PWRDN_RSRVD1_V(e) BF_AUDIOOUT_PWRDN_RSRVD1(BV_AUDIOOUT_PWRDN_RSRVD1__##e) +#define BFM_AUDIOOUT_PWRDN_RSRVD1_V(v) BM_AUDIOOUT_PWRDN_RSRVD1 +#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 +#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x1 +#define BF_AUDIOOUT_PWRDN_HEADPHONE(v) (((v) & 0x1) << 0) +#define BFM_AUDIOOUT_PWRDN_HEADPHONE(v) BM_AUDIOOUT_PWRDN_HEADPHONE +#define BF_AUDIOOUT_PWRDN_HEADPHONE_V(e) BF_AUDIOOUT_PWRDN_HEADPHONE(BV_AUDIOOUT_PWRDN_HEADPHONE__##e) +#define BFM_AUDIOOUT_PWRDN_HEADPHONE_V(v) BM_AUDIOOUT_PWRDN_HEADPHONE + +#define HW_AUDIOOUT_REFCTRL HW(AUDIOOUT_REFCTRL) +#define HWA_AUDIOOUT_REFCTRL (0x80048000 + 0x80) +#define HWT_AUDIOOUT_REFCTRL HWIO_32_RW +#define HWN_AUDIOOUT_REFCTRL AUDIOOUT_REFCTRL +#define HWI_AUDIOOUT_REFCTRL +#define HW_AUDIOOUT_REFCTRL_SET HW(AUDIOOUT_REFCTRL_SET) +#define HWA_AUDIOOUT_REFCTRL_SET (HWA_AUDIOOUT_REFCTRL + 0x4) +#define HWT_AUDIOOUT_REFCTRL_SET HWIO_32_WO +#define HWN_AUDIOOUT_REFCTRL_SET AUDIOOUT_REFCTRL +#define HWI_AUDIOOUT_REFCTRL_SET +#define HW_AUDIOOUT_REFCTRL_CLR HW(AUDIOOUT_REFCTRL_CLR) +#define HWA_AUDIOOUT_REFCTRL_CLR (HWA_AUDIOOUT_REFCTRL + 0x8) +#define HWT_AUDIOOUT_REFCTRL_CLR HWIO_32_WO +#define HWN_AUDIOOUT_REFCTRL_CLR AUDIOOUT_REFCTRL +#define HWI_AUDIOOUT_REFCTRL_CLR +#define HW_AUDIOOUT_REFCTRL_TOG HW(AUDIOOUT_REFCTRL_TOG) +#define HWA_AUDIOOUT_REFCTRL_TOG (HWA_AUDIOOUT_REFCTRL + 0xc) +#define HWT_AUDIOOUT_REFCTRL_TOG HWIO_32_WO +#define HWN_AUDIOOUT_REFCTRL_TOG AUDIOOUT_REFCTRL +#define HWI_AUDIOOUT_REFCTRL_TOG +#define BP_AUDIOOUT_REFCTRL_RSRVD4 27 +#define BM_AUDIOOUT_REFCTRL_RSRVD4 0xf8000000 +#define BF_AUDIOOUT_REFCTRL_RSRVD4(v) (((v) & 0x1f) << 27) +#define BFM_AUDIOOUT_REFCTRL_RSRVD4(v) BM_AUDIOOUT_REFCTRL_RSRVD4 +#define BF_AUDIOOUT_REFCTRL_RSRVD4_V(e) BF_AUDIOOUT_REFCTRL_RSRVD4(BV_AUDIOOUT_REFCTRL_RSRVD4__##e) +#define BFM_AUDIOOUT_REFCTRL_RSRVD4_V(v) BM_AUDIOOUT_REFCTRL_RSRVD4 +#define BP_AUDIOOUT_REFCTRL_FASTSETTLING 26 +#define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x4000000 +#define BF_AUDIOOUT_REFCTRL_FASTSETTLING(v) (((v) & 0x1) << 26) +#define BFM_AUDIOOUT_REFCTRL_FASTSETTLING(v) BM_AUDIOOUT_REFCTRL_FASTSETTLING +#define BF_AUDIOOUT_REFCTRL_FASTSETTLING_V(e) BF_AUDIOOUT_REFCTRL_FASTSETTLING(BV_AUDIOOUT_REFCTRL_FASTSETTLING__##e) +#define BFM_AUDIOOUT_REFCTRL_FASTSETTLING_V(v) BM_AUDIOOUT_REFCTRL_FASTSETTLING +#define BP_AUDIOOUT_REFCTRL_RAISE_REF 25 +#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x2000000 +#define BF_AUDIOOUT_REFCTRL_RAISE_REF(v) (((v) & 0x1) << 25) +#define BFM_AUDIOOUT_REFCTRL_RAISE_REF(v) BM_AUDIOOUT_REFCTRL_RAISE_REF +#define BF_AUDIOOUT_REFCTRL_RAISE_REF_V(e) BF_AUDIOOUT_REFCTRL_RAISE_REF(BV_AUDIOOUT_REFCTRL_RAISE_REF__##e) +#define BFM_AUDIOOUT_REFCTRL_RAISE_REF_V(v) BM_AUDIOOUT_REFCTRL_RAISE_REF +#define BP_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 24 +#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x1000000 +#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v) (((v) & 0x1) << 24) +#define BFM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(v) BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS +#define BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS_V(e) BF_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS(BV_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS__##e) +#define BFM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS_V(v) BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS +#define BP_AUDIOOUT_REFCTRL_RSRVD3 23 +#define BM_AUDIOOUT_REFCTRL_RSRVD3 0x800000 +#define BF_AUDIOOUT_REFCTRL_RSRVD3(v) (((v) & 0x1) << 23) +#define BFM_AUDIOOUT_REFCTRL_RSRVD3(v) BM_AUDIOOUT_REFCTRL_RSRVD3 +#define BF_AUDIOOUT_REFCTRL_RSRVD3_V(e) BF_AUDIOOUT_REFCTRL_RSRVD3(BV_AUDIOOUT_REFCTRL_RSRVD3__##e) +#define BFM_AUDIOOUT_REFCTRL_RSRVD3_V(v) BM_AUDIOOUT_REFCTRL_RSRVD3 +#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 +#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x700000 +#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) (((v) & 0x7) << 20) +#define BFM_AUDIOOUT_REFCTRL_VBG_ADJ(v) BM_AUDIOOUT_REFCTRL_VBG_ADJ +#define BF_AUDIOOUT_REFCTRL_VBG_ADJ_V(e) BF_AUDIOOUT_REFCTRL_VBG_ADJ(BV_AUDIOOUT_REFCTRL_VBG_ADJ__##e) +#define BFM_AUDIOOUT_REFCTRL_VBG_ADJ_V(v) BM_AUDIOOUT_REFCTRL_VBG_ADJ +#define BP_AUDIOOUT_REFCTRL_LOW_PWR 19 +#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x80000 +#define BF_AUDIOOUT_REFCTRL_LOW_PWR(v) (((v) & 0x1) << 19) +#define BFM_AUDIOOUT_REFCTRL_LOW_PWR(v) BM_AUDIOOUT_REFCTRL_LOW_PWR +#define BF_AUDIOOUT_REFCTRL_LOW_PWR_V(e) BF_AUDIOOUT_REFCTRL_LOW_PWR(BV_AUDIOOUT_REFCTRL_LOW_PWR__##e) +#define BFM_AUDIOOUT_REFCTRL_LOW_PWR_V(v) BM_AUDIOOUT_REFCTRL_LOW_PWR +#define BP_AUDIOOUT_REFCTRL_LW_REF 18 +#define BM_AUDIOOUT_REFCTRL_LW_REF 0x40000 +#define BF_AUDIOOUT_REFCTRL_LW_REF(v) (((v) & 0x1) << 18) +#define BFM_AUDIOOUT_REFCTRL_LW_REF(v) BM_AUDIOOUT_REFCTRL_LW_REF +#define BF_AUDIOOUT_REFCTRL_LW_REF_V(e) BF_AUDIOOUT_REFCTRL_LW_REF(BV_AUDIOOUT_REFCTRL_LW_REF__##e) +#define BFM_AUDIOOUT_REFCTRL_LW_REF_V(v) BM_AUDIOOUT_REFCTRL_LW_REF +#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 +#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x30000 +#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) (((v) & 0x3) << 16) +#define BFM_AUDIOOUT_REFCTRL_BIAS_CTRL(v) BM_AUDIOOUT_REFCTRL_BIAS_CTRL +#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL_V(e) BF_AUDIOOUT_REFCTRL_BIAS_CTRL(BV_AUDIOOUT_REFCTRL_BIAS_CTRL__##e) +#define BFM_AUDIOOUT_REFCTRL_BIAS_CTRL_V(v) BM_AUDIOOUT_REFCTRL_BIAS_CTRL +#define BP_AUDIOOUT_REFCTRL_RSRVD2 15 +#define BM_AUDIOOUT_REFCTRL_RSRVD2 0x8000 +#define BF_AUDIOOUT_REFCTRL_RSRVD2(v) (((v) & 0x1) << 15) +#define BFM_AUDIOOUT_REFCTRL_RSRVD2(v) BM_AUDIOOUT_REFCTRL_RSRVD2 +#define BF_AUDIOOUT_REFCTRL_RSRVD2_V(e) BF_AUDIOOUT_REFCTRL_RSRVD2(BV_AUDIOOUT_REFCTRL_RSRVD2__##e) +#define BFM_AUDIOOUT_REFCTRL_RSRVD2_V(v) BM_AUDIOOUT_REFCTRL_RSRVD2 +#define BP_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 14 +#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x4000 +#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v) (((v) & 0x1) << 14) +#define BFM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(v) BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD +#define BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD_V(e) BF_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD(BV_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD__##e) +#define BFM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD_V(v) BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD +#define BP_AUDIOOUT_REFCTRL_ADJ_ADC 13 +#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x2000 +#define BF_AUDIOOUT_REFCTRL_ADJ_ADC(v) (((v) & 0x1) << 13) +#define BFM_AUDIOOUT_REFCTRL_ADJ_ADC(v) BM_AUDIOOUT_REFCTRL_ADJ_ADC +#define BF_AUDIOOUT_REFCTRL_ADJ_ADC_V(e) BF_AUDIOOUT_REFCTRL_ADJ_ADC(BV_AUDIOOUT_REFCTRL_ADJ_ADC__##e) +#define BFM_AUDIOOUT_REFCTRL_ADJ_ADC_V(v) BM_AUDIOOUT_REFCTRL_ADJ_ADC +#define BP_AUDIOOUT_REFCTRL_ADJ_VAG 12 +#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x1000 +#define BF_AUDIOOUT_REFCTRL_ADJ_VAG(v) (((v) & 0x1) << 12) +#define BFM_AUDIOOUT_REFCTRL_ADJ_VAG(v) BM_AUDIOOUT_REFCTRL_ADJ_VAG +#define BF_AUDIOOUT_REFCTRL_ADJ_VAG_V(e) BF_AUDIOOUT_REFCTRL_ADJ_VAG(BV_AUDIOOUT_REFCTRL_ADJ_VAG__##e) +#define BFM_AUDIOOUT_REFCTRL_ADJ_VAG_V(v) BM_AUDIOOUT_REFCTRL_ADJ_VAG +#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 +#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0xf00 +#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) (((v) & 0xf) << 8) +#define BFM_AUDIOOUT_REFCTRL_ADC_REFVAL(v) BM_AUDIOOUT_REFCTRL_ADC_REFVAL +#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL_V(e) BF_AUDIOOUT_REFCTRL_ADC_REFVAL(BV_AUDIOOUT_REFCTRL_ADC_REFVAL__##e) +#define BFM_AUDIOOUT_REFCTRL_ADC_REFVAL_V(v) BM_AUDIOOUT_REFCTRL_ADC_REFVAL +#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 +#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0xf0 +#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) (((v) & 0xf) << 4) +#define BFM_AUDIOOUT_REFCTRL_VAG_VAL(v) BM_AUDIOOUT_REFCTRL_VAG_VAL +#define BF_AUDIOOUT_REFCTRL_VAG_VAL_V(e) BF_AUDIOOUT_REFCTRL_VAG_VAL(BV_AUDIOOUT_REFCTRL_VAG_VAL__##e) +#define BFM_AUDIOOUT_REFCTRL_VAG_VAL_V(v) BM_AUDIOOUT_REFCTRL_VAG_VAL +#define BP_AUDIOOUT_REFCTRL_RSRVD1 3 +#define BM_AUDIOOUT_REFCTRL_RSRVD1 0x8 +#define BF_AUDIOOUT_REFCTRL_RSRVD1(v) (((v) & 0x1) << 3) +#define BFM_AUDIOOUT_REFCTRL_RSRVD1(v) BM_AUDIOOUT_REFCTRL_RSRVD1 +#define BF_AUDIOOUT_REFCTRL_RSRVD1_V(e) BF_AUDIOOUT_REFCTRL_RSRVD1(BV_AUDIOOUT_REFCTRL_RSRVD1__##e) +#define BFM_AUDIOOUT_REFCTRL_RSRVD1_V(v) BM_AUDIOOUT_REFCTRL_RSRVD1 +#define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0 +#define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x7 +#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) (((v) & 0x7) << 0) +#define BFM_AUDIOOUT_REFCTRL_DAC_ADJ(v) BM_AUDIOOUT_REFCTRL_DAC_ADJ +#define BF_AUDIOOUT_REFCTRL_DAC_ADJ_V(e) BF_AUDIOOUT_REFCTRL_DAC_ADJ(BV_AUDIOOUT_REFCTRL_DAC_ADJ__##e) +#define BFM_AUDIOOUT_REFCTRL_DAC_ADJ_V(v) BM_AUDIOOUT_REFCTRL_DAC_ADJ + +#define HW_AUDIOOUT_ANACTRL HW(AUDIOOUT_ANACTRL) +#define HWA_AUDIOOUT_ANACTRL (0x80048000 + 0x90) +#define HWT_AUDIOOUT_ANACTRL HWIO_32_RW +#define HWN_AUDIOOUT_ANACTRL AUDIOOUT_ANACTRL +#define HWI_AUDIOOUT_ANACTRL +#define HW_AUDIOOUT_ANACTRL_SET HW(AUDIOOUT_ANACTRL_SET) +#define HWA_AUDIOOUT_ANACTRL_SET (HWA_AUDIOOUT_ANACTRL + 0x4) +#define HWT_AUDIOOUT_ANACTRL_SET HWIO_32_WO +#define HWN_AUDIOOUT_ANACTRL_SET AUDIOOUT_ANACTRL +#define HWI_AUDIOOUT_ANACTRL_SET +#define HW_AUDIOOUT_ANACTRL_CLR HW(AUDIOOUT_ANACTRL_CLR) +#define HWA_AUDIOOUT_ANACTRL_CLR (HWA_AUDIOOUT_ANACTRL + 0x8) +#define HWT_AUDIOOUT_ANACTRL_CLR HWIO_32_WO +#define HWN_AUDIOOUT_ANACTRL_CLR AUDIOOUT_ANACTRL +#define HWI_AUDIOOUT_ANACTRL_CLR +#define HW_AUDIOOUT_ANACTRL_TOG HW(AUDIOOUT_ANACTRL_TOG) +#define HWA_AUDIOOUT_ANACTRL_TOG (HWA_AUDIOOUT_ANACTRL + 0xc) +#define HWT_AUDIOOUT_ANACTRL_TOG HWIO_32_WO +#define HWN_AUDIOOUT_ANACTRL_TOG AUDIOOUT_ANACTRL +#define HWI_AUDIOOUT_ANACTRL_TOG +#define BP_AUDIOOUT_ANACTRL_RSRVD8 29 +#define BM_AUDIOOUT_ANACTRL_RSRVD8 0xe0000000 +#define BF_AUDIOOUT_ANACTRL_RSRVD8(v) (((v) & 0x7) << 29) +#define BFM_AUDIOOUT_ANACTRL_RSRVD8(v) BM_AUDIOOUT_ANACTRL_RSRVD8 +#define BF_AUDIOOUT_ANACTRL_RSRVD8_V(e) BF_AUDIOOUT_ANACTRL_RSRVD8(BV_AUDIOOUT_ANACTRL_RSRVD8__##e) +#define BFM_AUDIOOUT_ANACTRL_RSRVD8_V(v) BM_AUDIOOUT_ANACTRL_RSRVD8 +#define BP_AUDIOOUT_ANACTRL_SHORT_CM_STS 28 +#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000 +#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(v) (((v) & 0x1) << 28) +#define BFM_AUDIOOUT_ANACTRL_SHORT_CM_STS(v) BM_AUDIOOUT_ANACTRL_SHORT_CM_STS +#define BF_AUDIOOUT_ANACTRL_SHORT_CM_STS_V(e) BF_AUDIOOUT_ANACTRL_SHORT_CM_STS(BV_AUDIOOUT_ANACTRL_SHORT_CM_STS__##e) +#define BFM_AUDIOOUT_ANACTRL_SHORT_CM_STS_V(v) BM_AUDIOOUT_ANACTRL_SHORT_CM_STS +#define BP_AUDIOOUT_ANACTRL_RSRVD7 25 +#define BM_AUDIOOUT_ANACTRL_RSRVD7 0xe000000 +#define BF_AUDIOOUT_ANACTRL_RSRVD7(v) (((v) & 0x7) << 25) +#define BFM_AUDIOOUT_ANACTRL_RSRVD7(v) BM_AUDIOOUT_ANACTRL_RSRVD7 +#define BF_AUDIOOUT_ANACTRL_RSRVD7_V(e) BF_AUDIOOUT_ANACTRL_RSRVD7(BV_AUDIOOUT_ANACTRL_RSRVD7__##e) +#define BFM_AUDIOOUT_ANACTRL_RSRVD7_V(v) BM_AUDIOOUT_ANACTRL_RSRVD7 +#define BP_AUDIOOUT_ANACTRL_SHORT_LR_STS 24 +#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x1000000 +#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(v) (((v) & 0x1) << 24) +#define BFM_AUDIOOUT_ANACTRL_SHORT_LR_STS(v) BM_AUDIOOUT_ANACTRL_SHORT_LR_STS +#define BF_AUDIOOUT_ANACTRL_SHORT_LR_STS_V(e) BF_AUDIOOUT_ANACTRL_SHORT_LR_STS(BV_AUDIOOUT_ANACTRL_SHORT_LR_STS__##e) +#define BFM_AUDIOOUT_ANACTRL_SHORT_LR_STS_V(v) BM_AUDIOOUT_ANACTRL_SHORT_LR_STS +#define BP_AUDIOOUT_ANACTRL_RSRVD6 22 +#define BM_AUDIOOUT_ANACTRL_RSRVD6 0xc00000 +#define BF_AUDIOOUT_ANACTRL_RSRVD6(v) (((v) & 0x3) << 22) +#define BFM_AUDIOOUT_ANACTRL_RSRVD6(v) BM_AUDIOOUT_ANACTRL_RSRVD6 +#define BF_AUDIOOUT_ANACTRL_RSRVD6_V(e) BF_AUDIOOUT_ANACTRL_RSRVD6(BV_AUDIOOUT_ANACTRL_RSRVD6__##e) +#define BFM_AUDIOOUT_ANACTRL_RSRVD6_V(v) BM_AUDIOOUT_ANACTRL_RSRVD6 +#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20 +#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x300000 +#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) (((v) & 0x3) << 20) +#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) BM_AUDIOOUT_ANACTRL_SHORTMODE_CM +#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM_V(e) BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(BV_AUDIOOUT_ANACTRL_SHORTMODE_CM__##e) +#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_CM_V(v) BM_AUDIOOUT_ANACTRL_SHORTMODE_CM +#define BP_AUDIOOUT_ANACTRL_RSRVD5 19 +#define BM_AUDIOOUT_ANACTRL_RSRVD5 0x80000 +#define BF_AUDIOOUT_ANACTRL_RSRVD5(v) (((v) & 0x1) << 19) +#define BFM_AUDIOOUT_ANACTRL_RSRVD5(v) BM_AUDIOOUT_ANACTRL_RSRVD5 +#define BF_AUDIOOUT_ANACTRL_RSRVD5_V(e) BF_AUDIOOUT_ANACTRL_RSRVD5(BV_AUDIOOUT_ANACTRL_RSRVD5__##e) +#define BFM_AUDIOOUT_ANACTRL_RSRVD5_V(v) BM_AUDIOOUT_ANACTRL_RSRVD5 +#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17 +#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x60000 +#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) (((v) & 0x3) << 17) +#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) BM_AUDIOOUT_ANACTRL_SHORTMODE_LR +#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR_V(e) BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(BV_AUDIOOUT_ANACTRL_SHORTMODE_LR__##e) +#define BFM_AUDIOOUT_ANACTRL_SHORTMODE_LR_V(v) BM_AUDIOOUT_ANACTRL_SHORTMODE_LR +#define BP_AUDIOOUT_ANACTRL_RSRVD4 15 +#define BM_AUDIOOUT_ANACTRL_RSRVD4 0x18000 +#define BF_AUDIOOUT_ANACTRL_RSRVD4(v) (((v) & 0x3) << 15) +#define BFM_AUDIOOUT_ANACTRL_RSRVD4(v) BM_AUDIOOUT_ANACTRL_RSRVD4 +#define BF_AUDIOOUT_ANACTRL_RSRVD4_V(e) BF_AUDIOOUT_ANACTRL_RSRVD4(BV_AUDIOOUT_ANACTRL_RSRVD4__##e) +#define BFM_AUDIOOUT_ANACTRL_RSRVD4_V(v) BM_AUDIOOUT_ANACTRL_RSRVD4 +#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12 +#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x7000 +#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) (((v) & 0x7) << 12) +#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL +#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL_V(e) BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(BV_AUDIOOUT_ANACTRL_SHORT_LVLADJL__##e) +#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJL_V(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL +#define BP_AUDIOOUT_ANACTRL_RSRVD3 11 +#define BM_AUDIOOUT_ANACTRL_RSRVD3 0x800 +#define BF_AUDIOOUT_ANACTRL_RSRVD3(v) (((v) & 0x1) << 11) +#define BFM_AUDIOOUT_ANACTRL_RSRVD3(v) BM_AUDIOOUT_ANACTRL_RSRVD3 +#define BF_AUDIOOUT_ANACTRL_RSRVD3_V(e) BF_AUDIOOUT_ANACTRL_RSRVD3(BV_AUDIOOUT_ANACTRL_RSRVD3__##e) +#define BFM_AUDIOOUT_ANACTRL_RSRVD3_V(v) BM_AUDIOOUT_ANACTRL_RSRVD3 +#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8 +#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x700 +#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) (((v) & 0x7) << 8) +#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR +#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR_V(e) BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(BV_AUDIOOUT_ANACTRL_SHORT_LVLADJR__##e) +#define BFM_AUDIOOUT_ANACTRL_SHORT_LVLADJR_V(v) BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR +#define BP_AUDIOOUT_ANACTRL_RSRVD2 6 +#define BM_AUDIOOUT_ANACTRL_RSRVD2 0xc0 +#define BF_AUDIOOUT_ANACTRL_RSRVD2(v) (((v) & 0x3) << 6) +#define BFM_AUDIOOUT_ANACTRL_RSRVD2(v) BM_AUDIOOUT_ANACTRL_RSRVD2 +#define BF_AUDIOOUT_ANACTRL_RSRVD2_V(e) BF_AUDIOOUT_ANACTRL_RSRVD2(BV_AUDIOOUT_ANACTRL_RSRVD2__##e) +#define BFM_AUDIOOUT_ANACTRL_RSRVD2_V(v) BM_AUDIOOUT_ANACTRL_RSRVD2 +#define BP_AUDIOOUT_ANACTRL_HP_HOLD_GND 5 +#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x20 +#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(v) (((v) & 0x1) << 5) +#define BFM_AUDIOOUT_ANACTRL_HP_HOLD_GND(v) BM_AUDIOOUT_ANACTRL_HP_HOLD_GND +#define BF_AUDIOOUT_ANACTRL_HP_HOLD_GND_V(e) BF_AUDIOOUT_ANACTRL_HP_HOLD_GND(BV_AUDIOOUT_ANACTRL_HP_HOLD_GND__##e) +#define BFM_AUDIOOUT_ANACTRL_HP_HOLD_GND_V(v) BM_AUDIOOUT_ANACTRL_HP_HOLD_GND +#define BP_AUDIOOUT_ANACTRL_HP_CLASSAB 4 +#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x10 +#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB(v) (((v) & 0x1) << 4) +#define BFM_AUDIOOUT_ANACTRL_HP_CLASSAB(v) BM_AUDIOOUT_ANACTRL_HP_CLASSAB +#define BF_AUDIOOUT_ANACTRL_HP_CLASSAB_V(e) BF_AUDIOOUT_ANACTRL_HP_CLASSAB(BV_AUDIOOUT_ANACTRL_HP_CLASSAB__##e) +#define BFM_AUDIOOUT_ANACTRL_HP_CLASSAB_V(v) BM_AUDIOOUT_ANACTRL_HP_CLASSAB +#define BP_AUDIOOUT_ANACTRL_RSRVD1 0 +#define BM_AUDIOOUT_ANACTRL_RSRVD1 0xf +#define BF_AUDIOOUT_ANACTRL_RSRVD1(v) (((v) & 0xf) << 0) +#define BFM_AUDIOOUT_ANACTRL_RSRVD1(v) BM_AUDIOOUT_ANACTRL_RSRVD1 +#define BF_AUDIOOUT_ANACTRL_RSRVD1_V(e) BF_AUDIOOUT_ANACTRL_RSRVD1(BV_AUDIOOUT_ANACTRL_RSRVD1__##e) +#define BFM_AUDIOOUT_ANACTRL_RSRVD1_V(v) BM_AUDIOOUT_ANACTRL_RSRVD1 + +#define HW_AUDIOOUT_TEST HW(AUDIOOUT_TEST) +#define HWA_AUDIOOUT_TEST (0x80048000 + 0xa0) +#define HWT_AUDIOOUT_TEST HWIO_32_RW +#define HWN_AUDIOOUT_TEST AUDIOOUT_TEST +#define HWI_AUDIOOUT_TEST +#define HW_AUDIOOUT_TEST_SET HW(AUDIOOUT_TEST_SET) +#define HWA_AUDIOOUT_TEST_SET (HWA_AUDIOOUT_TEST + 0x4) +#define HWT_AUDIOOUT_TEST_SET HWIO_32_WO +#define HWN_AUDIOOUT_TEST_SET AUDIOOUT_TEST +#define HWI_AUDIOOUT_TEST_SET +#define HW_AUDIOOUT_TEST_CLR HW(AUDIOOUT_TEST_CLR) +#define HWA_AUDIOOUT_TEST_CLR (HWA_AUDIOOUT_TEST + 0x8) +#define HWT_AUDIOOUT_TEST_CLR HWIO_32_WO +#define HWN_AUDIOOUT_TEST_CLR AUDIOOUT_TEST +#define HWI_AUDIOOUT_TEST_CLR +#define HW_AUDIOOUT_TEST_TOG HW(AUDIOOUT_TEST_TOG) +#define HWA_AUDIOOUT_TEST_TOG (HWA_AUDIOOUT_TEST + 0xc) +#define HWT_AUDIOOUT_TEST_TOG HWIO_32_WO +#define HWN_AUDIOOUT_TEST_TOG AUDIOOUT_TEST +#define HWI_AUDIOOUT_TEST_TOG +#define BP_AUDIOOUT_TEST_RSRVD4 31 +#define BM_AUDIOOUT_TEST_RSRVD4 0x80000000 +#define BF_AUDIOOUT_TEST_RSRVD4(v) (((v) & 0x1) << 31) +#define BFM_AUDIOOUT_TEST_RSRVD4(v) BM_AUDIOOUT_TEST_RSRVD4 +#define BF_AUDIOOUT_TEST_RSRVD4_V(e) BF_AUDIOOUT_TEST_RSRVD4(BV_AUDIOOUT_TEST_RSRVD4__##e) +#define BFM_AUDIOOUT_TEST_RSRVD4_V(v) BM_AUDIOOUT_TEST_RSRVD4 +#define BP_AUDIOOUT_TEST_HP_ANTIPOP 28 +#define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000 +#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) (((v) & 0x7) << 28) +#define BFM_AUDIOOUT_TEST_HP_ANTIPOP(v) BM_AUDIOOUT_TEST_HP_ANTIPOP +#define BF_AUDIOOUT_TEST_HP_ANTIPOP_V(e) BF_AUDIOOUT_TEST_HP_ANTIPOP(BV_AUDIOOUT_TEST_HP_ANTIPOP__##e) +#define BFM_AUDIOOUT_TEST_HP_ANTIPOP_V(v) BM_AUDIOOUT_TEST_HP_ANTIPOP +#define BP_AUDIOOUT_TEST_RSRVD3 27 +#define BM_AUDIOOUT_TEST_RSRVD3 0x8000000 +#define BF_AUDIOOUT_TEST_RSRVD3(v) (((v) & 0x1) << 27) +#define BFM_AUDIOOUT_TEST_RSRVD3(v) BM_AUDIOOUT_TEST_RSRVD3 +#define BF_AUDIOOUT_TEST_RSRVD3_V(e) BF_AUDIOOUT_TEST_RSRVD3(BV_AUDIOOUT_TEST_RSRVD3__##e) +#define BFM_AUDIOOUT_TEST_RSRVD3_V(v) BM_AUDIOOUT_TEST_RSRVD3 +#define BP_AUDIOOUT_TEST_TM_ADCIN_TOHP 26 +#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x4000000 +#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(v) (((v) & 0x1) << 26) +#define BFM_AUDIOOUT_TEST_TM_ADCIN_TOHP(v) BM_AUDIOOUT_TEST_TM_ADCIN_TOHP +#define BF_AUDIOOUT_TEST_TM_ADCIN_TOHP_V(e) BF_AUDIOOUT_TEST_TM_ADCIN_TOHP(BV_AUDIOOUT_TEST_TM_ADCIN_TOHP__##e) +#define BFM_AUDIOOUT_TEST_TM_ADCIN_TOHP_V(v) BM_AUDIOOUT_TEST_TM_ADCIN_TOHP +#define BP_AUDIOOUT_TEST_TM_LOOP 25 +#define BM_AUDIOOUT_TEST_TM_LOOP 0x2000000 +#define BF_AUDIOOUT_TEST_TM_LOOP(v) (((v) & 0x1) << 25) +#define BFM_AUDIOOUT_TEST_TM_LOOP(v) BM_AUDIOOUT_TEST_TM_LOOP +#define BF_AUDIOOUT_TEST_TM_LOOP_V(e) BF_AUDIOOUT_TEST_TM_LOOP(BV_AUDIOOUT_TEST_TM_LOOP__##e) +#define BFM_AUDIOOUT_TEST_TM_LOOP_V(v) BM_AUDIOOUT_TEST_TM_LOOP +#define BP_AUDIOOUT_TEST_TM_HPCOMMON 24 +#define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x1000000 +#define BF_AUDIOOUT_TEST_TM_HPCOMMON(v) (((v) & 0x1) << 24) +#define BFM_AUDIOOUT_TEST_TM_HPCOMMON(v) BM_AUDIOOUT_TEST_TM_HPCOMMON +#define BF_AUDIOOUT_TEST_TM_HPCOMMON_V(e) BF_AUDIOOUT_TEST_TM_HPCOMMON(BV_AUDIOOUT_TEST_TM_HPCOMMON__##e) +#define BFM_AUDIOOUT_TEST_TM_HPCOMMON_V(v) BM_AUDIOOUT_TEST_TM_HPCOMMON +#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 +#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0xc00000 +#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) (((v) & 0x3) << 22) +#define BFM_AUDIOOUT_TEST_HP_I1_ADJ(v) BM_AUDIOOUT_TEST_HP_I1_ADJ +#define BF_AUDIOOUT_TEST_HP_I1_ADJ_V(e) BF_AUDIOOUT_TEST_HP_I1_ADJ(BV_AUDIOOUT_TEST_HP_I1_ADJ__##e) +#define BFM_AUDIOOUT_TEST_HP_I1_ADJ_V(v) BM_AUDIOOUT_TEST_HP_I1_ADJ +#define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20 +#define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x300000 +#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) (((v) & 0x3) << 20) +#define BFM_AUDIOOUT_TEST_HP_IALL_ADJ(v) BM_AUDIOOUT_TEST_HP_IALL_ADJ +#define BF_AUDIOOUT_TEST_HP_IALL_ADJ_V(e) BF_AUDIOOUT_TEST_HP_IALL_ADJ(BV_AUDIOOUT_TEST_HP_IALL_ADJ__##e) +#define BFM_AUDIOOUT_TEST_HP_IALL_ADJ_V(v) BM_AUDIOOUT_TEST_HP_IALL_ADJ +#define BP_AUDIOOUT_TEST_RSRVD2 14 +#define BM_AUDIOOUT_TEST_RSRVD2 0xfc000 +#define BF_AUDIOOUT_TEST_RSRVD2(v) (((v) & 0x3f) << 14) +#define BFM_AUDIOOUT_TEST_RSRVD2(v) BM_AUDIOOUT_TEST_RSRVD2 +#define BF_AUDIOOUT_TEST_RSRVD2_V(e) BF_AUDIOOUT_TEST_RSRVD2(BV_AUDIOOUT_TEST_RSRVD2__##e) +#define BFM_AUDIOOUT_TEST_RSRVD2_V(v) BM_AUDIOOUT_TEST_RSRVD2 +#define BP_AUDIOOUT_TEST_VAG_CLASSA 13 +#define BM_AUDIOOUT_TEST_VAG_CLASSA 0x2000 +#define BF_AUDIOOUT_TEST_VAG_CLASSA(v) (((v) & 0x1) << 13) +#define BFM_AUDIOOUT_TEST_VAG_CLASSA(v) BM_AUDIOOUT_TEST_VAG_CLASSA +#define BF_AUDIOOUT_TEST_VAG_CLASSA_V(e) BF_AUDIOOUT_TEST_VAG_CLASSA(BV_AUDIOOUT_TEST_VAG_CLASSA__##e) +#define BFM_AUDIOOUT_TEST_VAG_CLASSA_V(v) BM_AUDIOOUT_TEST_VAG_CLASSA +#define BP_AUDIOOUT_TEST_VAG_DOUBLE_I 12 +#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x1000 +#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I(v) (((v) & 0x1) << 12) +#define BFM_AUDIOOUT_TEST_VAG_DOUBLE_I(v) BM_AUDIOOUT_TEST_VAG_DOUBLE_I +#define BF_AUDIOOUT_TEST_VAG_DOUBLE_I_V(e) BF_AUDIOOUT_TEST_VAG_DOUBLE_I(BV_AUDIOOUT_TEST_VAG_DOUBLE_I__##e) +#define BFM_AUDIOOUT_TEST_VAG_DOUBLE_I_V(v) BM_AUDIOOUT_TEST_VAG_DOUBLE_I +#define BP_AUDIOOUT_TEST_RSRVD1 4 +#define BM_AUDIOOUT_TEST_RSRVD1 0xff0 +#define BF_AUDIOOUT_TEST_RSRVD1(v) (((v) & 0xff) << 4) +#define BFM_AUDIOOUT_TEST_RSRVD1(v) BM_AUDIOOUT_TEST_RSRVD1 +#define BF_AUDIOOUT_TEST_RSRVD1_V(e) BF_AUDIOOUT_TEST_RSRVD1(BV_AUDIOOUT_TEST_RSRVD1__##e) +#define BFM_AUDIOOUT_TEST_RSRVD1_V(v) BM_AUDIOOUT_TEST_RSRVD1 +#define BP_AUDIOOUT_TEST_ADCTODAC_LOOP 3 +#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP 0x8 +#define BF_AUDIOOUT_TEST_ADCTODAC_LOOP(v) (((v) & 0x1) << 3) +#define BFM_AUDIOOUT_TEST_ADCTODAC_LOOP(v) BM_AUDIOOUT_TEST_ADCTODAC_LOOP +#define BF_AUDIOOUT_TEST_ADCTODAC_LOOP_V(e) BF_AUDIOOUT_TEST_ADCTODAC_LOOP(BV_AUDIOOUT_TEST_ADCTODAC_LOOP__##e) +#define BFM_AUDIOOUT_TEST_ADCTODAC_LOOP_V(v) BM_AUDIOOUT_TEST_ADCTODAC_LOOP +#define BP_AUDIOOUT_TEST_DAC_CLASSA 2 +#define BM_AUDIOOUT_TEST_DAC_CLASSA 0x4 +#define BF_AUDIOOUT_TEST_DAC_CLASSA(v) (((v) & 0x1) << 2) +#define BFM_AUDIOOUT_TEST_DAC_CLASSA(v) BM_AUDIOOUT_TEST_DAC_CLASSA +#define BF_AUDIOOUT_TEST_DAC_CLASSA_V(e) BF_AUDIOOUT_TEST_DAC_CLASSA(BV_AUDIOOUT_TEST_DAC_CLASSA__##e) +#define BFM_AUDIOOUT_TEST_DAC_CLASSA_V(v) BM_AUDIOOUT_TEST_DAC_CLASSA +#define BP_AUDIOOUT_TEST_DAC_DOUBLE_I 1 +#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x2 +#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I(v) (((v) & 0x1) << 1) +#define BFM_AUDIOOUT_TEST_DAC_DOUBLE_I(v) BM_AUDIOOUT_TEST_DAC_DOUBLE_I +#define BF_AUDIOOUT_TEST_DAC_DOUBLE_I_V(e) BF_AUDIOOUT_TEST_DAC_DOUBLE_I(BV_AUDIOOUT_TEST_DAC_DOUBLE_I__##e) +#define BFM_AUDIOOUT_TEST_DAC_DOUBLE_I_V(v) BM_AUDIOOUT_TEST_DAC_DOUBLE_I +#define BP_AUDIOOUT_TEST_DAC_DIS_RTZ 0 +#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x1 +#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ(v) (((v) & 0x1) << 0) +#define BFM_AUDIOOUT_TEST_DAC_DIS_RTZ(v) BM_AUDIOOUT_TEST_DAC_DIS_RTZ +#define BF_AUDIOOUT_TEST_DAC_DIS_RTZ_V(e) BF_AUDIOOUT_TEST_DAC_DIS_RTZ(BV_AUDIOOUT_TEST_DAC_DIS_RTZ__##e) +#define BFM_AUDIOOUT_TEST_DAC_DIS_RTZ_V(v) BM_AUDIOOUT_TEST_DAC_DIS_RTZ + +#define HW_AUDIOOUT_BISTCTRL HW(AUDIOOUT_BISTCTRL) +#define HWA_AUDIOOUT_BISTCTRL (0x80048000 + 0xb0) +#define HWT_AUDIOOUT_BISTCTRL HWIO_32_RW +#define HWN_AUDIOOUT_BISTCTRL AUDIOOUT_BISTCTRL +#define HWI_AUDIOOUT_BISTCTRL +#define HW_AUDIOOUT_BISTCTRL_SET HW(AUDIOOUT_BISTCTRL_SET) +#define HWA_AUDIOOUT_BISTCTRL_SET (HWA_AUDIOOUT_BISTCTRL + 0x4) +#define HWT_AUDIOOUT_BISTCTRL_SET HWIO_32_WO +#define HWN_AUDIOOUT_BISTCTRL_SET AUDIOOUT_BISTCTRL +#define HWI_AUDIOOUT_BISTCTRL_SET +#define HW_AUDIOOUT_BISTCTRL_CLR HW(AUDIOOUT_BISTCTRL_CLR) +#define HWA_AUDIOOUT_BISTCTRL_CLR (HWA_AUDIOOUT_BISTCTRL + 0x8) +#define HWT_AUDIOOUT_BISTCTRL_CLR HWIO_32_WO +#define HWN_AUDIOOUT_BISTCTRL_CLR AUDIOOUT_BISTCTRL +#define HWI_AUDIOOUT_BISTCTRL_CLR +#define HW_AUDIOOUT_BISTCTRL_TOG HW(AUDIOOUT_BISTCTRL_TOG) +#define HWA_AUDIOOUT_BISTCTRL_TOG (HWA_AUDIOOUT_BISTCTRL + 0xc) +#define HWT_AUDIOOUT_BISTCTRL_TOG HWIO_32_WO +#define HWN_AUDIOOUT_BISTCTRL_TOG AUDIOOUT_BISTCTRL +#define HWI_AUDIOOUT_BISTCTRL_TOG +#define BP_AUDIOOUT_BISTCTRL_RSVD0 4 +#define BM_AUDIOOUT_BISTCTRL_RSVD0 0xfffffff0 +#define BF_AUDIOOUT_BISTCTRL_RSVD0(v) (((v) & 0xfffffff) << 4) +#define BFM_AUDIOOUT_BISTCTRL_RSVD0(v) BM_AUDIOOUT_BISTCTRL_RSVD0 +#define BF_AUDIOOUT_BISTCTRL_RSVD0_V(e) BF_AUDIOOUT_BISTCTRL_RSVD0(BV_AUDIOOUT_BISTCTRL_RSVD0__##e) +#define BFM_AUDIOOUT_BISTCTRL_RSVD0_V(v) BM_AUDIOOUT_BISTCTRL_RSVD0 +#define BP_AUDIOOUT_BISTCTRL_FAIL 3 +#define BM_AUDIOOUT_BISTCTRL_FAIL 0x8 +#define BF_AUDIOOUT_BISTCTRL_FAIL(v) (((v) & 0x1) << 3) +#define BFM_AUDIOOUT_BISTCTRL_FAIL(v) BM_AUDIOOUT_BISTCTRL_FAIL +#define BF_AUDIOOUT_BISTCTRL_FAIL_V(e) BF_AUDIOOUT_BISTCTRL_FAIL(BV_AUDIOOUT_BISTCTRL_FAIL__##e) +#define BFM_AUDIOOUT_BISTCTRL_FAIL_V(v) BM_AUDIOOUT_BISTCTRL_FAIL +#define BP_AUDIOOUT_BISTCTRL_PASS 2 +#define BM_AUDIOOUT_BISTCTRL_PASS 0x4 +#define BF_AUDIOOUT_BISTCTRL_PASS(v) (((v) & 0x1) << 2) +#define BFM_AUDIOOUT_BISTCTRL_PASS(v) BM_AUDIOOUT_BISTCTRL_PASS +#define BF_AUDIOOUT_BISTCTRL_PASS_V(e) BF_AUDIOOUT_BISTCTRL_PASS(BV_AUDIOOUT_BISTCTRL_PASS__##e) +#define BFM_AUDIOOUT_BISTCTRL_PASS_V(v) BM_AUDIOOUT_BISTCTRL_PASS +#define BP_AUDIOOUT_BISTCTRL_DONE 1 +#define BM_AUDIOOUT_BISTCTRL_DONE 0x2 +#define BF_AUDIOOUT_BISTCTRL_DONE(v) (((v) & 0x1) << 1) +#define BFM_AUDIOOUT_BISTCTRL_DONE(v) BM_AUDIOOUT_BISTCTRL_DONE +#define BF_AUDIOOUT_BISTCTRL_DONE_V(e) BF_AUDIOOUT_BISTCTRL_DONE(BV_AUDIOOUT_BISTCTRL_DONE__##e) +#define BFM_AUDIOOUT_BISTCTRL_DONE_V(v) BM_AUDIOOUT_BISTCTRL_DONE +#define BP_AUDIOOUT_BISTCTRL_START 0 +#define BM_AUDIOOUT_BISTCTRL_START 0x1 +#define BF_AUDIOOUT_BISTCTRL_START(v) (((v) & 0x1) << 0) +#define BFM_AUDIOOUT_BISTCTRL_START(v) BM_AUDIOOUT_BISTCTRL_START +#define BF_AUDIOOUT_BISTCTRL_START_V(e) BF_AUDIOOUT_BISTCTRL_START(BV_AUDIOOUT_BISTCTRL_START__##e) +#define BFM_AUDIOOUT_BISTCTRL_START_V(v) BM_AUDIOOUT_BISTCTRL_START + +#define HW_AUDIOOUT_BISTSTAT0 HW(AUDIOOUT_BISTSTAT0) +#define HWA_AUDIOOUT_BISTSTAT0 (0x80048000 + 0xc0) +#define HWT_AUDIOOUT_BISTSTAT0 HWIO_32_RW +#define HWN_AUDIOOUT_BISTSTAT0 AUDIOOUT_BISTSTAT0 +#define HWI_AUDIOOUT_BISTSTAT0 +#define HW_AUDIOOUT_BISTSTAT0_SET HW(AUDIOOUT_BISTSTAT0_SET) +#define HWA_AUDIOOUT_BISTSTAT0_SET (HWA_AUDIOOUT_BISTSTAT0 + 0x4) +#define HWT_AUDIOOUT_BISTSTAT0_SET HWIO_32_WO +#define HWN_AUDIOOUT_BISTSTAT0_SET AUDIOOUT_BISTSTAT0 +#define HWI_AUDIOOUT_BISTSTAT0_SET +#define HW_AUDIOOUT_BISTSTAT0_CLR HW(AUDIOOUT_BISTSTAT0_CLR) +#define HWA_AUDIOOUT_BISTSTAT0_CLR (HWA_AUDIOOUT_BISTSTAT0 + 0x8) +#define HWT_AUDIOOUT_BISTSTAT0_CLR HWIO_32_WO +#define HWN_AUDIOOUT_BISTSTAT0_CLR AUDIOOUT_BISTSTAT0 +#define HWI_AUDIOOUT_BISTSTAT0_CLR +#define HW_AUDIOOUT_BISTSTAT0_TOG HW(AUDIOOUT_BISTSTAT0_TOG) +#define HWA_AUDIOOUT_BISTSTAT0_TOG (HWA_AUDIOOUT_BISTSTAT0 + 0xc) +#define HWT_AUDIOOUT_BISTSTAT0_TOG HWIO_32_WO +#define HWN_AUDIOOUT_BISTSTAT0_TOG AUDIOOUT_BISTSTAT0 +#define HWI_AUDIOOUT_BISTSTAT0_TOG +#define BP_AUDIOOUT_BISTSTAT0_RSVD0 24 +#define BM_AUDIOOUT_BISTSTAT0_RSVD0 0xff000000 +#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v) (((v) & 0xff) << 24) +#define BFM_AUDIOOUT_BISTSTAT0_RSVD0(v) BM_AUDIOOUT_BISTSTAT0_RSVD0 +#define BF_AUDIOOUT_BISTSTAT0_RSVD0_V(e) BF_AUDIOOUT_BISTSTAT0_RSVD0(BV_AUDIOOUT_BISTSTAT0_RSVD0__##e) +#define BFM_AUDIOOUT_BISTSTAT0_RSVD0_V(v) BM_AUDIOOUT_BISTSTAT0_RSVD0 +#define BP_AUDIOOUT_BISTSTAT0_DATA 0 +#define BM_AUDIOOUT_BISTSTAT0_DATA 0xffffff +#define BF_AUDIOOUT_BISTSTAT0_DATA(v) (((v) & 0xffffff) << 0) +#define BFM_AUDIOOUT_BISTSTAT0_DATA(v) BM_AUDIOOUT_BISTSTAT0_DATA +#define BF_AUDIOOUT_BISTSTAT0_DATA_V(e) BF_AUDIOOUT_BISTSTAT0_DATA(BV_AUDIOOUT_BISTSTAT0_DATA__##e) +#define BFM_AUDIOOUT_BISTSTAT0_DATA_V(v) BM_AUDIOOUT_BISTSTAT0_DATA + +#define HW_AUDIOOUT_BISTSTAT1 HW(AUDIOOUT_BISTSTAT1) +#define HWA_AUDIOOUT_BISTSTAT1 (0x80048000 + 0xd0) +#define HWT_AUDIOOUT_BISTSTAT1 HWIO_32_RW +#define HWN_AUDIOOUT_BISTSTAT1 AUDIOOUT_BISTSTAT1 +#define HWI_AUDIOOUT_BISTSTAT1 +#define HW_AUDIOOUT_BISTSTAT1_SET HW(AUDIOOUT_BISTSTAT1_SET) +#define HWA_AUDIOOUT_BISTSTAT1_SET (HWA_AUDIOOUT_BISTSTAT1 + 0x4) +#define HWT_AUDIOOUT_BISTSTAT1_SET HWIO_32_WO +#define HWN_AUDIOOUT_BISTSTAT1_SET AUDIOOUT_BISTSTAT1 +#define HWI_AUDIOOUT_BISTSTAT1_SET +#define HW_AUDIOOUT_BISTSTAT1_CLR HW(AUDIOOUT_BISTSTAT1_CLR) +#define HWA_AUDIOOUT_BISTSTAT1_CLR (HWA_AUDIOOUT_BISTSTAT1 + 0x8) +#define HWT_AUDIOOUT_BISTSTAT1_CLR HWIO_32_WO +#define HWN_AUDIOOUT_BISTSTAT1_CLR AUDIOOUT_BISTSTAT1 +#define HWI_AUDIOOUT_BISTSTAT1_CLR +#define HW_AUDIOOUT_BISTSTAT1_TOG HW(AUDIOOUT_BISTSTAT1_TOG) +#define HWA_AUDIOOUT_BISTSTAT1_TOG (HWA_AUDIOOUT_BISTSTAT1 + 0xc) +#define HWT_AUDIOOUT_BISTSTAT1_TOG HWIO_32_WO +#define HWN_AUDIOOUT_BISTSTAT1_TOG AUDIOOUT_BISTSTAT1 +#define HWI_AUDIOOUT_BISTSTAT1_TOG +#define BP_AUDIOOUT_BISTSTAT1_RSVD1 29 +#define BM_AUDIOOUT_BISTSTAT1_RSVD1 0xe0000000 +#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v) (((v) & 0x7) << 29) +#define BFM_AUDIOOUT_BISTSTAT1_RSVD1(v) BM_AUDIOOUT_BISTSTAT1_RSVD1 +#define BF_AUDIOOUT_BISTSTAT1_RSVD1_V(e) BF_AUDIOOUT_BISTSTAT1_RSVD1(BV_AUDIOOUT_BISTSTAT1_RSVD1__##e) +#define BFM_AUDIOOUT_BISTSTAT1_RSVD1_V(v) BM_AUDIOOUT_BISTSTAT1_RSVD1 +#define BP_AUDIOOUT_BISTSTAT1_STATE 24 +#define BM_AUDIOOUT_BISTSTAT1_STATE 0x1f000000 +#define BF_AUDIOOUT_BISTSTAT1_STATE(v) (((v) & 0x1f) << 24) +#define BFM_AUDIOOUT_BISTSTAT1_STATE(v) BM_AUDIOOUT_BISTSTAT1_STATE +#define BF_AUDIOOUT_BISTSTAT1_STATE_V(e) BF_AUDIOOUT_BISTSTAT1_STATE(BV_AUDIOOUT_BISTSTAT1_STATE__##e) +#define BFM_AUDIOOUT_BISTSTAT1_STATE_V(v) BM_AUDIOOUT_BISTSTAT1_STATE +#define BP_AUDIOOUT_BISTSTAT1_RSVD0 8 +#define BM_AUDIOOUT_BISTSTAT1_RSVD0 0xffff00 +#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v) (((v) & 0xffff) << 8) +#define BFM_AUDIOOUT_BISTSTAT1_RSVD0(v) BM_AUDIOOUT_BISTSTAT1_RSVD0 +#define BF_AUDIOOUT_BISTSTAT1_RSVD0_V(e) BF_AUDIOOUT_BISTSTAT1_RSVD0(BV_AUDIOOUT_BISTSTAT1_RSVD0__##e) +#define BFM_AUDIOOUT_BISTSTAT1_RSVD0_V(v) BM_AUDIOOUT_BISTSTAT1_RSVD0 +#define BP_AUDIOOUT_BISTSTAT1_ADDR 0 +#define BM_AUDIOOUT_BISTSTAT1_ADDR 0xff +#define BF_AUDIOOUT_BISTSTAT1_ADDR(v) (((v) & 0xff) << 0) +#define BFM_AUDIOOUT_BISTSTAT1_ADDR(v) BM_AUDIOOUT_BISTSTAT1_ADDR +#define BF_AUDIOOUT_BISTSTAT1_ADDR_V(e) BF_AUDIOOUT_BISTSTAT1_ADDR(BV_AUDIOOUT_BISTSTAT1_ADDR__##e) +#define BFM_AUDIOOUT_BISTSTAT1_ADDR_V(v) BM_AUDIOOUT_BISTSTAT1_ADDR + +#define HW_AUDIOOUT_ANACLKCTRL HW(AUDIOOUT_ANACLKCTRL) +#define HWA_AUDIOOUT_ANACLKCTRL (0x80048000 + 0xe0) +#define HWT_AUDIOOUT_ANACLKCTRL HWIO_32_RW +#define HWN_AUDIOOUT_ANACLKCTRL AUDIOOUT_ANACLKCTRL +#define HWI_AUDIOOUT_ANACLKCTRL +#define HW_AUDIOOUT_ANACLKCTRL_SET HW(AUDIOOUT_ANACLKCTRL_SET) +#define HWA_AUDIOOUT_ANACLKCTRL_SET (HWA_AUDIOOUT_ANACLKCTRL + 0x4) +#define HWT_AUDIOOUT_ANACLKCTRL_SET HWIO_32_WO +#define HWN_AUDIOOUT_ANACLKCTRL_SET AUDIOOUT_ANACLKCTRL +#define HWI_AUDIOOUT_ANACLKCTRL_SET +#define HW_AUDIOOUT_ANACLKCTRL_CLR HW(AUDIOOUT_ANACLKCTRL_CLR) +#define HWA_AUDIOOUT_ANACLKCTRL_CLR (HWA_AUDIOOUT_ANACLKCTRL + 0x8) +#define HWT_AUDIOOUT_ANACLKCTRL_CLR HWIO_32_WO +#define HWN_AUDIOOUT_ANACLKCTRL_CLR AUDIOOUT_ANACLKCTRL +#define HWI_AUDIOOUT_ANACLKCTRL_CLR +#define HW_AUDIOOUT_ANACLKCTRL_TOG HW(AUDIOOUT_ANACLKCTRL_TOG) +#define HWA_AUDIOOUT_ANACLKCTRL_TOG (HWA_AUDIOOUT_ANACLKCTRL + 0xc) +#define HWT_AUDIOOUT_ANACLKCTRL_TOG HWIO_32_WO +#define HWN_AUDIOOUT_ANACLKCTRL_TOG AUDIOOUT_ANACLKCTRL +#define HWI_AUDIOOUT_ANACLKCTRL_TOG +#define BP_AUDIOOUT_ANACLKCTRL_CLKGATE 31 +#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 +#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_AUDIOOUT_ANACLKCTRL_CLKGATE(v) BM_AUDIOOUT_ANACLKCTRL_CLKGATE +#define BF_AUDIOOUT_ANACLKCTRL_CLKGATE_V(e) BF_AUDIOOUT_ANACLKCTRL_CLKGATE(BV_AUDIOOUT_ANACLKCTRL_CLKGATE__##e) +#define BFM_AUDIOOUT_ANACLKCTRL_CLKGATE_V(v) BM_AUDIOOUT_ANACLKCTRL_CLKGATE +#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3 5 +#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3 0x7fffffe0 +#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v) (((v) & 0x3ffffff) << 5) +#define BFM_AUDIOOUT_ANACLKCTRL_RSRVD3(v) BM_AUDIOOUT_ANACLKCTRL_RSRVD3 +#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3_V(e) BF_AUDIOOUT_ANACLKCTRL_RSRVD3(BV_AUDIOOUT_ANACLKCTRL_RSRVD3__##e) +#define BFM_AUDIOOUT_ANACLKCTRL_RSRVD3_V(v) BM_AUDIOOUT_ANACLKCTRL_RSRVD3 +#define BP_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 4 +#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x10 +#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) (((v) & 0x1) << 4) +#define BFM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(v) BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK +#define BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK_V(e) BF_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK(BV_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK__##e) +#define BFM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK_V(v) BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK +#define BP_AUDIOOUT_ANACLKCTRL_RSRVD2 3 +#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2 0x8 +#define BF_AUDIOOUT_ANACLKCTRL_RSRVD2(v) (((v) & 0x1) << 3) +#define BFM_AUDIOOUT_ANACLKCTRL_RSRVD2(v) BM_AUDIOOUT_ANACLKCTRL_RSRVD2 +#define BF_AUDIOOUT_ANACLKCTRL_RSRVD2_V(e) BF_AUDIOOUT_ANACLKCTRL_RSRVD2(BV_AUDIOOUT_ANACLKCTRL_RSRVD2__##e) +#define BFM_AUDIOOUT_ANACLKCTRL_RSRVD2_V(v) BM_AUDIOOUT_ANACLKCTRL_RSRVD2 +#define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0 +#define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x7 +#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) (((v) & 0x7) << 0) +#define BFM_AUDIOOUT_ANACLKCTRL_DACDIV(v) BM_AUDIOOUT_ANACLKCTRL_DACDIV +#define BF_AUDIOOUT_ANACLKCTRL_DACDIV_V(e) BF_AUDIOOUT_ANACLKCTRL_DACDIV(BV_AUDIOOUT_ANACLKCTRL_DACDIV__##e) +#define BFM_AUDIOOUT_ANACLKCTRL_DACDIV_V(v) BM_AUDIOOUT_ANACLKCTRL_DACDIV + +#define HW_AUDIOOUT_DATA HW(AUDIOOUT_DATA) +#define HWA_AUDIOOUT_DATA (0x80048000 + 0xf0) +#define HWT_AUDIOOUT_DATA HWIO_32_RW +#define HWN_AUDIOOUT_DATA AUDIOOUT_DATA +#define HWI_AUDIOOUT_DATA +#define HW_AUDIOOUT_DATA_SET HW(AUDIOOUT_DATA_SET) +#define HWA_AUDIOOUT_DATA_SET (HWA_AUDIOOUT_DATA + 0x4) +#define HWT_AUDIOOUT_DATA_SET HWIO_32_WO +#define HWN_AUDIOOUT_DATA_SET AUDIOOUT_DATA +#define HWI_AUDIOOUT_DATA_SET +#define HW_AUDIOOUT_DATA_CLR HW(AUDIOOUT_DATA_CLR) +#define HWA_AUDIOOUT_DATA_CLR (HWA_AUDIOOUT_DATA + 0x8) +#define HWT_AUDIOOUT_DATA_CLR HWIO_32_WO +#define HWN_AUDIOOUT_DATA_CLR AUDIOOUT_DATA +#define HWI_AUDIOOUT_DATA_CLR +#define HW_AUDIOOUT_DATA_TOG HW(AUDIOOUT_DATA_TOG) +#define HWA_AUDIOOUT_DATA_TOG (HWA_AUDIOOUT_DATA + 0xc) +#define HWT_AUDIOOUT_DATA_TOG HWIO_32_WO +#define HWN_AUDIOOUT_DATA_TOG AUDIOOUT_DATA +#define HWI_AUDIOOUT_DATA_TOG +#define BP_AUDIOOUT_DATA_HIGH 16 +#define BM_AUDIOOUT_DATA_HIGH 0xffff0000 +#define BF_AUDIOOUT_DATA_HIGH(v) (((v) & 0xffff) << 16) +#define BFM_AUDIOOUT_DATA_HIGH(v) BM_AUDIOOUT_DATA_HIGH +#define BF_AUDIOOUT_DATA_HIGH_V(e) BF_AUDIOOUT_DATA_HIGH(BV_AUDIOOUT_DATA_HIGH__##e) +#define BFM_AUDIOOUT_DATA_HIGH_V(v) BM_AUDIOOUT_DATA_HIGH +#define BP_AUDIOOUT_DATA_LOW 0 +#define BM_AUDIOOUT_DATA_LOW 0xffff +#define BF_AUDIOOUT_DATA_LOW(v) (((v) & 0xffff) << 0) +#define BFM_AUDIOOUT_DATA_LOW(v) BM_AUDIOOUT_DATA_LOW +#define BF_AUDIOOUT_DATA_LOW_V(e) BF_AUDIOOUT_DATA_LOW(BV_AUDIOOUT_DATA_LOW__##e) +#define BFM_AUDIOOUT_DATA_LOW_V(v) BM_AUDIOOUT_DATA_LOW + +#define HW_AUDIOOUT_SPEAKERCTRL HW(AUDIOOUT_SPEAKERCTRL) +#define HWA_AUDIOOUT_SPEAKERCTRL (0x80048000 + 0x100) +#define HWT_AUDIOOUT_SPEAKERCTRL HWIO_32_RW +#define HWN_AUDIOOUT_SPEAKERCTRL AUDIOOUT_SPEAKERCTRL +#define HWI_AUDIOOUT_SPEAKERCTRL +#define HW_AUDIOOUT_SPEAKERCTRL_SET HW(AUDIOOUT_SPEAKERCTRL_SET) +#define HWA_AUDIOOUT_SPEAKERCTRL_SET (HWA_AUDIOOUT_SPEAKERCTRL + 0x4) +#define HWT_AUDIOOUT_SPEAKERCTRL_SET HWIO_32_WO +#define HWN_AUDIOOUT_SPEAKERCTRL_SET AUDIOOUT_SPEAKERCTRL +#define HWI_AUDIOOUT_SPEAKERCTRL_SET +#define HW_AUDIOOUT_SPEAKERCTRL_CLR HW(AUDIOOUT_SPEAKERCTRL_CLR) +#define HWA_AUDIOOUT_SPEAKERCTRL_CLR (HWA_AUDIOOUT_SPEAKERCTRL + 0x8) +#define HWT_AUDIOOUT_SPEAKERCTRL_CLR HWIO_32_WO +#define HWN_AUDIOOUT_SPEAKERCTRL_CLR AUDIOOUT_SPEAKERCTRL +#define HWI_AUDIOOUT_SPEAKERCTRL_CLR +#define HW_AUDIOOUT_SPEAKERCTRL_TOG HW(AUDIOOUT_SPEAKERCTRL_TOG) +#define HWA_AUDIOOUT_SPEAKERCTRL_TOG (HWA_AUDIOOUT_SPEAKERCTRL + 0xc) +#define HWT_AUDIOOUT_SPEAKERCTRL_TOG HWIO_32_WO +#define HWN_AUDIOOUT_SPEAKERCTRL_TOG AUDIOOUT_SPEAKERCTRL +#define HWI_AUDIOOUT_SPEAKERCTRL_TOG +#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2 25 +#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 0xfe000000 +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v) (((v) & 0x7f) << 25) +#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD2(v) BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2_V(e) BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(BV_AUDIOOUT_SPEAKERCTRL_RSRVD2__##e) +#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD2_V(v) BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 +#define BP_AUDIOOUT_SPEAKERCTRL_MUTE 24 +#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x1000000 +#define BF_AUDIOOUT_SPEAKERCTRL_MUTE(v) (((v) & 0x1) << 24) +#define BFM_AUDIOOUT_SPEAKERCTRL_MUTE(v) BM_AUDIOOUT_SPEAKERCTRL_MUTE +#define BF_AUDIOOUT_SPEAKERCTRL_MUTE_V(e) BF_AUDIOOUT_SPEAKERCTRL_MUTE(BV_AUDIOOUT_SPEAKERCTRL_MUTE__##e) +#define BFM_AUDIOOUT_SPEAKERCTRL_MUTE_V(v) BM_AUDIOOUT_SPEAKERCTRL_MUTE +#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ 22 +#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ 0xc00000 +#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v) (((v) & 0x3) << 22) +#define BFM_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v) BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ +#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ_V(e) BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(BV_AUDIOOUT_SPEAKERCTRL_I1_ADJ__##e) +#define BFM_AUDIOOUT_SPEAKERCTRL_I1_ADJ_V(v) BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ +#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 20 +#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 0x300000 +#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v) (((v) & 0x3) << 20) +#define BFM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v) BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ +#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ_V(e) BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(BV_AUDIOOUT_SPEAKERCTRL_IALL_ADJ__##e) +#define BFM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ_V(v) BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ +#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1 16 +#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 0xf0000 +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v) (((v) & 0xf) << 16) +#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD1(v) BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1_V(e) BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(BV_AUDIOOUT_SPEAKERCTRL_RSRVD1__##e) +#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD1_V(v) BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 +#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER 14 +#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER 0xc000 +#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v) (((v) & 0x3) << 14) +#define BFM_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v) BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER +#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER_V(e) BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(BV_AUDIOOUT_SPEAKERCTRL_POSDRIVER__##e) +#define BFM_AUDIOOUT_SPEAKERCTRL_POSDRIVER_V(v) BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER +#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 12 +#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 0x3000 +#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v) (((v) & 0x3) << 12) +#define BFM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v) BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER +#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER_V(e) BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(BV_AUDIOOUT_SPEAKERCTRL_NEGDRIVER__##e) +#define BFM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER_V(v) BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER +#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0 0 +#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 0xfff +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v) (((v) & 0xfff) << 0) +#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD0(v) BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0_V(e) BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(BV_AUDIOOUT_SPEAKERCTRL_RSRVD0__##e) +#define BFM_AUDIOOUT_SPEAKERCTRL_RSRVD0_V(v) BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 + +#define HW_AUDIOOUT_VERSION HW(AUDIOOUT_VERSION) +#define HWA_AUDIOOUT_VERSION (0x80048000 + 0x200) +#define HWT_AUDIOOUT_VERSION HWIO_32_RW +#define HWN_AUDIOOUT_VERSION AUDIOOUT_VERSION +#define HWI_AUDIOOUT_VERSION +#define BP_AUDIOOUT_VERSION_MAJOR 24 +#define BM_AUDIOOUT_VERSION_MAJOR 0xff000000 +#define BF_AUDIOOUT_VERSION_MAJOR(v) (((v) & 0xff) << 24) +#define BFM_AUDIOOUT_VERSION_MAJOR(v) BM_AUDIOOUT_VERSION_MAJOR +#define BF_AUDIOOUT_VERSION_MAJOR_V(e) BF_AUDIOOUT_VERSION_MAJOR(BV_AUDIOOUT_VERSION_MAJOR__##e) +#define BFM_AUDIOOUT_VERSION_MAJOR_V(v) BM_AUDIOOUT_VERSION_MAJOR +#define BP_AUDIOOUT_VERSION_MINOR 16 +#define BM_AUDIOOUT_VERSION_MINOR 0xff0000 +#define BF_AUDIOOUT_VERSION_MINOR(v) (((v) & 0xff) << 16) +#define BFM_AUDIOOUT_VERSION_MINOR(v) BM_AUDIOOUT_VERSION_MINOR +#define BF_AUDIOOUT_VERSION_MINOR_V(e) BF_AUDIOOUT_VERSION_MINOR(BV_AUDIOOUT_VERSION_MINOR__##e) +#define BFM_AUDIOOUT_VERSION_MINOR_V(v) BM_AUDIOOUT_VERSION_MINOR +#define BP_AUDIOOUT_VERSION_STEP 0 +#define BM_AUDIOOUT_VERSION_STEP 0xffff +#define BF_AUDIOOUT_VERSION_STEP(v) (((v) & 0xffff) << 0) +#define BFM_AUDIOOUT_VERSION_STEP(v) BM_AUDIOOUT_VERSION_STEP +#define BF_AUDIOOUT_VERSION_STEP_V(e) BF_AUDIOOUT_VERSION_STEP(BV_AUDIOOUT_VERSION_STEP__##e) +#define BFM_AUDIOOUT_VERSION_STEP_V(v) BM_AUDIOOUT_VERSION_STEP + +#endif /* __HEADERGEN_IMX233_AUDIOOUT_H__*/ diff --git a/firmware/target/arm/imx233/regs/imx233/bch.h b/firmware/target/arm/imx233/regs/imx233/bch.h new file mode 100644 index 0000000000..7b8ad3ade0 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/bch.h @@ -0,0 +1,876 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * imx233 version: 2.4.0 + * imx233 authors: Amaury Pouly + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_IMX233_BCH_H__ +#define __HEADERGEN_IMX233_BCH_H__ + +#define HW_BCH_CTRL HW(BCH_CTRL) +#define HWA_BCH_CTRL (0x8000a000 + 0x0) +#define HWT_BCH_CTRL HWIO_32_RW +#define HWN_BCH_CTRL BCH_CTRL +#define HWI_BCH_CTRL +#define HW_BCH_CTRL_SET HW(BCH_CTRL_SET) +#define HWA_BCH_CTRL_SET (HWA_BCH_CTRL + 0x4) +#define HWT_BCH_CTRL_SET HWIO_32_WO +#define HWN_BCH_CTRL_SET BCH_CTRL +#define HWI_BCH_CTRL_SET +#define HW_BCH_CTRL_CLR HW(BCH_CTRL_CLR) +#define HWA_BCH_CTRL_CLR (HWA_BCH_CTRL + 0x8) +#define HWT_BCH_CTRL_CLR HWIO_32_WO +#define HWN_BCH_CTRL_CLR BCH_CTRL +#define HWI_BCH_CTRL_CLR +#define HW_BCH_CTRL_TOG HW(BCH_CTRL_TOG) +#define HWA_BCH_CTRL_TOG (HWA_BCH_CTRL + 0xc) +#define HWT_BCH_CTRL_TOG HWIO_32_WO +#define HWN_BCH_CTRL_TOG BCH_CTRL +#define HWI_BCH_CTRL_TOG +#define BP_BCH_CTRL_SFTRST 31 +#define BM_BCH_CTRL_SFTRST 0x80000000 +#define BV_BCH_CTRL_SFTRST__RUN 0x0 +#define BV_BCH_CTRL_SFTRST__RESET 0x1 +#define BF_BCH_CTRL_SFTRST(v) (((v) & 0x1) << 31) +#define BFM_BCH_CTRL_SFTRST(v) BM_BCH_CTRL_SFTRST +#define BF_BCH_CTRL_SFTRST_V(e) BF_BCH_CTRL_SFTRST(BV_BCH_CTRL_SFTRST__##e) +#define BFM_BCH_CTRL_SFTRST_V(v) BM_BCH_CTRL_SFTRST +#define BP_BCH_CTRL_CLKGATE 30 +#define BM_BCH_CTRL_CLKGATE 0x40000000 +#define BV_BCH_CTRL_CLKGATE__RUN 0x0 +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 +#define BF_BCH_CTRL_CLKGATE(v) (((v) & 0x1) << 30) +#define BFM_BCH_CTRL_CLKGATE(v) BM_BCH_CTRL_CLKGATE +#define BF_BCH_CTRL_CLKGATE_V(e) BF_BCH_CTRL_CLKGATE(BV_BCH_CTRL_CLKGATE__##e) +#define BFM_BCH_CTRL_CLKGATE_V(v) BM_BCH_CTRL_CLKGATE +#define BP_BCH_CTRL_RSVD5 23 +#define BM_BCH_CTRL_RSVD5 0x3f800000 +#define BF_BCH_CTRL_RSVD5(v) (((v) & 0x7f) << 23) +#define BFM_BCH_CTRL_RSVD5(v) BM_BCH_CTRL_RSVD5 +#define BF_BCH_CTRL_RSVD5_V(e) BF_BCH_CTRL_RSVD5(BV_BCH_CTRL_RSVD5__##e) +#define BFM_BCH_CTRL_RSVD5_V(v) BM_BCH_CTRL_RSVD5 +#define BP_BCH_CTRL_DEBUGSYNDROME 22 +#define BM_BCH_CTRL_DEBUGSYNDROME 0x400000 +#define BF_BCH_CTRL_DEBUGSYNDROME(v) (((v) & 0x1) << 22) +#define BFM_BCH_CTRL_DEBUGSYNDROME(v) BM_BCH_CTRL_DEBUGSYNDROME +#define BF_BCH_CTRL_DEBUGSYNDROME_V(e) BF_BCH_CTRL_DEBUGSYNDROME(BV_BCH_CTRL_DEBUGSYNDROME__##e) +#define BFM_BCH_CTRL_DEBUGSYNDROME_V(v) BM_BCH_CTRL_DEBUGSYNDROME +#define BP_BCH_CTRL_RSVD4 20 +#define BM_BCH_CTRL_RSVD4 0x300000 +#define BF_BCH_CTRL_RSVD4(v) (((v) & 0x3) << 20) +#define BFM_BCH_CTRL_RSVD4(v) BM_BCH_CTRL_RSVD4 +#define BF_BCH_CTRL_RSVD4_V(e) BF_BCH_CTRL_RSVD4(BV_BCH_CTRL_RSVD4__##e) +#define BFM_BCH_CTRL_RSVD4_V(v) BM_BCH_CTRL_RSVD4 +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT 0xc0000 +#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) & 0x3) << 18) +#define BFM_BCH_CTRL_M2M_LAYOUT(v) BM_BCH_CTRL_M2M_LAYOUT +#define BF_BCH_CTRL_M2M_LAYOUT_V(e) BF_BCH_CTRL_M2M_LAYOUT(BV_BCH_CTRL_M2M_LAYOUT__##e) +#define BFM_BCH_CTRL_M2M_LAYOUT_V(v) BM_BCH_CTRL_M2M_LAYOUT +#define BP_BCH_CTRL_M2M_ENCODE 17 +#define BM_BCH_CTRL_M2M_ENCODE 0x20000 +#define BF_BCH_CTRL_M2M_ENCODE(v) (((v) & 0x1) << 17) +#define BFM_BCH_CTRL_M2M_ENCODE(v) BM_BCH_CTRL_M2M_ENCODE +#define BF_BCH_CTRL_M2M_ENCODE_V(e) BF_BCH_CTRL_M2M_ENCODE(BV_BCH_CTRL_M2M_ENCODE__##e) +#define BFM_BCH_CTRL_M2M_ENCODE_V(v) BM_BCH_CTRL_M2M_ENCODE +#define BP_BCH_CTRL_M2M_ENABLE 16 +#define BM_BCH_CTRL_M2M_ENABLE 0x10000 +#define BF_BCH_CTRL_M2M_ENABLE(v) (((v) & 0x1) << 16) +#define BFM_BCH_CTRL_M2M_ENABLE(v) BM_BCH_CTRL_M2M_ENABLE +#define BF_BCH_CTRL_M2M_ENABLE_V(e) BF_BCH_CTRL_M2M_ENABLE(BV_BCH_CTRL_M2M_ENABLE__##e) +#define BFM_BCH_CTRL_M2M_ENABLE_V(v) BM_BCH_CTRL_M2M_ENABLE +#define BP_BCH_CTRL_RSVD3 11 +#define BM_BCH_CTRL_RSVD3 0xf800 +#define BF_BCH_CTRL_RSVD3(v) (((v) & 0x1f) << 11) +#define BFM_BCH_CTRL_RSVD3(v) BM_BCH_CTRL_RSVD3 +#define BF_BCH_CTRL_RSVD3_V(e) BF_BCH_CTRL_RSVD3(BV_BCH_CTRL_RSVD3__##e) +#define BFM_BCH_CTRL_RSVD3_V(v) BM_BCH_CTRL_RSVD3 +#define BP_BCH_CTRL_DEBUG_STALL_IRQ_EN 10 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x400 +#define BF_BCH_CTRL_DEBUG_STALL_IRQ_EN(v) (((v) & 0x1) << 10) +#define BFM_BCH_CTRL_DEBUG_STALL_IRQ_EN(v) BM_BCH_CTRL_DEBUG_STALL_IRQ_EN +#define BF_BCH_CTRL_DEBUG_STALL_IRQ_EN_V(e) BF_BCH_CTRL_DEBUG_STALL_IRQ_EN(BV_BCH_CTRL_DEBUG_STALL_IRQ_EN__##e) +#define BFM_BCH_CTRL_DEBUG_STALL_IRQ_EN_V(v) BM_BCH_CTRL_DEBUG_STALL_IRQ_EN +#define BP_BCH_CTRL_RSVD2 9 +#define BM_BCH_CTRL_RSVD2 0x200 +#define BF_BCH_CTRL_RSVD2(v) (((v) & 0x1) << 9) +#define BFM_BCH_CTRL_RSVD2(v) BM_BCH_CTRL_RSVD2 +#define BF_BCH_CTRL_RSVD2_V(e) BF_BCH_CTRL_RSVD2(BV_BCH_CTRL_RSVD2__##e) +#define BFM_BCH_CTRL_RSVD2_V(v) BM_BCH_CTRL_RSVD2 +#define BP_BCH_CTRL_COMPLETE_IRQ_EN 8 +#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x100 +#define BF_BCH_CTRL_COMPLETE_IRQ_EN(v) (((v) & 0x1) << 8) +#define BFM_BCH_CTRL_COMPLETE_IRQ_EN(v) BM_BCH_CTRL_COMPLETE_IRQ_EN +#define BF_BCH_CTRL_COMPLETE_IRQ_EN_V(e) BF_BCH_CTRL_COMPLETE_IRQ_EN(BV_BCH_CTRL_COMPLETE_IRQ_EN__##e) +#define BFM_BCH_CTRL_COMPLETE_IRQ_EN_V(v) BM_BCH_CTRL_COMPLETE_IRQ_EN +#define BP_BCH_CTRL_RSVD1 4 +#define BM_BCH_CTRL_RSVD1 0xf0 +#define BF_BCH_CTRL_RSVD1(v) (((v) & 0xf) << 4) +#define BFM_BCH_CTRL_RSVD1(v) BM_BCH_CTRL_RSVD1 +#define BF_BCH_CTRL_RSVD1_V(e) BF_BCH_CTRL_RSVD1(BV_BCH_CTRL_RSVD1__##e) +#define BFM_BCH_CTRL_RSVD1_V(v) BM_BCH_CTRL_RSVD1 +#define BP_BCH_CTRL_BM_ERROR_IRQ 3 +#define BM_BCH_CTRL_BM_ERROR_IRQ 0x8 +#define BF_BCH_CTRL_BM_ERROR_IRQ(v) (((v) & 0x1) << 3) +#define BFM_BCH_CTRL_BM_ERROR_IRQ(v) BM_BCH_CTRL_BM_ERROR_IRQ +#define BF_BCH_CTRL_BM_ERROR_IRQ_V(e) BF_BCH_CTRL_BM_ERROR_IRQ(BV_BCH_CTRL_BM_ERROR_IRQ__##e) +#define BFM_BCH_CTRL_BM_ERROR_IRQ_V(v) BM_BCH_CTRL_BM_ERROR_IRQ +#define BP_BCH_CTRL_DEBUG_STALL_IRQ 2 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x4 +#define BF_BCH_CTRL_DEBUG_STALL_IRQ(v) (((v) & 0x1) << 2) +#define BFM_BCH_CTRL_DEBUG_STALL_IRQ(v) BM_BCH_CTRL_DEBUG_STALL_IRQ +#define BF_BCH_CTRL_DEBUG_STALL_IRQ_V(e) BF_BCH_CTRL_DEBUG_STALL_IRQ(BV_BCH_CTRL_DEBUG_STALL_IRQ__##e) +#define BFM_BCH_CTRL_DEBUG_STALL_IRQ_V(v) BM_BCH_CTRL_DEBUG_STALL_IRQ +#define BP_BCH_CTRL_RSVD0 1 +#define BM_BCH_CTRL_RSVD0 0x2 +#define BF_BCH_CTRL_RSVD0(v) (((v) & 0x1) << 1) +#define BFM_BCH_CTRL_RSVD0(v) BM_BCH_CTRL_RSVD0 +#define BF_BCH_CTRL_RSVD0_V(e) BF_BCH_CTRL_RSVD0(BV_BCH_CTRL_RSVD0__##e) +#define BFM_BCH_CTRL_RSVD0_V(v) BM_BCH_CTRL_RSVD0 +#define BP_BCH_CTRL_COMPLETE_IRQ 0 +#define BM_BCH_CTRL_COMPLETE_IRQ 0x1 +#define BF_BCH_CTRL_COMPLETE_IRQ(v) (((v) & 0x1) << 0) +#define BFM_BCH_CTRL_COMPLETE_IRQ(v) BM_BCH_CTRL_COMPLETE_IRQ +#define BF_BCH_CTRL_COMPLETE_IRQ_V(e) BF_BCH_CTRL_COMPLETE_IRQ(BV_BCH_CTRL_COMPLETE_IRQ__##e) +#define BFM_BCH_CTRL_COMPLETE_IRQ_V(v) BM_BCH_CTRL_COMPLETE_IRQ + +#define HW_BCH_STATUS0 HW(BCH_STATUS0) +#define HWA_BCH_STATUS0 (0x8000a000 + 0x10) +#define HWT_BCH_STATUS0 HWIO_32_RW +#define HWN_BCH_STATUS0 BCH_STATUS0 +#define HWI_BCH_STATUS0 +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE 0xfff00000 +#define BF_BCH_STATUS0_HANDLE(v) (((v) & 0xfff) << 20) +#define BFM_BCH_STATUS0_HANDLE(v) BM_BCH_STATUS0_HANDLE +#define BF_BCH_STATUS0_HANDLE_V(e) BF_BCH_STATUS0_HANDLE(BV_BCH_STATUS0_HANDLE__##e) +#define BFM_BCH_STATUS0_HANDLE_V(v) BM_BCH_STATUS0_HANDLE +#define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE 0xf0000 +#define BF_BCH_STATUS0_COMPLETED_CE(v) (((v) & 0xf) << 16) +#define BFM_BCH_STATUS0_COMPLETED_CE(v) BM_BCH_STATUS0_COMPLETED_CE +#define BF_BCH_STATUS0_COMPLETED_CE_V(e) BF_BCH_STATUS0_COMPLETED_CE(BV_BCH_STATUS0_COMPLETED_CE__##e) +#define BFM_BCH_STATUS0_COMPLETED_CE_V(v) BM_BCH_STATUS0_COMPLETED_CE +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 0xff00 +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x0 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x1 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x2 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x3 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x4 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xfe +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xff +#define BF_BCH_STATUS0_STATUS_BLK0(v) (((v) & 0xff) << 8) +#define BFM_BCH_STATUS0_STATUS_BLK0(v) BM_BCH_STATUS0_STATUS_BLK0 +#define BF_BCH_STATUS0_STATUS_BLK0_V(e) BF_BCH_STATUS0_STATUS_BLK0(BV_BCH_STATUS0_STATUS_BLK0__##e) +#define BFM_BCH_STATUS0_STATUS_BLK0_V(v) BM_BCH_STATUS0_STATUS_BLK0 +#define BP_BCH_STATUS0_RSVD1 5 +#define BM_BCH_STATUS0_RSVD1 0xe0 +#define BF_BCH_STATUS0_RSVD1(v) (((v) & 0x7) << 5) +#define BFM_BCH_STATUS0_RSVD1(v) BM_BCH_STATUS0_RSVD1 +#define BF_BCH_STATUS0_RSVD1_V(e) BF_BCH_STATUS0_RSVD1(BV_BCH_STATUS0_RSVD1__##e) +#define BFM_BCH_STATUS0_RSVD1_V(v) BM_BCH_STATUS0_RSVD1 +#define BP_BCH_STATUS0_ALLONES 4 +#define BM_BCH_STATUS0_ALLONES 0x10 +#define BF_BCH_STATUS0_ALLONES(v) (((v) & 0x1) << 4) +#define BFM_BCH_STATUS0_ALLONES(v) BM_BCH_STATUS0_ALLONES +#define BF_BCH_STATUS0_ALLONES_V(e) BF_BCH_STATUS0_ALLONES(BV_BCH_STATUS0_ALLONES__##e) +#define BFM_BCH_STATUS0_ALLONES_V(v) BM_BCH_STATUS0_ALLONES +#define BP_BCH_STATUS0_CORRECTED 3 +#define BM_BCH_STATUS0_CORRECTED 0x8 +#define BF_BCH_STATUS0_CORRECTED(v) (((v) & 0x1) << 3) +#define BFM_BCH_STATUS0_CORRECTED(v) BM_BCH_STATUS0_CORRECTED +#define BF_BCH_STATUS0_CORRECTED_V(e) BF_BCH_STATUS0_CORRECTED(BV_BCH_STATUS0_CORRECTED__##e) +#define BFM_BCH_STATUS0_CORRECTED_V(v) BM_BCH_STATUS0_CORRECTED +#define BP_BCH_STATUS0_UNCORRECTABLE 2 +#define BM_BCH_STATUS0_UNCORRECTABLE 0x4 +#define BF_BCH_STATUS0_UNCORRECTABLE(v) (((v) & 0x1) << 2) +#define BFM_BCH_STATUS0_UNCORRECTABLE(v) BM_BCH_STATUS0_UNCORRECTABLE +#define BF_BCH_STATUS0_UNCORRECTABLE_V(e) BF_BCH_STATUS0_UNCORRECTABLE(BV_BCH_STATUS0_UNCORRECTABLE__##e) +#define BFM_BCH_STATUS0_UNCORRECTABLE_V(v) BM_BCH_STATUS0_UNCORRECTABLE +#define BP_BCH_STATUS0_RSVD0 0 +#define BM_BCH_STATUS0_RSVD0 0x3 +#define BF_BCH_STATUS0_RSVD0(v) (((v) & 0x3) << 0) +#define BFM_BCH_STATUS0_RSVD0(v) BM_BCH_STATUS0_RSVD0 +#define BF_BCH_STATUS0_RSVD0_V(e) BF_BCH_STATUS0_RSVD0(BV_BCH_STATUS0_RSVD0__##e) +#define BFM_BCH_STATUS0_RSVD0_V(v) BM_BCH_STATUS0_RSVD0 + +#define HW_BCH_MODE HW(BCH_MODE) +#define HWA_BCH_MODE (0x8000a000 + 0x20) +#define HWT_BCH_MODE HWIO_32_RW +#define HWN_BCH_MODE BCH_MODE +#define HWI_BCH_MODE +#define BP_BCH_MODE_RSVD 8 +#define BM_BCH_MODE_RSVD 0xffffff00 +#define BF_BCH_MODE_RSVD(v) (((v) & 0xffffff) << 8) +#define BFM_BCH_MODE_RSVD(v) BM_BCH_MODE_RSVD +#define BF_BCH_MODE_RSVD_V(e) BF_BCH_MODE_RSVD(BV_BCH_MODE_RSVD__##e) +#define BFM_BCH_MODE_RSVD_V(v) BM_BCH_MODE_RSVD +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD 0xff +#define BF_BCH_MODE_ERASE_THRESHOLD(v) (((v) & 0xff) << 0) +#define BFM_BCH_MODE_ERASE_THRESHOLD(v) BM_BCH_MODE_ERASE_THRESHOLD +#define BF_BCH_MODE_ERASE_THRESHOLD_V(e) BF_BCH_MODE_ERASE_THRESHOLD(BV_BCH_MODE_ERASE_THRESHOLD__##e) +#define BFM_BCH_MODE_ERASE_THRESHOLD_V(v) BM_BCH_MODE_ERASE_THRESHOLD + +#define HW_BCH_ENCODEPTR HW(BCH_ENCODEPTR) +#define HWA_BCH_ENCODEPTR (0x8000a000 + 0x30) +#define HWT_BCH_ENCODEPTR HWIO_32_RW +#define HWN_BCH_ENCODEPTR BCH_ENCODEPTR +#define HWI_BCH_ENCODEPTR +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xffffffff +#define BF_BCH_ENCODEPTR_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_BCH_ENCODEPTR_ADDR(v) BM_BCH_ENCODEPTR_ADDR +#define BF_BCH_ENCODEPTR_ADDR_V(e) BF_BCH_ENCODEPTR_ADDR(BV_BCH_ENCODEPTR_ADDR__##e) +#define BFM_BCH_ENCODEPTR_ADDR_V(v) BM_BCH_ENCODEPTR_ADDR + +#define HW_BCH_DATAPTR HW(BCH_DATAPTR) +#define HWA_BCH_DATAPTR (0x8000a000 + 0x40) +#define HWT_BCH_DATAPTR HWIO_32_RW +#define HWN_BCH_DATAPTR BCH_DATAPTR +#define HWI_BCH_DATAPTR +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xffffffff +#define BF_BCH_DATAPTR_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_BCH_DATAPTR_ADDR(v) BM_BCH_DATAPTR_ADDR +#define BF_BCH_DATAPTR_ADDR_V(e) BF_BCH_DATAPTR_ADDR(BV_BCH_DATAPTR_ADDR__##e) +#define BFM_BCH_DATAPTR_ADDR_V(v) BM_BCH_DATAPTR_ADDR + +#define HW_BCH_METAPTR HW(BCH_METAPTR) +#define HWA_BCH_METAPTR (0x8000a000 + 0x50) +#define HWT_BCH_METAPTR HWIO_32_RW +#define HWN_BCH_METAPTR BCH_METAPTR +#define HWI_BCH_METAPTR +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xffffffff +#define BF_BCH_METAPTR_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_BCH_METAPTR_ADDR(v) BM_BCH_METAPTR_ADDR +#define BF_BCH_METAPTR_ADDR_V(e) BF_BCH_METAPTR_ADDR(BV_BCH_METAPTR_ADDR__##e) +#define BFM_BCH_METAPTR_ADDR_V(v) BM_BCH_METAPTR_ADDR + +#define HW_BCH_LAYOUTSELECT HW(BCH_LAYOUTSELECT) +#define HWA_BCH_LAYOUTSELECT (0x8000a000 + 0x70) +#define HWT_BCH_LAYOUTSELECT HWIO_32_RW +#define HWN_BCH_LAYOUTSELECT BCH_LAYOUTSELECT +#define HWI_BCH_LAYOUTSELECT +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xc0000000 +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) (((v) & 0x3) << 30) +#define BFM_BCH_LAYOUTSELECT_CS15_SELECT(v) BM_BCH_LAYOUTSELECT_CS15_SELECT +#define BF_BCH_LAYOUTSELECT_CS15_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS15_SELECT(BV_BCH_LAYOUTSELECT_CS15_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS15_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS15_SELECT +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) (((v) & 0x3) << 28) +#define BFM_BCH_LAYOUTSELECT_CS14_SELECT(v) BM_BCH_LAYOUTSELECT_CS14_SELECT +#define BF_BCH_LAYOUTSELECT_CS14_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS14_SELECT(BV_BCH_LAYOUTSELECT_CS14_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS14_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS14_SELECT +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0xc000000 +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) (((v) & 0x3) << 26) +#define BFM_BCH_LAYOUTSELECT_CS13_SELECT(v) BM_BCH_LAYOUTSELECT_CS13_SELECT +#define BF_BCH_LAYOUTSELECT_CS13_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS13_SELECT(BV_BCH_LAYOUTSELECT_CS13_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS13_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS13_SELECT +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x3000000 +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) (((v) & 0x3) << 24) +#define BFM_BCH_LAYOUTSELECT_CS12_SELECT(v) BM_BCH_LAYOUTSELECT_CS12_SELECT +#define BF_BCH_LAYOUTSELECT_CS12_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS12_SELECT(BV_BCH_LAYOUTSELECT_CS12_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS12_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS12_SELECT +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0xc00000 +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) (((v) & 0x3) << 22) +#define BFM_BCH_LAYOUTSELECT_CS11_SELECT(v) BM_BCH_LAYOUTSELECT_CS11_SELECT +#define BF_BCH_LAYOUTSELECT_CS11_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS11_SELECT(BV_BCH_LAYOUTSELECT_CS11_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS11_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS11_SELECT +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x300000 +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) (((v) & 0x3) << 20) +#define BFM_BCH_LAYOUTSELECT_CS10_SELECT(v) BM_BCH_LAYOUTSELECT_CS10_SELECT +#define BF_BCH_LAYOUTSELECT_CS10_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS10_SELECT(BV_BCH_LAYOUTSELECT_CS10_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS10_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS10_SELECT +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0xc0000 +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) (((v) & 0x3) << 18) +#define BFM_BCH_LAYOUTSELECT_CS9_SELECT(v) BM_BCH_LAYOUTSELECT_CS9_SELECT +#define BF_BCH_LAYOUTSELECT_CS9_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS9_SELECT(BV_BCH_LAYOUTSELECT_CS9_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS9_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS9_SELECT +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x30000 +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) (((v) & 0x3) << 16) +#define BFM_BCH_LAYOUTSELECT_CS8_SELECT(v) BM_BCH_LAYOUTSELECT_CS8_SELECT +#define BF_BCH_LAYOUTSELECT_CS8_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS8_SELECT(BV_BCH_LAYOUTSELECT_CS8_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS8_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS8_SELECT +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0xc000 +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) (((v) & 0x3) << 14) +#define BFM_BCH_LAYOUTSELECT_CS7_SELECT(v) BM_BCH_LAYOUTSELECT_CS7_SELECT +#define BF_BCH_LAYOUTSELECT_CS7_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS7_SELECT(BV_BCH_LAYOUTSELECT_CS7_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS7_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS7_SELECT +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x3000 +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) (((v) & 0x3) << 12) +#define BFM_BCH_LAYOUTSELECT_CS6_SELECT(v) BM_BCH_LAYOUTSELECT_CS6_SELECT +#define BF_BCH_LAYOUTSELECT_CS6_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS6_SELECT(BV_BCH_LAYOUTSELECT_CS6_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS6_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS6_SELECT +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0xc00 +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) (((v) & 0x3) << 10) +#define BFM_BCH_LAYOUTSELECT_CS5_SELECT(v) BM_BCH_LAYOUTSELECT_CS5_SELECT +#define BF_BCH_LAYOUTSELECT_CS5_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS5_SELECT(BV_BCH_LAYOUTSELECT_CS5_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS5_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS5_SELECT +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x300 +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) (((v) & 0x3) << 8) +#define BFM_BCH_LAYOUTSELECT_CS4_SELECT(v) BM_BCH_LAYOUTSELECT_CS4_SELECT +#define BF_BCH_LAYOUTSELECT_CS4_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS4_SELECT(BV_BCH_LAYOUTSELECT_CS4_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS4_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS4_SELECT +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0xc0 +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) (((v) & 0x3) << 6) +#define BFM_BCH_LAYOUTSELECT_CS3_SELECT(v) BM_BCH_LAYOUTSELECT_CS3_SELECT +#define BF_BCH_LAYOUTSELECT_CS3_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS3_SELECT(BV_BCH_LAYOUTSELECT_CS3_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS3_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS3_SELECT +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x30 +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) (((v) & 0x3) << 4) +#define BFM_BCH_LAYOUTSELECT_CS2_SELECT(v) BM_BCH_LAYOUTSELECT_CS2_SELECT +#define BF_BCH_LAYOUTSELECT_CS2_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS2_SELECT(BV_BCH_LAYOUTSELECT_CS2_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS2_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS2_SELECT +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0xc +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) (((v) & 0x3) << 2) +#define BFM_BCH_LAYOUTSELECT_CS1_SELECT(v) BM_BCH_LAYOUTSELECT_CS1_SELECT +#define BF_BCH_LAYOUTSELECT_CS1_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS1_SELECT(BV_BCH_LAYOUTSELECT_CS1_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS1_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS1_SELECT +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x3 +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) (((v) & 0x3) << 0) +#define BFM_BCH_LAYOUTSELECT_CS0_SELECT(v) BM_BCH_LAYOUTSELECT_CS0_SELECT +#define BF_BCH_LAYOUTSELECT_CS0_SELECT_V(e) BF_BCH_LAYOUTSELECT_CS0_SELECT(BV_BCH_LAYOUTSELECT_CS0_SELECT__##e) +#define BFM_BCH_LAYOUTSELECT_CS0_SELECT_V(v) BM_BCH_LAYOUTSELECT_CS0_SELECT + +#define HW_BCH_FLASH0LAYOUT0 HW(BCH_FLASH0LAYOUT0) +#define HWA_BCH_FLASH0LAYOUT0 (0x8000a000 + 0x80) +#define HWT_BCH_FLASH0LAYOUT0 HWIO_32_RW +#define HWN_BCH_FLASH0LAYOUT0 BCH_FLASH0LAYOUT0 +#define HWI_BCH_FLASH0LAYOUT0 +#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xff000000 +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) (((v) & 0xff) << 24) +#define BFM_BCH_FLASH0LAYOUT0_NBLOCKS(v) BM_BCH_FLASH0LAYOUT0_NBLOCKS +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS_V(e) BF_BCH_FLASH0LAYOUT0_NBLOCKS(BV_BCH_FLASH0LAYOUT0_NBLOCKS__##e) +#define BFM_BCH_FLASH0LAYOUT0_NBLOCKS_V(v) BM_BCH_FLASH0LAYOUT0_NBLOCKS +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0xff0000 +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) (((v) & 0xff) << 16) +#define BFM_BCH_FLASH0LAYOUT0_META_SIZE(v) BM_BCH_FLASH0LAYOUT0_META_SIZE +#define BF_BCH_FLASH0LAYOUT0_META_SIZE_V(e) BF_BCH_FLASH0LAYOUT0_META_SIZE(BV_BCH_FLASH0LAYOUT0_META_SIZE__##e) +#define BFM_BCH_FLASH0LAYOUT0_META_SIZE_V(v) BM_BCH_FLASH0LAYOUT0_META_SIZE +#define BP_BCH_FLASH0LAYOUT0_ECC0 12 +#define BM_BCH_FLASH0LAYOUT0_ECC0 0xf000 +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xa +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) (((v) & 0xf) << 12) +#define BFM_BCH_FLASH0LAYOUT0_ECC0(v) BM_BCH_FLASH0LAYOUT0_ECC0 +#define BF_BCH_FLASH0LAYOUT0_ECC0_V(e) BF_BCH_FLASH0LAYOUT0_ECC0(BV_BCH_FLASH0LAYOUT0_ECC0__##e) +#define BFM_BCH_FLASH0LAYOUT0_ECC0_V(v) BM_BCH_FLASH0LAYOUT0_ECC0 +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0xfff +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) BM_BCH_FLASH0LAYOUT0_DATA0_SIZE +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE_V(e) BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(BV_BCH_FLASH0LAYOUT0_DATA0_SIZE__##e) +#define BFM_BCH_FLASH0LAYOUT0_DATA0_SIZE_V(v) BM_BCH_FLASH0LAYOUT0_DATA0_SIZE + +#define HW_BCH_FLASH0LAYOUT1 HW(BCH_FLASH0LAYOUT1) +#define HWA_BCH_FLASH0LAYOUT1 (0x8000a000 + 0x90) +#define HWT_BCH_FLASH0LAYOUT1 HWIO_32_RW +#define HWN_BCH_FLASH0LAYOUT1 BCH_FLASH0LAYOUT1 +#define HWI_BCH_FLASH0LAYOUT1 +#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xffff0000 +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) (((v) & 0xffff) << 16) +#define BFM_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) BM_BCH_FLASH0LAYOUT1_PAGE_SIZE +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE_V(e) BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(BV_BCH_FLASH0LAYOUT1_PAGE_SIZE__##e) +#define BFM_BCH_FLASH0LAYOUT1_PAGE_SIZE_V(v) BM_BCH_FLASH0LAYOUT1_PAGE_SIZE +#define BP_BCH_FLASH0LAYOUT1_ECCN 12 +#define BM_BCH_FLASH0LAYOUT1_ECCN 0xf000 +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xa +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) (((v) & 0xf) << 12) +#define BFM_BCH_FLASH0LAYOUT1_ECCN(v) BM_BCH_FLASH0LAYOUT1_ECCN +#define BF_BCH_FLASH0LAYOUT1_ECCN_V(e) BF_BCH_FLASH0LAYOUT1_ECCN(BV_BCH_FLASH0LAYOUT1_ECCN__##e) +#define BFM_BCH_FLASH0LAYOUT1_ECCN_V(v) BM_BCH_FLASH0LAYOUT1_ECCN +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0xfff +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) BM_BCH_FLASH0LAYOUT1_DATAN_SIZE +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE_V(e) BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(BV_BCH_FLASH0LAYOUT1_DATAN_SIZE__##e) +#define BFM_BCH_FLASH0LAYOUT1_DATAN_SIZE_V(v) BM_BCH_FLASH0LAYOUT1_DATAN_SIZE + +#define HW_BCH_FLASH1LAYOUT0 HW(BCH_FLASH1LAYOUT0) +#define HWA_BCH_FLASH1LAYOUT0 (0x8000a000 + 0xa0) +#define HWT_BCH_FLASH1LAYOUT0 HWIO_32_RW +#define HWN_BCH_FLASH1LAYOUT0 BCH_FLASH1LAYOUT0 +#define HWI_BCH_FLASH1LAYOUT0 +#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xff000000 +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) (((v) & 0xff) << 24) +#define BFM_BCH_FLASH1LAYOUT0_NBLOCKS(v) BM_BCH_FLASH1LAYOUT0_NBLOCKS +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS_V(e) BF_BCH_FLASH1LAYOUT0_NBLOCKS(BV_BCH_FLASH1LAYOUT0_NBLOCKS__##e) +#define BFM_BCH_FLASH1LAYOUT0_NBLOCKS_V(v) BM_BCH_FLASH1LAYOUT0_NBLOCKS +#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0xff0000 +#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) (((v) & 0xff) << 16) +#define BFM_BCH_FLASH1LAYOUT0_META_SIZE(v) BM_BCH_FLASH1LAYOUT0_META_SIZE +#define BF_BCH_FLASH1LAYOUT0_META_SIZE_V(e) BF_BCH_FLASH1LAYOUT0_META_SIZE(BV_BCH_FLASH1LAYOUT0_META_SIZE__##e) +#define BFM_BCH_FLASH1LAYOUT0_META_SIZE_V(v) BM_BCH_FLASH1LAYOUT0_META_SIZE +#define BP_BCH_FLASH1LAYOUT0_ECC0 12 +#define BM_BCH_FLASH1LAYOUT0_ECC0 0xf000 +#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xa +#define BF_BCH_FLASH1LAYOUT0_ECC0(v) (((v) & 0xf) << 12) +#define BFM_BCH_FLASH1LAYOUT0_ECC0(v) BM_BCH_FLASH1LAYOUT0_ECC0 +#define BF_BCH_FLASH1LAYOUT0_ECC0_V(e) BF_BCH_FLASH1LAYOUT0_ECC0(BV_BCH_FLASH1LAYOUT0_ECC0__##e) +#define BFM_BCH_FLASH1LAYOUT0_ECC0_V(v) BM_BCH_FLASH1LAYOUT0_ECC0 +#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0xfff +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) BM_BCH_FLASH1LAYOUT0_DATA0_SIZE +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE_V(e) BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(BV_BCH_FLASH1LAYOUT0_DATA0_SIZE__##e) +#define BFM_BCH_FLASH1LAYOUT0_DATA0_SIZE_V(v) BM_BCH_FLASH1LAYOUT0_DATA0_SIZE + +#define HW_BCH_FLASH1LAYOUT1 HW(BCH_FLASH1LAYOUT1) +#define HWA_BCH_FLASH1LAYOUT1 (0x8000a000 + 0xb0) +#define HWT_BCH_FLASH1LAYOUT1 HWIO_32_RW +#define HWN_BCH_FLASH1LAYOUT1 BCH_FLASH1LAYOUT1 +#define HWI_BCH_FLASH1LAYOUT1 +#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xffff0000 +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) (((v) & 0xffff) << 16) +#define BFM_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) BM_BCH_FLASH1LAYOUT1_PAGE_SIZE +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE_V(e) BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(BV_BCH_FLASH1LAYOUT1_PAGE_SIZE__##e) +#define BFM_BCH_FLASH1LAYOUT1_PAGE_SIZE_V(v) BM_BCH_FLASH1LAYOUT1_PAGE_SIZE +#define BP_BCH_FLASH1LAYOUT1_ECCN 12 +#define BM_BCH_FLASH1LAYOUT1_ECCN 0xf000 +#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xa +#define BF_BCH_FLASH1LAYOUT1_ECCN(v) (((v) & 0xf) << 12) +#define BFM_BCH_FLASH1LAYOUT1_ECCN(v) BM_BCH_FLASH1LAYOUT1_ECCN +#define BF_BCH_FLASH1LAYOUT1_ECCN_V(e) BF_BCH_FLASH1LAYOUT1_ECCN(BV_BCH_FLASH1LAYOUT1_ECCN__##e) +#define BFM_BCH_FLASH1LAYOUT1_ECCN_V(v) BM_BCH_FLASH1LAYOUT1_ECCN +#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0xfff +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) BM_BCH_FLASH1LAYOUT1_DATAN_SIZE +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE_V(e) BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(BV_BCH_FLASH1LAYOUT1_DATAN_SIZE__##e) +#define BFM_BCH_FLASH1LAYOUT1_DATAN_SIZE_V(v) BM_BCH_FLASH1LAYOUT1_DATAN_SIZE + +#define HW_BCH_FLASH2LAYOUT0 HW(BCH_FLASH2LAYOUT0) +#define HWA_BCH_FLASH2LAYOUT0 (0x8000a000 + 0xc0) +#define HWT_BCH_FLASH2LAYOUT0 HWIO_32_RW +#define HWN_BCH_FLASH2LAYOUT0 BCH_FLASH2LAYOUT0 +#define HWI_BCH_FLASH2LAYOUT0 +#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xff000000 +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) (((v) & 0xff) << 24) +#define BFM_BCH_FLASH2LAYOUT0_NBLOCKS(v) BM_BCH_FLASH2LAYOUT0_NBLOCKS +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS_V(e) BF_BCH_FLASH2LAYOUT0_NBLOCKS(BV_BCH_FLASH2LAYOUT0_NBLOCKS__##e) +#define BFM_BCH_FLASH2LAYOUT0_NBLOCKS_V(v) BM_BCH_FLASH2LAYOUT0_NBLOCKS +#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0xff0000 +#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) (((v) & 0xff) << 16) +#define BFM_BCH_FLASH2LAYOUT0_META_SIZE(v) BM_BCH_FLASH2LAYOUT0_META_SIZE +#define BF_BCH_FLASH2LAYOUT0_META_SIZE_V(e) BF_BCH_FLASH2LAYOUT0_META_SIZE(BV_BCH_FLASH2LAYOUT0_META_SIZE__##e) +#define BFM_BCH_FLASH2LAYOUT0_META_SIZE_V(v) BM_BCH_FLASH2LAYOUT0_META_SIZE +#define BP_BCH_FLASH2LAYOUT0_ECC0 12 +#define BM_BCH_FLASH2LAYOUT0_ECC0 0xf000 +#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xa +#define BF_BCH_FLASH2LAYOUT0_ECC0(v) (((v) & 0xf) << 12) +#define BFM_BCH_FLASH2LAYOUT0_ECC0(v) BM_BCH_FLASH2LAYOUT0_ECC0 +#define BF_BCH_FLASH2LAYOUT0_ECC0_V(e) BF_BCH_FLASH2LAYOUT0_ECC0(BV_BCH_FLASH2LAYOUT0_ECC0__##e) +#define BFM_BCH_FLASH2LAYOUT0_ECC0_V(v) BM_BCH_FLASH2LAYOUT0_ECC0 +#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0xfff +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) BM_BCH_FLASH2LAYOUT0_DATA0_SIZE +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE_V(e) BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(BV_BCH_FLASH2LAYOUT0_DATA0_SIZE__##e) +#define BFM_BCH_FLASH2LAYOUT0_DATA0_SIZE_V(v) BM_BCH_FLASH2LAYOUT0_DATA0_SIZE + +#define HW_BCH_FLASH2LAYOUT1 HW(BCH_FLASH2LAYOUT1) +#define HWA_BCH_FLASH2LAYOUT1 (0x8000a000 + 0xd0) +#define HWT_BCH_FLASH2LAYOUT1 HWIO_32_RW +#define HWN_BCH_FLASH2LAYOUT1 BCH_FLASH2LAYOUT1 +#define HWI_BCH_FLASH2LAYOUT1 +#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xffff0000 +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) (((v) & 0xffff) << 16) +#define BFM_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) BM_BCH_FLASH2LAYOUT1_PAGE_SIZE +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE_V(e) BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(BV_BCH_FLASH2LAYOUT1_PAGE_SIZE__##e) +#define BFM_BCH_FLASH2LAYOUT1_PAGE_SIZE_V(v) BM_BCH_FLASH2LAYOUT1_PAGE_SIZE +#define BP_BCH_FLASH2LAYOUT1_ECCN 12 +#define BM_BCH_FLASH2LAYOUT1_ECCN 0xf000 +#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xa +#define BF_BCH_FLASH2LAYOUT1_ECCN(v) (((v) & 0xf) << 12) +#define BFM_BCH_FLASH2LAYOUT1_ECCN(v) BM_BCH_FLASH2LAYOUT1_ECCN +#define BF_BCH_FLASH2LAYOUT1_ECCN_V(e) BF_BCH_FLASH2LAYOUT1_ECCN(BV_BCH_FLASH2LAYOUT1_ECCN__##e) +#define BFM_BCH_FLASH2LAYOUT1_ECCN_V(v) BM_BCH_FLASH2LAYOUT1_ECCN +#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0xfff +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) BM_BCH_FLASH2LAYOUT1_DATAN_SIZE +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE_V(e) BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(BV_BCH_FLASH2LAYOUT1_DATAN_SIZE__##e) +#define BFM_BCH_FLASH2LAYOUT1_DATAN_SIZE_V(v) BM_BCH_FLASH2LAYOUT1_DATAN_SIZE + +#define HW_BCH_FLASH3LAYOUT0 HW(BCH_FLASH3LAYOUT0) +#define HWA_BCH_FLASH3LAYOUT0 (0x8000a000 + 0xe0) +#define HWT_BCH_FLASH3LAYOUT0 HWIO_32_RW +#define HWN_BCH_FLASH3LAYOUT0 BCH_FLASH3LAYOUT0 +#define HWI_BCH_FLASH3LAYOUT0 +#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xff000000 +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) (((v) & 0xff) << 24) +#define BFM_BCH_FLASH3LAYOUT0_NBLOCKS(v) BM_BCH_FLASH3LAYOUT0_NBLOCKS +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS_V(e) BF_BCH_FLASH3LAYOUT0_NBLOCKS(BV_BCH_FLASH3LAYOUT0_NBLOCKS__##e) +#define BFM_BCH_FLASH3LAYOUT0_NBLOCKS_V(v) BM_BCH_FLASH3LAYOUT0_NBLOCKS +#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0xff0000 +#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) (((v) & 0xff) << 16) +#define BFM_BCH_FLASH3LAYOUT0_META_SIZE(v) BM_BCH_FLASH3LAYOUT0_META_SIZE +#define BF_BCH_FLASH3LAYOUT0_META_SIZE_V(e) BF_BCH_FLASH3LAYOUT0_META_SIZE(BV_BCH_FLASH3LAYOUT0_META_SIZE__##e) +#define BFM_BCH_FLASH3LAYOUT0_META_SIZE_V(v) BM_BCH_FLASH3LAYOUT0_META_SIZE +#define BP_BCH_FLASH3LAYOUT0_ECC0 12 +#define BM_BCH_FLASH3LAYOUT0_ECC0 0xf000 +#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xa +#define BF_BCH_FLASH3LAYOUT0_ECC0(v) (((v) & 0xf) << 12) +#define BFM_BCH_FLASH3LAYOUT0_ECC0(v) BM_BCH_FLASH3LAYOUT0_ECC0 +#define BF_BCH_FLASH3LAYOUT0_ECC0_V(e) BF_BCH_FLASH3LAYOUT0_ECC0(BV_BCH_FLASH3LAYOUT0_ECC0__##e) +#define BFM_BCH_FLASH3LAYOUT0_ECC0_V(v) BM_BCH_FLASH3LAYOUT0_ECC0 +#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0xfff +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) BM_BCH_FLASH3LAYOUT0_DATA0_SIZE +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE_V(e) BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(BV_BCH_FLASH3LAYOUT0_DATA0_SIZE__##e) +#define BFM_BCH_FLASH3LAYOUT0_DATA0_SIZE_V(v) BM_BCH_FLASH3LAYOUT0_DATA0_SIZE + +#define HW_BCH_FLASH3LAYOUT1 HW(BCH_FLASH3LAYOUT1) +#define HWA_BCH_FLASH3LAYOUT1 (0x8000a000 + 0xf0) +#define HWT_BCH_FLASH3LAYOUT1 HWIO_32_RW +#define HWN_BCH_FLASH3LAYOUT1 BCH_FLASH3LAYOUT1 +#define HWI_BCH_FLASH3LAYOUT1 +#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xffff0000 +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) (((v) & 0xffff) << 16) +#define BFM_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) BM_BCH_FLASH3LAYOUT1_PAGE_SIZE +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE_V(e) BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(BV_BCH_FLASH3LAYOUT1_PAGE_SIZE__##e) +#define BFM_BCH_FLASH3LAYOUT1_PAGE_SIZE_V(v) BM_BCH_FLASH3LAYOUT1_PAGE_SIZE +#define BP_BCH_FLASH3LAYOUT1_ECCN 12 +#define BM_BCH_FLASH3LAYOUT1_ECCN 0xf000 +#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xa +#define BF_BCH_FLASH3LAYOUT1_ECCN(v) (((v) & 0xf) << 12) +#define BFM_BCH_FLASH3LAYOUT1_ECCN(v) BM_BCH_FLASH3LAYOUT1_ECCN +#define BF_BCH_FLASH3LAYOUT1_ECCN_V(e) BF_BCH_FLASH3LAYOUT1_ECCN(BV_BCH_FLASH3LAYOUT1_ECCN__##e) +#define BFM_BCH_FLASH3LAYOUT1_ECCN_V(v) BM_BCH_FLASH3LAYOUT1_ECCN +#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0xfff +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) BM_BCH_FLASH3LAYOUT1_DATAN_SIZE +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE_V(e) BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(BV_BCH_FLASH3LAYOUT1_DATAN_SIZE__##e) +#define BFM_BCH_FLASH3LAYOUT1_DATAN_SIZE_V(v) BM_BCH_FLASH3LAYOUT1_DATAN_SIZE + +#define HW_BCH_DEBUG0 HW(BCH_DEBUG0) +#define HWA_BCH_DEBUG0 (0x8000a000 + 0x100) +#define HWT_BCH_DEBUG0 HWIO_32_RW +#define HWN_BCH_DEBUG0 BCH_DEBUG0 +#define HWI_BCH_DEBUG0 +#define HW_BCH_DEBUG0_SET HW(BCH_DEBUG0_SET) +#define HWA_BCH_DEBUG0_SET (HWA_BCH_DEBUG0 + 0x4) +#define HWT_BCH_DEBUG0_SET HWIO_32_WO +#define HWN_BCH_DEBUG0_SET BCH_DEBUG0 +#define HWI_BCH_DEBUG0_SET +#define HW_BCH_DEBUG0_CLR HW(BCH_DEBUG0_CLR) +#define HWA_BCH_DEBUG0_CLR (HWA_BCH_DEBUG0 + 0x8) +#define HWT_BCH_DEBUG0_CLR HWIO_32_WO +#define HWN_BCH_DEBUG0_CLR BCH_DEBUG0 +#define HWI_BCH_DEBUG0_CLR +#define HW_BCH_DEBUG0_TOG HW(BCH_DEBUG0_TOG) +#define HWA_BCH_DEBUG0_TOG (HWA_BCH_DEBUG0 + 0xc) +#define HWT_BCH_DEBUG0_TOG HWIO_32_WO +#define HWN_BCH_DEBUG0_TOG BCH_DEBUG0 +#define HWI_BCH_DEBUG0_TOG +#define BP_BCH_DEBUG0_RSVD1 27 +#define BM_BCH_DEBUG0_RSVD1 0xf8000000 +#define BF_BCH_DEBUG0_RSVD1(v) (((v) & 0x1f) << 27) +#define BFM_BCH_DEBUG0_RSVD1(v) BM_BCH_DEBUG0_RSVD1 +#define BF_BCH_DEBUG0_RSVD1_V(e) BF_BCH_DEBUG0_RSVD1(BV_BCH_DEBUG0_RSVD1__##e) +#define BFM_BCH_DEBUG0_RSVD1_V(v) BM_BCH_DEBUG0_RSVD1 +#define BP_BCH_DEBUG0_ROM_BIST_ENABLE 26 +#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x4000000 +#define BF_BCH_DEBUG0_ROM_BIST_ENABLE(v) (((v) & 0x1) << 26) +#define BFM_BCH_DEBUG0_ROM_BIST_ENABLE(v) BM_BCH_DEBUG0_ROM_BIST_ENABLE +#define BF_BCH_DEBUG0_ROM_BIST_ENABLE_V(e) BF_BCH_DEBUG0_ROM_BIST_ENABLE(BV_BCH_DEBUG0_ROM_BIST_ENABLE__##e) +#define BFM_BCH_DEBUG0_ROM_BIST_ENABLE_V(v) BM_BCH_DEBUG0_ROM_BIST_ENABLE +#define BP_BCH_DEBUG0_ROM_BIST_COMPLETE 25 +#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x2000000 +#define BF_BCH_DEBUG0_ROM_BIST_COMPLETE(v) (((v) & 0x1) << 25) +#define BFM_BCH_DEBUG0_ROM_BIST_COMPLETE(v) BM_BCH_DEBUG0_ROM_BIST_COMPLETE +#define BF_BCH_DEBUG0_ROM_BIST_COMPLETE_V(e) BF_BCH_DEBUG0_ROM_BIST_COMPLETE(BV_BCH_DEBUG0_ROM_BIST_COMPLETE__##e) +#define BFM_BCH_DEBUG0_ROM_BIST_COMPLETE_V(v) BM_BCH_DEBUG0_ROM_BIST_COMPLETE +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x1ff0000 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) (((v) & 0x1ff) << 16) +#define BFM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(e) BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__##e) +#define BFM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_V(v) BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL +#define BP_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 15 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x8000 +#define BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v) (((v) & 0x1) << 15) +#define BFM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(v) BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND +#define BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_V(e) BF_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(BV_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND__##e) +#define BFM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_V(v) BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND +#define BP_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 14 +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x4000 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) (((v) & 0x1) << 14) +#define BFM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(v) BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG +#define BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(e) BF_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__##e) +#define BFM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_V(v) BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG +#define BP_BCH_DEBUG0_KES_DEBUG_MODE4K 13 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x2000 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K(v) (((v) & 0x1) << 13) +#define BFM_BCH_DEBUG0_KES_DEBUG_MODE4K(v) BM_BCH_DEBUG0_KES_DEBUG_MODE4K +#define BF_BCH_DEBUG0_KES_DEBUG_MODE4K_V(e) BF_BCH_DEBUG0_KES_DEBUG_MODE4K(BV_BCH_DEBUG0_KES_DEBUG_MODE4K__##e) +#define BFM_BCH_DEBUG0_KES_DEBUG_MODE4K_V(v) BM_BCH_DEBUG0_KES_DEBUG_MODE4K +#define BP_BCH_DEBUG0_KES_DEBUG_KICK 12 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x1000 +#define BF_BCH_DEBUG0_KES_DEBUG_KICK(v) (((v) & 0x1) << 12) +#define BFM_BCH_DEBUG0_KES_DEBUG_KICK(v) BM_BCH_DEBUG0_KES_DEBUG_KICK +#define BF_BCH_DEBUG0_KES_DEBUG_KICK_V(e) BF_BCH_DEBUG0_KES_DEBUG_KICK(BV_BCH_DEBUG0_KES_DEBUG_KICK__##e) +#define BFM_BCH_DEBUG0_KES_DEBUG_KICK_V(v) BM_BCH_DEBUG0_KES_DEBUG_KICK +#define BP_BCH_DEBUG0_KES_STANDALONE 11 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x800 +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BF_BCH_DEBUG0_KES_STANDALONE(v) (((v) & 0x1) << 11) +#define BFM_BCH_DEBUG0_KES_STANDALONE(v) BM_BCH_DEBUG0_KES_STANDALONE +#define BF_BCH_DEBUG0_KES_STANDALONE_V(e) BF_BCH_DEBUG0_KES_STANDALONE(BV_BCH_DEBUG0_KES_STANDALONE__##e) +#define BFM_BCH_DEBUG0_KES_STANDALONE_V(v) BM_BCH_DEBUG0_KES_STANDALONE +#define BP_BCH_DEBUG0_KES_DEBUG_STEP 10 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x400 +#define BF_BCH_DEBUG0_KES_DEBUG_STEP(v) (((v) & 0x1) << 10) +#define BFM_BCH_DEBUG0_KES_DEBUG_STEP(v) BM_BCH_DEBUG0_KES_DEBUG_STEP +#define BF_BCH_DEBUG0_KES_DEBUG_STEP_V(e) BF_BCH_DEBUG0_KES_DEBUG_STEP(BV_BCH_DEBUG0_KES_DEBUG_STEP__##e) +#define BFM_BCH_DEBUG0_KES_DEBUG_STEP_V(v) BM_BCH_DEBUG0_KES_DEBUG_STEP +#define BP_BCH_DEBUG0_KES_DEBUG_STALL 9 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x200 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BF_BCH_DEBUG0_KES_DEBUG_STALL(v) (((v) & 0x1) << 9) +#define BFM_BCH_DEBUG0_KES_DEBUG_STALL(v) BM_BCH_DEBUG0_KES_DEBUG_STALL +#define BF_BCH_DEBUG0_KES_DEBUG_STALL_V(e) BF_BCH_DEBUG0_KES_DEBUG_STALL(BV_BCH_DEBUG0_KES_DEBUG_STALL__##e) +#define BFM_BCH_DEBUG0_KES_DEBUG_STALL_V(v) BM_BCH_DEBUG0_KES_DEBUG_STALL +#define BP_BCH_DEBUG0_BM_KES_TEST_BYPASS 8 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x100 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS(v) (((v) & 0x1) << 8) +#define BFM_BCH_DEBUG0_BM_KES_TEST_BYPASS(v) BM_BCH_DEBUG0_BM_KES_TEST_BYPASS +#define BF_BCH_DEBUG0_BM_KES_TEST_BYPASS_V(e) BF_BCH_DEBUG0_BM_KES_TEST_BYPASS(BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__##e) +#define BFM_BCH_DEBUG0_BM_KES_TEST_BYPASS_V(v) BM_BCH_DEBUG0_BM_KES_TEST_BYPASS +#define BP_BCH_DEBUG0_RSVD0 6 +#define BM_BCH_DEBUG0_RSVD0 0xc0 +#define BF_BCH_DEBUG0_RSVD0(v) (((v) & 0x3) << 6) +#define BFM_BCH_DEBUG0_RSVD0(v) BM_BCH_DEBUG0_RSVD0 +#define BF_BCH_DEBUG0_RSVD0_V(e) BF_BCH_DEBUG0_RSVD0(BV_BCH_DEBUG0_RSVD0__##e) +#define BFM_BCH_DEBUG0_RSVD0_V(v) BM_BCH_DEBUG0_RSVD0 +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x3f +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) (((v) & 0x3f) << 0) +#define BFM_BCH_DEBUG0_DEBUG_REG_SELECT(v) BM_BCH_DEBUG0_DEBUG_REG_SELECT +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT_V(e) BF_BCH_DEBUG0_DEBUG_REG_SELECT(BV_BCH_DEBUG0_DEBUG_REG_SELECT__##e) +#define BFM_BCH_DEBUG0_DEBUG_REG_SELECT_V(v) BM_BCH_DEBUG0_DEBUG_REG_SELECT + +#define HW_BCH_DBGKESREAD HW(BCH_DBGKESREAD) +#define HWA_BCH_DBGKESREAD (0x8000a000 + 0x110) +#define HWT_BCH_DBGKESREAD HWIO_32_RW +#define HWN_BCH_DBGKESREAD BCH_DBGKESREAD +#define HWI_BCH_DBGKESREAD +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xffffffff +#define BF_BCH_DBGKESREAD_VALUES(v) (((v) & 0xffffffff) << 0) +#define BFM_BCH_DBGKESREAD_VALUES(v) BM_BCH_DBGKESREAD_VALUES +#define BF_BCH_DBGKESREAD_VALUES_V(e) BF_BCH_DBGKESREAD_VALUES(BV_BCH_DBGKESREAD_VALUES__##e) +#define BFM_BCH_DBGKESREAD_VALUES_V(v) BM_BCH_DBGKESREAD_VALUES + +#define HW_BCH_DBGCSFEREAD HW(BCH_DBGCSFEREAD) +#define HWA_BCH_DBGCSFEREAD (0x8000a000 + 0x120) +#define HWT_BCH_DBGCSFEREAD HWIO_32_RW +#define HWN_BCH_DBGCSFEREAD BCH_DBGCSFEREAD +#define HWI_BCH_DBGCSFEREAD +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xffffffff +#define BF_BCH_DBGCSFEREAD_VALUES(v) (((v) & 0xffffffff) << 0) +#define BFM_BCH_DBGCSFEREAD_VALUES(v) BM_BCH_DBGCSFEREAD_VALUES +#define BF_BCH_DBGCSFEREAD_VALUES_V(e) BF_BCH_DBGCSFEREAD_VALUES(BV_BCH_DBGCSFEREAD_VALUES__##e) +#define BFM_BCH_DBGCSFEREAD_VALUES_V(v) BM_BCH_DBGCSFEREAD_VALUES + +#define HW_BCH_DBGSYNDGENREAD HW(BCH_DBGSYNDGENREAD) +#define HWA_BCH_DBGSYNDGENREAD (0x8000a000 + 0x130) +#define HWT_BCH_DBGSYNDGENREAD HWIO_32_RW +#define HWN_BCH_DBGSYNDGENREAD BCH_DBGSYNDGENREAD +#define HWI_BCH_DBGSYNDGENREAD +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xffffffff +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (((v) & 0xffffffff) << 0) +#define BFM_BCH_DBGSYNDGENREAD_VALUES(v) BM_BCH_DBGSYNDGENREAD_VALUES +#define BF_BCH_DBGSYNDGENREAD_VALUES_V(e) BF_BCH_DBGSYNDGENREAD_VALUES(BV_BCH_DBGSYNDGENREAD_VALUES__##e) +#define BFM_BCH_DBGSYNDGENREAD_VALUES_V(v) BM_BCH_DBGSYNDGENREAD_VALUES + +#define HW_BCH_DBGAHBMREAD HW(BCH_DBGAHBMREAD) +#define HWA_BCH_DBGAHBMREAD (0x8000a000 + 0x140) +#define HWT_BCH_DBGAHBMREAD HWIO_32_RW +#define HWN_BCH_DBGAHBMREAD BCH_DBGAHBMREAD +#define HWI_BCH_DBGAHBMREAD +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xffffffff +#define BF_BCH_DBGAHBMREAD_VALUES(v) (((v) & 0xffffffff) << 0) +#define BFM_BCH_DBGAHBMREAD_VALUES(v) BM_BCH_DBGAHBMREAD_VALUES +#define BF_BCH_DBGAHBMREAD_VALUES_V(e) BF_BCH_DBGAHBMREAD_VALUES(BV_BCH_DBGAHBMREAD_VALUES__##e) +#define BFM_BCH_DBGAHBMREAD_VALUES_V(v) BM_BCH_DBGAHBMREAD_VALUES + +#define HW_BCH_BLOCKNAME HW(BCH_BLOCKNAME) +#define HWA_BCH_BLOCKNAME (0x8000a000 + 0x150) +#define HWT_BCH_BLOCKNAME HWIO_32_RW +#define HWN_BCH_BLOCKNAME BCH_BLOCKNAME +#define HWI_BCH_BLOCKNAME +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xffffffff +#define BF_BCH_BLOCKNAME_NAME(v) (((v) & 0xffffffff) << 0) +#define BFM_BCH_BLOCKNAME_NAME(v) BM_BCH_BLOCKNAME_NAME +#define BF_BCH_BLOCKNAME_NAME_V(e) BF_BCH_BLOCKNAME_NAME(BV_BCH_BLOCKNAME_NAME__##e) +#define BFM_BCH_BLOCKNAME_NAME_V(v) BM_BCH_BLOCKNAME_NAME + +#define HW_BCH_VERSION HW(BCH_VERSION) +#define HWA_BCH_VERSION (0x8000a000 + 0x160) +#define HWT_BCH_VERSION HWIO_32_RW +#define HWN_BCH_VERSION BCH_VERSION +#define HWI_BCH_VERSION +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR 0xff000000 +#define BF_BCH_VERSION_MAJOR(v) (((v) & 0xff) << 24) +#define BFM_BCH_VERSION_MAJOR(v) BM_BCH_VERSION_MAJOR +#define BF_BCH_VERSION_MAJOR_V(e) BF_BCH_VERSION_MAJOR(BV_BCH_VERSION_MAJOR__##e) +#define BFM_BCH_VERSION_MAJOR_V(v) BM_BCH_VERSION_MAJOR +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR 0xff0000 +#define BF_BCH_VERSION_MINOR(v) (((v) & 0xff) << 16) +#define BFM_BCH_VERSION_MINOR(v) BM_BCH_VERSION_MINOR +#define BF_BCH_VERSION_MINOR_V(e) BF_BCH_VERSION_MINOR(BV_BCH_VERSION_MINOR__##e) +#define BFM_BCH_VERSION_MINOR_V(v) BM_BCH_VERSION_MINOR +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP 0xffff +#define BF_BCH_VERSION_STEP(v) (((v) & 0xffff) << 0) +#define BFM_BCH_VERSION_STEP(v) BM_BCH_VERSION_STEP +#define BF_BCH_VERSION_STEP_V(e) BF_BCH_VERSION_STEP(BV_BCH_VERSION_STEP__##e) +#define BFM_BCH_VERSION_STEP_V(v) BM_BCH_VERSION_STEP + +#endif /* __HEADERGEN_IMX233_BCH_H__*/ diff --git a/firmware/target/arm/imx233/regs/imx233/clkctrl.h b/firmware/target/arm/imx233/regs/imx233/clkctrl.h new file mode 100644 index 0000000000..3aaefcbab5 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/clkctrl.h @@ -0,0 +1,1146 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * imx233 version: 2.4.0 + * imx233 authors: Amaury Pouly + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_IMX233_CLKCTRL_H__ +#define __HEADERGEN_IMX233_CLKCTRL_H__ + +#define HW_CLKCTRL_PLLCTRL0 HW(CLKCTRL_PLLCTRL0) +#define HWA_CLKCTRL_PLLCTRL0 (0x80040000 + 0x0) +#define HWT_CLKCTRL_PLLCTRL0 HWIO_32_RW +#define HWN_CLKCTRL_PLLCTRL0 CLKCTRL_PLLCTRL0 +#define HWI_CLKCTRL_PLLCTRL0 +#define HW_CLKCTRL_PLLCTRL0_SET HW(CLKCTRL_PLLCTRL0_SET) +#define HWA_CLKCTRL_PLLCTRL0_SET (HWA_CLKCTRL_PLLCTRL0 + 0x4) +#define HWT_CLKCTRL_PLLCTRL0_SET HWIO_32_WO +#define HWN_CLKCTRL_PLLCTRL0_SET CLKCTRL_PLLCTRL0 +#define HWI_CLKCTRL_PLLCTRL0_SET +#define HW_CLKCTRL_PLLCTRL0_CLR HW(CLKCTRL_PLLCTRL0_CLR) +#define HWA_CLKCTRL_PLLCTRL0_CLR (HWA_CLKCTRL_PLLCTRL0 + 0x8) +#define HWT_CLKCTRL_PLLCTRL0_CLR HWIO_32_WO +#define HWN_CLKCTRL_PLLCTRL0_CLR CLKCTRL_PLLCTRL0 +#define HWI_CLKCTRL_PLLCTRL0_CLR +#define HW_CLKCTRL_PLLCTRL0_TOG HW(CLKCTRL_PLLCTRL0_TOG) +#define HWA_CLKCTRL_PLLCTRL0_TOG (HWA_CLKCTRL_PLLCTRL0 + 0xc) +#define HWT_CLKCTRL_PLLCTRL0_TOG HWIO_32_WO +#define HWN_CLKCTRL_PLLCTRL0_TOG CLKCTRL_PLLCTRL0 +#define HWI_CLKCTRL_PLLCTRL0_TOG +#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xc0000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) (((v) & 0x3) << 30) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD6(v) BM_CLKCTRL_PLLCTRL0_RSRVD6 +#define BF_CLKCTRL_PLLCTRL0_RSRVD6_V(e) BF_CLKCTRL_PLLCTRL0_RSRVD6(BV_CLKCTRL_PLLCTRL0_RSRVD6__##e) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD6_V(v) BM_CLKCTRL_PLLCTRL0_RSRVD6 +#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 +#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) (((v) & 0x3) << 28) +#define BFM_CLKCTRL_PLLCTRL0_LFR_SEL(v) BM_CLKCTRL_PLLCTRL0_LFR_SEL +#define BF_CLKCTRL_PLLCTRL0_LFR_SEL_V(e) BF_CLKCTRL_PLLCTRL0_LFR_SEL(BV_CLKCTRL_PLLCTRL0_LFR_SEL__##e) +#define BFM_CLKCTRL_PLLCTRL0_LFR_SEL_V(v) BM_CLKCTRL_PLLCTRL0_LFR_SEL +#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0xc000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) (((v) & 0x3) << 26) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD5(v) BM_CLKCTRL_PLLCTRL0_RSRVD5 +#define BF_CLKCTRL_PLLCTRL0_RSRVD5_V(e) BF_CLKCTRL_PLLCTRL0_RSRVD5(BV_CLKCTRL_PLLCTRL0_RSRVD5__##e) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD5_V(v) BM_CLKCTRL_PLLCTRL0_RSRVD5 +#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x3000000 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 +#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) (((v) & 0x3) << 24) +#define BFM_CLKCTRL_PLLCTRL0_CP_SEL(v) BM_CLKCTRL_PLLCTRL0_CP_SEL +#define BF_CLKCTRL_PLLCTRL0_CP_SEL_V(e) BF_CLKCTRL_PLLCTRL0_CP_SEL(BV_CLKCTRL_PLLCTRL0_CP_SEL__##e) +#define BFM_CLKCTRL_PLLCTRL0_CP_SEL_V(v) BM_CLKCTRL_PLLCTRL0_CP_SEL +#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0xc00000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) (((v) & 0x3) << 22) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD4(v) BM_CLKCTRL_PLLCTRL0_RSRVD4 +#define BF_CLKCTRL_PLLCTRL0_RSRVD4_V(e) BF_CLKCTRL_PLLCTRL0_RSRVD4(BV_CLKCTRL_PLLCTRL0_RSRVD4__##e) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD4_V(v) BM_CLKCTRL_PLLCTRL0_RSRVD4 +#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x300000 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 +#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) (((v) & 0x3) << 20) +#define BFM_CLKCTRL_PLLCTRL0_DIV_SEL(v) BM_CLKCTRL_PLLCTRL0_DIV_SEL +#define BF_CLKCTRL_PLLCTRL0_DIV_SEL_V(e) BF_CLKCTRL_PLLCTRL0_DIV_SEL(BV_CLKCTRL_PLLCTRL0_DIV_SEL__##e) +#define BFM_CLKCTRL_PLLCTRL0_DIV_SEL_V(v) BM_CLKCTRL_PLLCTRL0_DIV_SEL +#define BP_CLKCTRL_PLLCTRL0_RSRVD3 19 +#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x80000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD3(v) (((v) & 0x1) << 19) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD3(v) BM_CLKCTRL_PLLCTRL0_RSRVD3 +#define BF_CLKCTRL_PLLCTRL0_RSRVD3_V(e) BF_CLKCTRL_PLLCTRL0_RSRVD3(BV_CLKCTRL_PLLCTRL0_RSRVD3__##e) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD3_V(v) BM_CLKCTRL_PLLCTRL0_RSRVD3 +#define BP_CLKCTRL_PLLCTRL0_EN_USB_CLKS 18 +#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x40000 +#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) (((v) & 0x1) << 18) +#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS(v) BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS +#define BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(e) BF_CLKCTRL_PLLCTRL0_EN_USB_CLKS(BV_CLKCTRL_PLLCTRL0_EN_USB_CLKS__##e) +#define BFM_CLKCTRL_PLLCTRL0_EN_USB_CLKS_V(v) BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS +#define BP_CLKCTRL_PLLCTRL0_RSRVD2 17 +#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x20000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD2(v) (((v) & 0x1) << 17) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD2(v) BM_CLKCTRL_PLLCTRL0_RSRVD2 +#define BF_CLKCTRL_PLLCTRL0_RSRVD2_V(e) BF_CLKCTRL_PLLCTRL0_RSRVD2(BV_CLKCTRL_PLLCTRL0_RSRVD2__##e) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD2_V(v) BM_CLKCTRL_PLLCTRL0_RSRVD2 +#define BP_CLKCTRL_PLLCTRL0_POWER 16 +#define BM_CLKCTRL_PLLCTRL0_POWER 0x10000 +#define BF_CLKCTRL_PLLCTRL0_POWER(v) (((v) & 0x1) << 16) +#define BFM_CLKCTRL_PLLCTRL0_POWER(v) BM_CLKCTRL_PLLCTRL0_POWER +#define BF_CLKCTRL_PLLCTRL0_POWER_V(e) BF_CLKCTRL_PLLCTRL0_POWER(BV_CLKCTRL_PLLCTRL0_POWER__##e) +#define BFM_CLKCTRL_PLLCTRL0_POWER_V(v) BM_CLKCTRL_PLLCTRL0_POWER +#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0xffff +#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) (((v) & 0xffff) << 0) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD1(v) BM_CLKCTRL_PLLCTRL0_RSRVD1 +#define BF_CLKCTRL_PLLCTRL0_RSRVD1_V(e) BF_CLKCTRL_PLLCTRL0_RSRVD1(BV_CLKCTRL_PLLCTRL0_RSRVD1__##e) +#define BFM_CLKCTRL_PLLCTRL0_RSRVD1_V(v) BM_CLKCTRL_PLLCTRL0_RSRVD1 + +#define HW_CLKCTRL_PLLCTRL1 HW(CLKCTRL_PLLCTRL1) +#define HWA_CLKCTRL_PLLCTRL1 (0x80040000 + 0x10) +#define HWT_CLKCTRL_PLLCTRL1 HWIO_32_RW +#define HWN_CLKCTRL_PLLCTRL1 CLKCTRL_PLLCTRL1 +#define HWI_CLKCTRL_PLLCTRL1 +#define BP_CLKCTRL_PLLCTRL1_LOCK 31 +#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 +#define BF_CLKCTRL_PLLCTRL1_LOCK(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_PLLCTRL1_LOCK(v) BM_CLKCTRL_PLLCTRL1_LOCK +#define BF_CLKCTRL_PLLCTRL1_LOCK_V(e) BF_CLKCTRL_PLLCTRL1_LOCK(BV_CLKCTRL_PLLCTRL1_LOCK__##e) +#define BFM_CLKCTRL_PLLCTRL1_LOCK_V(v) BM_CLKCTRL_PLLCTRL1_LOCK +#define BP_CLKCTRL_PLLCTRL1_FORCE_LOCK 30 +#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 +#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK(v) BM_CLKCTRL_PLLCTRL1_FORCE_LOCK +#define BF_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(e) BF_CLKCTRL_PLLCTRL1_FORCE_LOCK(BV_CLKCTRL_PLLCTRL1_FORCE_LOCK__##e) +#define BFM_CLKCTRL_PLLCTRL1_FORCE_LOCK_V(v) BM_CLKCTRL_PLLCTRL1_FORCE_LOCK +#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3fff0000 +#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) (((v) & 0x3fff) << 16) +#define BFM_CLKCTRL_PLLCTRL1_RSRVD1(v) BM_CLKCTRL_PLLCTRL1_RSRVD1 +#define BF_CLKCTRL_PLLCTRL1_RSRVD1_V(e) BF_CLKCTRL_PLLCTRL1_RSRVD1(BV_CLKCTRL_PLLCTRL1_RSRVD1__##e) +#define BFM_CLKCTRL_PLLCTRL1_RSRVD1_V(v) BM_CLKCTRL_PLLCTRL1_RSRVD1 +#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0xffff +#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) (((v) & 0xffff) << 0) +#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) BM_CLKCTRL_PLLCTRL1_LOCK_COUNT +#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(e) BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(BV_CLKCTRL_PLLCTRL1_LOCK_COUNT__##e) +#define BFM_CLKCTRL_PLLCTRL1_LOCK_COUNT_V(v) BM_CLKCTRL_PLLCTRL1_LOCK_COUNT + +#define HW_CLKCTRL_CPU HW(CLKCTRL_CPU) +#define HWA_CLKCTRL_CPU (0x80040000 + 0x20) +#define HWT_CLKCTRL_CPU HWIO_32_RW +#define HWN_CLKCTRL_CPU CLKCTRL_CPU +#define HWI_CLKCTRL_CPU +#define HW_CLKCTRL_CPU_SET HW(CLKCTRL_CPU_SET) +#define HWA_CLKCTRL_CPU_SET (HWA_CLKCTRL_CPU + 0x4) +#define HWT_CLKCTRL_CPU_SET HWIO_32_WO +#define HWN_CLKCTRL_CPU_SET CLKCTRL_CPU +#define HWI_CLKCTRL_CPU_SET +#define HW_CLKCTRL_CPU_CLR HW(CLKCTRL_CPU_CLR) +#define HWA_CLKCTRL_CPU_CLR (HWA_CLKCTRL_CPU + 0x8) +#define HWT_CLKCTRL_CPU_CLR HWIO_32_WO +#define HWN_CLKCTRL_CPU_CLR CLKCTRL_CPU +#define HWI_CLKCTRL_CPU_CLR +#define HW_CLKCTRL_CPU_TOG HW(CLKCTRL_CPU_TOG) +#define HWA_CLKCTRL_CPU_TOG (HWA_CLKCTRL_CPU + 0xc) +#define HWT_CLKCTRL_CPU_TOG HWIO_32_WO +#define HWN_CLKCTRL_CPU_TOG CLKCTRL_CPU +#define HWI_CLKCTRL_CPU_TOG +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xc0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) (((v) & 0x3) << 30) +#define BFM_CLKCTRL_CPU_RSRVD5(v) BM_CLKCTRL_CPU_RSRVD5 +#define BF_CLKCTRL_CPU_RSRVD5_V(e) BF_CLKCTRL_CPU_RSRVD5(BV_CLKCTRL_CPU_RSRVD5__##e) +#define BFM_CLKCTRL_CPU_RSRVD5_V(v) BM_CLKCTRL_CPU_RSRVD5 +#define BP_CLKCTRL_CPU_BUSY_REF_XTAL 29 +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BF_CLKCTRL_CPU_BUSY_REF_XTAL(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_CPU_BUSY_REF_XTAL(v) BM_CLKCTRL_CPU_BUSY_REF_XTAL +#define BF_CLKCTRL_CPU_BUSY_REF_XTAL_V(e) BF_CLKCTRL_CPU_BUSY_REF_XTAL(BV_CLKCTRL_CPU_BUSY_REF_XTAL__##e) +#define BFM_CLKCTRL_CPU_BUSY_REF_XTAL_V(v) BM_CLKCTRL_CPU_BUSY_REF_XTAL +#define BP_CLKCTRL_CPU_BUSY_REF_CPU 28 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BF_CLKCTRL_CPU_BUSY_REF_CPU(v) (((v) & 0x1) << 28) +#define BFM_CLKCTRL_CPU_BUSY_REF_CPU(v) BM_CLKCTRL_CPU_BUSY_REF_CPU +#define BF_CLKCTRL_CPU_BUSY_REF_CPU_V(e) BF_CLKCTRL_CPU_BUSY_REF_CPU(BV_CLKCTRL_CPU_BUSY_REF_CPU__##e) +#define BFM_CLKCTRL_CPU_BUSY_REF_CPU_V(v) BM_CLKCTRL_CPU_BUSY_REF_CPU +#define BP_CLKCTRL_CPU_RSRVD4 27 +#define BM_CLKCTRL_CPU_RSRVD4 0x8000000 +#define BF_CLKCTRL_CPU_RSRVD4(v) (((v) & 0x1) << 27) +#define BFM_CLKCTRL_CPU_RSRVD4(v) BM_CLKCTRL_CPU_RSRVD4 +#define BF_CLKCTRL_CPU_RSRVD4_V(e) BF_CLKCTRL_CPU_RSRVD4(BV_CLKCTRL_CPU_RSRVD4__##e) +#define BFM_CLKCTRL_CPU_RSRVD4_V(v) BM_CLKCTRL_CPU_RSRVD4 +#define BP_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 26 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x4000000 +#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v) (((v) & 0x1) << 26) +#define BFM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(v) BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN +#define BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN_V(e) BF_CLKCTRL_CPU_DIV_XTAL_FRAC_EN(BV_CLKCTRL_CPU_DIV_XTAL_FRAC_EN__##e) +#define BFM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN_V(v) BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x3ff0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) (((v) & 0x3ff) << 16) +#define BFM_CLKCTRL_CPU_DIV_XTAL(v) BM_CLKCTRL_CPU_DIV_XTAL +#define BF_CLKCTRL_CPU_DIV_XTAL_V(e) BF_CLKCTRL_CPU_DIV_XTAL(BV_CLKCTRL_CPU_DIV_XTAL__##e) +#define BFM_CLKCTRL_CPU_DIV_XTAL_V(v) BM_CLKCTRL_CPU_DIV_XTAL +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0xe000 +#define BF_CLKCTRL_CPU_RSRVD3(v) (((v) & 0x7) << 13) +#define BFM_CLKCTRL_CPU_RSRVD3(v) BM_CLKCTRL_CPU_RSRVD3 +#define BF_CLKCTRL_CPU_RSRVD3_V(e) BF_CLKCTRL_CPU_RSRVD3(BV_CLKCTRL_CPU_RSRVD3__##e) +#define BFM_CLKCTRL_CPU_RSRVD3_V(v) BM_CLKCTRL_CPU_RSRVD3 +#define BP_CLKCTRL_CPU_INTERRUPT_WAIT 12 +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x1000 +#define BF_CLKCTRL_CPU_INTERRUPT_WAIT(v) (((v) & 0x1) << 12) +#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT(v) BM_CLKCTRL_CPU_INTERRUPT_WAIT +#define BF_CLKCTRL_CPU_INTERRUPT_WAIT_V(e) BF_CLKCTRL_CPU_INTERRUPT_WAIT(BV_CLKCTRL_CPU_INTERRUPT_WAIT__##e) +#define BFM_CLKCTRL_CPU_INTERRUPT_WAIT_V(v) BM_CLKCTRL_CPU_INTERRUPT_WAIT +#define BP_CLKCTRL_CPU_RSRVD2 11 +#define BM_CLKCTRL_CPU_RSRVD2 0x800 +#define BF_CLKCTRL_CPU_RSRVD2(v) (((v) & 0x1) << 11) +#define BFM_CLKCTRL_CPU_RSRVD2(v) BM_CLKCTRL_CPU_RSRVD2 +#define BF_CLKCTRL_CPU_RSRVD2_V(e) BF_CLKCTRL_CPU_RSRVD2(BV_CLKCTRL_CPU_RSRVD2__##e) +#define BFM_CLKCTRL_CPU_RSRVD2_V(v) BM_CLKCTRL_CPU_RSRVD2 +#define BP_CLKCTRL_CPU_DIV_CPU_FRAC_EN 10 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x400 +#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v) (((v) & 0x1) << 10) +#define BFM_CLKCTRL_CPU_DIV_CPU_FRAC_EN(v) BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN +#define BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN_V(e) BF_CLKCTRL_CPU_DIV_CPU_FRAC_EN(BV_CLKCTRL_CPU_DIV_CPU_FRAC_EN__##e) +#define BFM_CLKCTRL_CPU_DIV_CPU_FRAC_EN_V(v) BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x3c0 +#define BF_CLKCTRL_CPU_RSRVD1(v) (((v) & 0xf) << 6) +#define BFM_CLKCTRL_CPU_RSRVD1(v) BM_CLKCTRL_CPU_RSRVD1 +#define BF_CLKCTRL_CPU_RSRVD1_V(e) BF_CLKCTRL_CPU_RSRVD1(BV_CLKCTRL_CPU_RSRVD1__##e) +#define BFM_CLKCTRL_CPU_RSRVD1_V(v) BM_CLKCTRL_CPU_RSRVD1 +#define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x3f +#define BF_CLKCTRL_CPU_DIV_CPU(v) (((v) & 0x3f) << 0) +#define BFM_CLKCTRL_CPU_DIV_CPU(v) BM_CLKCTRL_CPU_DIV_CPU +#define BF_CLKCTRL_CPU_DIV_CPU_V(e) BF_CLKCTRL_CPU_DIV_CPU(BV_CLKCTRL_CPU_DIV_CPU__##e) +#define BFM_CLKCTRL_CPU_DIV_CPU_V(v) BM_CLKCTRL_CPU_DIV_CPU + +#define HW_CLKCTRL_HBUS HW(CLKCTRL_HBUS) +#define HWA_CLKCTRL_HBUS (0x80040000 + 0x30) +#define HWT_CLKCTRL_HBUS HWIO_32_RW +#define HWN_CLKCTRL_HBUS CLKCTRL_HBUS +#define HWI_CLKCTRL_HBUS +#define HW_CLKCTRL_HBUS_SET HW(CLKCTRL_HBUS_SET) +#define HWA_CLKCTRL_HBUS_SET (HWA_CLKCTRL_HBUS + 0x4) +#define HWT_CLKCTRL_HBUS_SET HWIO_32_WO +#define HWN_CLKCTRL_HBUS_SET CLKCTRL_HBUS +#define HWI_CLKCTRL_HBUS_SET +#define HW_CLKCTRL_HBUS_CLR HW(CLKCTRL_HBUS_CLR) +#define HWA_CLKCTRL_HBUS_CLR (HWA_CLKCTRL_HBUS + 0x8) +#define HWT_CLKCTRL_HBUS_CLR HWIO_32_WO +#define HWN_CLKCTRL_HBUS_CLR CLKCTRL_HBUS +#define HWI_CLKCTRL_HBUS_CLR +#define HW_CLKCTRL_HBUS_TOG HW(CLKCTRL_HBUS_TOG) +#define HWA_CLKCTRL_HBUS_TOG (HWA_CLKCTRL_HBUS + 0xc) +#define HWT_CLKCTRL_HBUS_TOG HWIO_32_WO +#define HWN_CLKCTRL_HBUS_TOG CLKCTRL_HBUS +#define HWI_CLKCTRL_HBUS_TOG +#define BP_CLKCTRL_HBUS_RSRVD4 30 +#define BM_CLKCTRL_HBUS_RSRVD4 0xc0000000 +#define BF_CLKCTRL_HBUS_RSRVD4(v) (((v) & 0x3) << 30) +#define BFM_CLKCTRL_HBUS_RSRVD4(v) BM_CLKCTRL_HBUS_RSRVD4 +#define BF_CLKCTRL_HBUS_RSRVD4_V(e) BF_CLKCTRL_HBUS_RSRVD4(BV_CLKCTRL_HBUS_RSRVD4__##e) +#define BFM_CLKCTRL_HBUS_RSRVD4_V(v) BM_CLKCTRL_HBUS_RSRVD4 +#define BP_CLKCTRL_HBUS_BUSY 29 +#define BM_CLKCTRL_HBUS_BUSY 0x20000000 +#define BF_CLKCTRL_HBUS_BUSY(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_HBUS_BUSY(v) BM_CLKCTRL_HBUS_BUSY +#define BF_CLKCTRL_HBUS_BUSY_V(e) BF_CLKCTRL_HBUS_BUSY(BV_CLKCTRL_HBUS_BUSY__##e) +#define BFM_CLKCTRL_HBUS_BUSY_V(v) BM_CLKCTRL_HBUS_BUSY +#define BP_CLKCTRL_HBUS_DCP_AS_ENABLE 28 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 +#define BF_CLKCTRL_HBUS_DCP_AS_ENABLE(v) (((v) & 0x1) << 28) +#define BFM_CLKCTRL_HBUS_DCP_AS_ENABLE(v) BM_CLKCTRL_HBUS_DCP_AS_ENABLE +#define BF_CLKCTRL_HBUS_DCP_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_DCP_AS_ENABLE(BV_CLKCTRL_HBUS_DCP_AS_ENABLE__##e) +#define BFM_CLKCTRL_HBUS_DCP_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_DCP_AS_ENABLE +#define BP_CLKCTRL_HBUS_PXP_AS_ENABLE 27 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x8000000 +#define BF_CLKCTRL_HBUS_PXP_AS_ENABLE(v) (((v) & 0x1) << 27) +#define BFM_CLKCTRL_HBUS_PXP_AS_ENABLE(v) BM_CLKCTRL_HBUS_PXP_AS_ENABLE +#define BF_CLKCTRL_HBUS_PXP_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_PXP_AS_ENABLE(BV_CLKCTRL_HBUS_PXP_AS_ENABLE__##e) +#define BFM_CLKCTRL_HBUS_PXP_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_PXP_AS_ENABLE +#define BP_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 26 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x4000000 +#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v) (((v) & 0x1) << 26) +#define BFM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(v) BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE +#define BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_APBHDMA_AS_ENABLE(BV_CLKCTRL_HBUS_APBHDMA_AS_ENABLE__##e) +#define BFM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE +#define BP_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 25 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x2000000 +#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v) (((v) & 0x1) << 25) +#define BFM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(v) BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE +#define BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_APBXDMA_AS_ENABLE(BV_CLKCTRL_HBUS_APBXDMA_AS_ENABLE__##e) +#define BFM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE +#define BP_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 24 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x1000000 +#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v) (((v) & 0x1) << 24) +#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(v) BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE +#define BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE(BV_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE__##e) +#define BFM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE +#define BP_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 23 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x800000 +#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v) (((v) & 0x1) << 23) +#define BFM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(v) BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE +#define BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE(BV_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE__##e) +#define BFM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE +#define BP_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 22 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x400000 +#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v) (((v) & 0x1) << 22) +#define BFM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(v) BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE +#define BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE(BV_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE__##e) +#define BFM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE +#define BP_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 21 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x200000 +#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v) (((v) & 0x1) << 21) +#define BFM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(v) BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE +#define BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE_V(e) BF_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE(BV_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE__##e) +#define BFM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE_V(v) BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE +#define BP_CLKCTRL_HBUS_AUTO_SLOW_MODE 20 +#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x100000 +#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) (((v) & 0x1) << 20) +#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE(v) BM_CLKCTRL_HBUS_AUTO_SLOW_MODE +#define BF_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(e) BF_CLKCTRL_HBUS_AUTO_SLOW_MODE(BV_CLKCTRL_HBUS_AUTO_SLOW_MODE__##e) +#define BFM_CLKCTRL_HBUS_AUTO_SLOW_MODE_V(v) BM_CLKCTRL_HBUS_AUTO_SLOW_MODE +#define BP_CLKCTRL_HBUS_RSRVD2 19 +#define BM_CLKCTRL_HBUS_RSRVD2 0x80000 +#define BF_CLKCTRL_HBUS_RSRVD2(v) (((v) & 0x1) << 19) +#define BFM_CLKCTRL_HBUS_RSRVD2(v) BM_CLKCTRL_HBUS_RSRVD2 +#define BF_CLKCTRL_HBUS_RSRVD2_V(e) BF_CLKCTRL_HBUS_RSRVD2(BV_CLKCTRL_HBUS_RSRVD2__##e) +#define BFM_CLKCTRL_HBUS_RSRVD2_V(v) BM_CLKCTRL_HBUS_RSRVD2 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x70000 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) (((v) & 0x7) << 16) +#define BFM_CLKCTRL_HBUS_SLOW_DIV(v) BM_CLKCTRL_HBUS_SLOW_DIV +#define BF_CLKCTRL_HBUS_SLOW_DIV_V(e) BF_CLKCTRL_HBUS_SLOW_DIV(BV_CLKCTRL_HBUS_SLOW_DIV__##e) +#define BFM_CLKCTRL_HBUS_SLOW_DIV_V(v) BM_CLKCTRL_HBUS_SLOW_DIV +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0xffc0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) (((v) & 0x3ff) << 6) +#define BFM_CLKCTRL_HBUS_RSRVD1(v) BM_CLKCTRL_HBUS_RSRVD1 +#define BF_CLKCTRL_HBUS_RSRVD1_V(e) BF_CLKCTRL_HBUS_RSRVD1(BV_CLKCTRL_HBUS_RSRVD1__##e) +#define BFM_CLKCTRL_HBUS_RSRVD1_V(v) BM_CLKCTRL_HBUS_RSRVD1 +#define BP_CLKCTRL_HBUS_DIV_FRAC_EN 5 +#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x20 +#define BF_CLKCTRL_HBUS_DIV_FRAC_EN(v) (((v) & 0x1) << 5) +#define BFM_CLKCTRL_HBUS_DIV_FRAC_EN(v) BM_CLKCTRL_HBUS_DIV_FRAC_EN +#define BF_CLKCTRL_HBUS_DIV_FRAC_EN_V(e) BF_CLKCTRL_HBUS_DIV_FRAC_EN(BV_CLKCTRL_HBUS_DIV_FRAC_EN__##e) +#define BFM_CLKCTRL_HBUS_DIV_FRAC_EN_V(v) BM_CLKCTRL_HBUS_DIV_FRAC_EN +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x1f +#define BF_CLKCTRL_HBUS_DIV(v) (((v) & 0x1f) << 0) +#define BFM_CLKCTRL_HBUS_DIV(v) BM_CLKCTRL_HBUS_DIV +#define BF_CLKCTRL_HBUS_DIV_V(e) BF_CLKCTRL_HBUS_DIV(BV_CLKCTRL_HBUS_DIV__##e) +#define BFM_CLKCTRL_HBUS_DIV_V(v) BM_CLKCTRL_HBUS_DIV + +#define HW_CLKCTRL_XBUS HW(CLKCTRL_XBUS) +#define HWA_CLKCTRL_XBUS (0x80040000 + 0x40) +#define HWT_CLKCTRL_XBUS HWIO_32_RW +#define HWN_CLKCTRL_XBUS CLKCTRL_XBUS +#define HWI_CLKCTRL_XBUS +#define BP_CLKCTRL_XBUS_BUSY 31 +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BF_CLKCTRL_XBUS_BUSY(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_XBUS_BUSY(v) BM_CLKCTRL_XBUS_BUSY +#define BF_CLKCTRL_XBUS_BUSY_V(e) BF_CLKCTRL_XBUS_BUSY(BV_CLKCTRL_XBUS_BUSY__##e) +#define BFM_CLKCTRL_XBUS_BUSY_V(v) BM_CLKCTRL_XBUS_BUSY +#define BP_CLKCTRL_XBUS_RSRVD1 11 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7ffff800 +#define BF_CLKCTRL_XBUS_RSRVD1(v) (((v) & 0xfffff) << 11) +#define BFM_CLKCTRL_XBUS_RSRVD1(v) BM_CLKCTRL_XBUS_RSRVD1 +#define BF_CLKCTRL_XBUS_RSRVD1_V(e) BF_CLKCTRL_XBUS_RSRVD1(BV_CLKCTRL_XBUS_RSRVD1__##e) +#define BFM_CLKCTRL_XBUS_RSRVD1_V(v) BM_CLKCTRL_XBUS_RSRVD1 +#define BP_CLKCTRL_XBUS_DIV_FRAC_EN 10 +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x400 +#define BF_CLKCTRL_XBUS_DIV_FRAC_EN(v) (((v) & 0x1) << 10) +#define BFM_CLKCTRL_XBUS_DIV_FRAC_EN(v) BM_CLKCTRL_XBUS_DIV_FRAC_EN +#define BF_CLKCTRL_XBUS_DIV_FRAC_EN_V(e) BF_CLKCTRL_XBUS_DIV_FRAC_EN(BV_CLKCTRL_XBUS_DIV_FRAC_EN__##e) +#define BFM_CLKCTRL_XBUS_DIV_FRAC_EN_V(v) BM_CLKCTRL_XBUS_DIV_FRAC_EN +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x3ff +#define BF_CLKCTRL_XBUS_DIV(v) (((v) & 0x3ff) << 0) +#define BFM_CLKCTRL_XBUS_DIV(v) BM_CLKCTRL_XBUS_DIV +#define BF_CLKCTRL_XBUS_DIV_V(e) BF_CLKCTRL_XBUS_DIV(BV_CLKCTRL_XBUS_DIV__##e) +#define BFM_CLKCTRL_XBUS_DIV_V(v) BM_CLKCTRL_XBUS_DIV + +#define HW_CLKCTRL_XTAL HW(CLKCTRL_XTAL) +#define HWA_CLKCTRL_XTAL (0x80040000 + 0x50) +#define HWT_CLKCTRL_XTAL HWIO_32_RW +#define HWN_CLKCTRL_XTAL CLKCTRL_XTAL +#define HWI_CLKCTRL_XTAL +#define HW_CLKCTRL_XTAL_SET HW(CLKCTRL_XTAL_SET) +#define HWA_CLKCTRL_XTAL_SET (HWA_CLKCTRL_XTAL + 0x4) +#define HWT_CLKCTRL_XTAL_SET HWIO_32_WO +#define HWN_CLKCTRL_XTAL_SET CLKCTRL_XTAL +#define HWI_CLKCTRL_XTAL_SET +#define HW_CLKCTRL_XTAL_CLR HW(CLKCTRL_XTAL_CLR) +#define HWA_CLKCTRL_XTAL_CLR (HWA_CLKCTRL_XTAL + 0x8) +#define HWT_CLKCTRL_XTAL_CLR HWIO_32_WO +#define HWN_CLKCTRL_XTAL_CLR CLKCTRL_XTAL +#define HWI_CLKCTRL_XTAL_CLR +#define HW_CLKCTRL_XTAL_TOG HW(CLKCTRL_XTAL_TOG) +#define HWA_CLKCTRL_XTAL_TOG (HWA_CLKCTRL_XTAL + 0xc) +#define HWT_CLKCTRL_XTAL_TOG HWIO_32_WO +#define HWN_CLKCTRL_XTAL_TOG CLKCTRL_XTAL +#define HWI_CLKCTRL_XTAL_TOG +#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BF_CLKCTRL_XTAL_UART_CLK_GATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_XTAL_UART_CLK_GATE(v) BM_CLKCTRL_XTAL_UART_CLK_GATE +#define BF_CLKCTRL_XTAL_UART_CLK_GATE_V(e) BF_CLKCTRL_XTAL_UART_CLK_GATE(BV_CLKCTRL_XTAL_UART_CLK_GATE__##e) +#define BFM_CLKCTRL_XTAL_UART_CLK_GATE_V(v) BM_CLKCTRL_XTAL_UART_CLK_GATE +#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 +#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 +#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE(v) BM_CLKCTRL_XTAL_FILT_CLK24M_GATE +#define BF_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(e) BF_CLKCTRL_XTAL_FILT_CLK24M_GATE(BV_CLKCTRL_XTAL_FILT_CLK24M_GATE__##e) +#define BFM_CLKCTRL_XTAL_FILT_CLK24M_GATE_V(v) BM_CLKCTRL_XTAL_FILT_CLK24M_GATE +#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 +#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE(v) BM_CLKCTRL_XTAL_PWM_CLK24M_GATE +#define BF_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(e) BF_CLKCTRL_XTAL_PWM_CLK24M_GATE(BV_CLKCTRL_XTAL_PWM_CLK24M_GATE__##e) +#define BFM_CLKCTRL_XTAL_PWM_CLK24M_GATE_V(v) BM_CLKCTRL_XTAL_PWM_CLK24M_GATE +#define BP_CLKCTRL_XTAL_DRI_CLK24M_GATE 28 +#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 +#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) (((v) & 0x1) << 28) +#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE(v) BM_CLKCTRL_XTAL_DRI_CLK24M_GATE +#define BF_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(e) BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(BV_CLKCTRL_XTAL_DRI_CLK24M_GATE__##e) +#define BFM_CLKCTRL_XTAL_DRI_CLK24M_GATE_V(v) BM_CLKCTRL_XTAL_DRI_CLK24M_GATE +#define BP_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 27 +#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x8000000 +#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) (((v) & 0x1) << 27) +#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(v) BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE +#define BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(e) BF_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE(BV_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE__##e) +#define BFM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE_V(v) BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE +#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x4000000 +#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) (((v) & 0x1) << 26) +#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(v) BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE +#define BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(e) BF_CLKCTRL_XTAL_TIMROT_CLK32K_GATE(BV_CLKCTRL_XTAL_TIMROT_CLK32K_GATE__##e) +#define BFM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE_V(v) BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x3fffffc +#define BF_CLKCTRL_XTAL_RSRVD1(v) (((v) & 0xffffff) << 2) +#define BFM_CLKCTRL_XTAL_RSRVD1(v) BM_CLKCTRL_XTAL_RSRVD1 +#define BF_CLKCTRL_XTAL_RSRVD1_V(e) BF_CLKCTRL_XTAL_RSRVD1(BV_CLKCTRL_XTAL_RSRVD1__##e) +#define BFM_CLKCTRL_XTAL_RSRVD1_V(v) BM_CLKCTRL_XTAL_RSRVD1 +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x3 +#define BF_CLKCTRL_XTAL_DIV_UART(v) (((v) & 0x3) << 0) +#define BFM_CLKCTRL_XTAL_DIV_UART(v) BM_CLKCTRL_XTAL_DIV_UART +#define BF_CLKCTRL_XTAL_DIV_UART_V(e) BF_CLKCTRL_XTAL_DIV_UART(BV_CLKCTRL_XTAL_DIV_UART__##e) +#define BFM_CLKCTRL_XTAL_DIV_UART_V(v) BM_CLKCTRL_XTAL_DIV_UART + +#define HW_CLKCTRL_PIX HW(CLKCTRL_PIX) +#define HWA_CLKCTRL_PIX (0x80040000 + 0x60) +#define HWT_CLKCTRL_PIX HWIO_32_RW +#define HWN_CLKCTRL_PIX CLKCTRL_PIX +#define HWI_CLKCTRL_PIX +#define BP_CLKCTRL_PIX_CLKGATE 31 +#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 +#define BF_CLKCTRL_PIX_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_PIX_CLKGATE(v) BM_CLKCTRL_PIX_CLKGATE +#define BF_CLKCTRL_PIX_CLKGATE_V(e) BF_CLKCTRL_PIX_CLKGATE(BV_CLKCTRL_PIX_CLKGATE__##e) +#define BFM_CLKCTRL_PIX_CLKGATE_V(v) BM_CLKCTRL_PIX_CLKGATE +#define BP_CLKCTRL_PIX_RSRVD2 30 +#define BM_CLKCTRL_PIX_RSRVD2 0x40000000 +#define BF_CLKCTRL_PIX_RSRVD2(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_PIX_RSRVD2(v) BM_CLKCTRL_PIX_RSRVD2 +#define BF_CLKCTRL_PIX_RSRVD2_V(e) BF_CLKCTRL_PIX_RSRVD2(BV_CLKCTRL_PIX_RSRVD2__##e) +#define BFM_CLKCTRL_PIX_RSRVD2_V(v) BM_CLKCTRL_PIX_RSRVD2 +#define BP_CLKCTRL_PIX_BUSY 29 +#define BM_CLKCTRL_PIX_BUSY 0x20000000 +#define BF_CLKCTRL_PIX_BUSY(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_PIX_BUSY(v) BM_CLKCTRL_PIX_BUSY +#define BF_CLKCTRL_PIX_BUSY_V(e) BF_CLKCTRL_PIX_BUSY(BV_CLKCTRL_PIX_BUSY__##e) +#define BFM_CLKCTRL_PIX_BUSY_V(v) BM_CLKCTRL_PIX_BUSY +#define BP_CLKCTRL_PIX_RSRVD1 13 +#define BM_CLKCTRL_PIX_RSRVD1 0x1fffe000 +#define BF_CLKCTRL_PIX_RSRVD1(v) (((v) & 0xffff) << 13) +#define BFM_CLKCTRL_PIX_RSRVD1(v) BM_CLKCTRL_PIX_RSRVD1 +#define BF_CLKCTRL_PIX_RSRVD1_V(e) BF_CLKCTRL_PIX_RSRVD1(BV_CLKCTRL_PIX_RSRVD1__##e) +#define BFM_CLKCTRL_PIX_RSRVD1_V(v) BM_CLKCTRL_PIX_RSRVD1 +#define BP_CLKCTRL_PIX_DIV_FRAC_EN 12 +#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x1000 +#define BF_CLKCTRL_PIX_DIV_FRAC_EN(v) (((v) & 0x1) << 12) +#define BFM_CLKCTRL_PIX_DIV_FRAC_EN(v) BM_CLKCTRL_PIX_DIV_FRAC_EN +#define BF_CLKCTRL_PIX_DIV_FRAC_EN_V(e) BF_CLKCTRL_PIX_DIV_FRAC_EN(BV_CLKCTRL_PIX_DIV_FRAC_EN__##e) +#define BFM_CLKCTRL_PIX_DIV_FRAC_EN_V(v) BM_CLKCTRL_PIX_DIV_FRAC_EN +#define BP_CLKCTRL_PIX_DIV 0 +#define BM_CLKCTRL_PIX_DIV 0xfff +#define BF_CLKCTRL_PIX_DIV(v) (((v) & 0xfff) << 0) +#define BFM_CLKCTRL_PIX_DIV(v) BM_CLKCTRL_PIX_DIV +#define BF_CLKCTRL_PIX_DIV_V(e) BF_CLKCTRL_PIX_DIV(BV_CLKCTRL_PIX_DIV__##e) +#define BFM_CLKCTRL_PIX_DIV_V(v) BM_CLKCTRL_PIX_DIV + +#define HW_CLKCTRL_SSP HW(CLKCTRL_SSP) +#define HWA_CLKCTRL_SSP (0x80040000 + 0x70) +#define HWT_CLKCTRL_SSP HWIO_32_RW +#define HWN_CLKCTRL_SSP CLKCTRL_SSP +#define HWI_CLKCTRL_SSP +#define BP_CLKCTRL_SSP_CLKGATE 31 +#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 +#define BF_CLKCTRL_SSP_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_SSP_CLKGATE(v) BM_CLKCTRL_SSP_CLKGATE +#define BF_CLKCTRL_SSP_CLKGATE_V(e) BF_CLKCTRL_SSP_CLKGATE(BV_CLKCTRL_SSP_CLKGATE__##e) +#define BFM_CLKCTRL_SSP_CLKGATE_V(v) BM_CLKCTRL_SSP_CLKGATE +#define BP_CLKCTRL_SSP_RSRVD2 30 +#define BM_CLKCTRL_SSP_RSRVD2 0x40000000 +#define BF_CLKCTRL_SSP_RSRVD2(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_SSP_RSRVD2(v) BM_CLKCTRL_SSP_RSRVD2 +#define BF_CLKCTRL_SSP_RSRVD2_V(e) BF_CLKCTRL_SSP_RSRVD2(BV_CLKCTRL_SSP_RSRVD2__##e) +#define BFM_CLKCTRL_SSP_RSRVD2_V(v) BM_CLKCTRL_SSP_RSRVD2 +#define BP_CLKCTRL_SSP_BUSY 29 +#define BM_CLKCTRL_SSP_BUSY 0x20000000 +#define BF_CLKCTRL_SSP_BUSY(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_SSP_BUSY(v) BM_CLKCTRL_SSP_BUSY +#define BF_CLKCTRL_SSP_BUSY_V(e) BF_CLKCTRL_SSP_BUSY(BV_CLKCTRL_SSP_BUSY__##e) +#define BFM_CLKCTRL_SSP_BUSY_V(v) BM_CLKCTRL_SSP_BUSY +#define BP_CLKCTRL_SSP_RSRVD1 10 +#define BM_CLKCTRL_SSP_RSRVD1 0x1ffffc00 +#define BF_CLKCTRL_SSP_RSRVD1(v) (((v) & 0x7ffff) << 10) +#define BFM_CLKCTRL_SSP_RSRVD1(v) BM_CLKCTRL_SSP_RSRVD1 +#define BF_CLKCTRL_SSP_RSRVD1_V(e) BF_CLKCTRL_SSP_RSRVD1(BV_CLKCTRL_SSP_RSRVD1__##e) +#define BFM_CLKCTRL_SSP_RSRVD1_V(v) BM_CLKCTRL_SSP_RSRVD1 +#define BP_CLKCTRL_SSP_DIV_FRAC_EN 9 +#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x200 +#define BF_CLKCTRL_SSP_DIV_FRAC_EN(v) (((v) & 0x1) << 9) +#define BFM_CLKCTRL_SSP_DIV_FRAC_EN(v) BM_CLKCTRL_SSP_DIV_FRAC_EN +#define BF_CLKCTRL_SSP_DIV_FRAC_EN_V(e) BF_CLKCTRL_SSP_DIV_FRAC_EN(BV_CLKCTRL_SSP_DIV_FRAC_EN__##e) +#define BFM_CLKCTRL_SSP_DIV_FRAC_EN_V(v) BM_CLKCTRL_SSP_DIV_FRAC_EN +#define BP_CLKCTRL_SSP_DIV 0 +#define BM_CLKCTRL_SSP_DIV 0x1ff +#define BF_CLKCTRL_SSP_DIV(v) (((v) & 0x1ff) << 0) +#define BFM_CLKCTRL_SSP_DIV(v) BM_CLKCTRL_SSP_DIV +#define BF_CLKCTRL_SSP_DIV_V(e) BF_CLKCTRL_SSP_DIV(BV_CLKCTRL_SSP_DIV__##e) +#define BFM_CLKCTRL_SSP_DIV_V(v) BM_CLKCTRL_SSP_DIV + +#define HW_CLKCTRL_GPMI HW(CLKCTRL_GPMI) +#define HWA_CLKCTRL_GPMI (0x80040000 + 0x80) +#define HWT_CLKCTRL_GPMI HWIO_32_RW +#define HWN_CLKCTRL_GPMI CLKCTRL_GPMI +#define HWI_CLKCTRL_GPMI +#define BP_CLKCTRL_GPMI_CLKGATE 31 +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BF_CLKCTRL_GPMI_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_GPMI_CLKGATE(v) BM_CLKCTRL_GPMI_CLKGATE +#define BF_CLKCTRL_GPMI_CLKGATE_V(e) BF_CLKCTRL_GPMI_CLKGATE(BV_CLKCTRL_GPMI_CLKGATE__##e) +#define BFM_CLKCTRL_GPMI_CLKGATE_V(v) BM_CLKCTRL_GPMI_CLKGATE +#define BP_CLKCTRL_GPMI_RSRVD2 30 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BF_CLKCTRL_GPMI_RSRVD2(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_GPMI_RSRVD2(v) BM_CLKCTRL_GPMI_RSRVD2 +#define BF_CLKCTRL_GPMI_RSRVD2_V(e) BF_CLKCTRL_GPMI_RSRVD2(BV_CLKCTRL_GPMI_RSRVD2__##e) +#define BFM_CLKCTRL_GPMI_RSRVD2_V(v) BM_CLKCTRL_GPMI_RSRVD2 +#define BP_CLKCTRL_GPMI_BUSY 29 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BF_CLKCTRL_GPMI_BUSY(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_GPMI_BUSY(v) BM_CLKCTRL_GPMI_BUSY +#define BF_CLKCTRL_GPMI_BUSY_V(e) BF_CLKCTRL_GPMI_BUSY(BV_CLKCTRL_GPMI_BUSY__##e) +#define BFM_CLKCTRL_GPMI_BUSY_V(v) BM_CLKCTRL_GPMI_BUSY +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1ffff800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) (((v) & 0x3ffff) << 11) +#define BFM_CLKCTRL_GPMI_RSRVD1(v) BM_CLKCTRL_GPMI_RSRVD1 +#define BF_CLKCTRL_GPMI_RSRVD1_V(e) BF_CLKCTRL_GPMI_RSRVD1(BV_CLKCTRL_GPMI_RSRVD1__##e) +#define BFM_CLKCTRL_GPMI_RSRVD1_V(v) BM_CLKCTRL_GPMI_RSRVD1 +#define BP_CLKCTRL_GPMI_DIV_FRAC_EN 10 +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x400 +#define BF_CLKCTRL_GPMI_DIV_FRAC_EN(v) (((v) & 0x1) << 10) +#define BFM_CLKCTRL_GPMI_DIV_FRAC_EN(v) BM_CLKCTRL_GPMI_DIV_FRAC_EN +#define BF_CLKCTRL_GPMI_DIV_FRAC_EN_V(e) BF_CLKCTRL_GPMI_DIV_FRAC_EN(BV_CLKCTRL_GPMI_DIV_FRAC_EN__##e) +#define BFM_CLKCTRL_GPMI_DIV_FRAC_EN_V(v) BM_CLKCTRL_GPMI_DIV_FRAC_EN +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x3ff +#define BF_CLKCTRL_GPMI_DIV(v) (((v) & 0x3ff) << 0) +#define BFM_CLKCTRL_GPMI_DIV(v) BM_CLKCTRL_GPMI_DIV +#define BF_CLKCTRL_GPMI_DIV_V(e) BF_CLKCTRL_GPMI_DIV(BV_CLKCTRL_GPMI_DIV__##e) +#define BFM_CLKCTRL_GPMI_DIV_V(v) BM_CLKCTRL_GPMI_DIV + +#define HW_CLKCTRL_SPDIF HW(CLKCTRL_SPDIF) +#define HWA_CLKCTRL_SPDIF (0x80040000 + 0x90) +#define HWT_CLKCTRL_SPDIF HWIO_32_RW +#define HWN_CLKCTRL_SPDIF CLKCTRL_SPDIF +#define HWI_CLKCTRL_SPDIF +#define BP_CLKCTRL_SPDIF_CLKGATE 31 +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BF_CLKCTRL_SPDIF_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_SPDIF_CLKGATE(v) BM_CLKCTRL_SPDIF_CLKGATE +#define BF_CLKCTRL_SPDIF_CLKGATE_V(e) BF_CLKCTRL_SPDIF_CLKGATE(BV_CLKCTRL_SPDIF_CLKGATE__##e) +#define BFM_CLKCTRL_SPDIF_CLKGATE_V(v) BM_CLKCTRL_SPDIF_CLKGATE +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7fffffff +#define BF_CLKCTRL_SPDIF_RSRVD(v) (((v) & 0x7fffffff) << 0) +#define BFM_CLKCTRL_SPDIF_RSRVD(v) BM_CLKCTRL_SPDIF_RSRVD +#define BF_CLKCTRL_SPDIF_RSRVD_V(e) BF_CLKCTRL_SPDIF_RSRVD(BV_CLKCTRL_SPDIF_RSRVD__##e) +#define BFM_CLKCTRL_SPDIF_RSRVD_V(v) BM_CLKCTRL_SPDIF_RSRVD + +#define HW_CLKCTRL_EMI HW(CLKCTRL_EMI) +#define HWA_CLKCTRL_EMI (0x80040000 + 0xa0) +#define HWT_CLKCTRL_EMI HWIO_32_RW +#define HWN_CLKCTRL_EMI CLKCTRL_EMI +#define HWI_CLKCTRL_EMI +#define BP_CLKCTRL_EMI_CLKGATE 31 +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BF_CLKCTRL_EMI_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_EMI_CLKGATE(v) BM_CLKCTRL_EMI_CLKGATE +#define BF_CLKCTRL_EMI_CLKGATE_V(e) BF_CLKCTRL_EMI_CLKGATE(BV_CLKCTRL_EMI_CLKGATE__##e) +#define BFM_CLKCTRL_EMI_CLKGATE_V(v) BM_CLKCTRL_EMI_CLKGATE +#define BP_CLKCTRL_EMI_SYNC_MODE_EN 30 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 +#define BF_CLKCTRL_EMI_SYNC_MODE_EN(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_EMI_SYNC_MODE_EN(v) BM_CLKCTRL_EMI_SYNC_MODE_EN +#define BF_CLKCTRL_EMI_SYNC_MODE_EN_V(e) BF_CLKCTRL_EMI_SYNC_MODE_EN(BV_CLKCTRL_EMI_SYNC_MODE_EN__##e) +#define BFM_CLKCTRL_EMI_SYNC_MODE_EN_V(v) BM_CLKCTRL_EMI_SYNC_MODE_EN +#define BP_CLKCTRL_EMI_BUSY_REF_XTAL 29 +#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BF_CLKCTRL_EMI_BUSY_REF_XTAL(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_EMI_BUSY_REF_XTAL(v) BM_CLKCTRL_EMI_BUSY_REF_XTAL +#define BF_CLKCTRL_EMI_BUSY_REF_XTAL_V(e) BF_CLKCTRL_EMI_BUSY_REF_XTAL(BV_CLKCTRL_EMI_BUSY_REF_XTAL__##e) +#define BFM_CLKCTRL_EMI_BUSY_REF_XTAL_V(v) BM_CLKCTRL_EMI_BUSY_REF_XTAL +#define BP_CLKCTRL_EMI_BUSY_REF_EMI 28 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BF_CLKCTRL_EMI_BUSY_REF_EMI(v) (((v) & 0x1) << 28) +#define BFM_CLKCTRL_EMI_BUSY_REF_EMI(v) BM_CLKCTRL_EMI_BUSY_REF_EMI +#define BF_CLKCTRL_EMI_BUSY_REF_EMI_V(e) BF_CLKCTRL_EMI_BUSY_REF_EMI(BV_CLKCTRL_EMI_BUSY_REF_EMI__##e) +#define BFM_CLKCTRL_EMI_BUSY_REF_EMI_V(v) BM_CLKCTRL_EMI_BUSY_REF_EMI +#define BP_CLKCTRL_EMI_BUSY_REF_CPU 27 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x8000000 +#define BF_CLKCTRL_EMI_BUSY_REF_CPU(v) (((v) & 0x1) << 27) +#define BFM_CLKCTRL_EMI_BUSY_REF_CPU(v) BM_CLKCTRL_EMI_BUSY_REF_CPU +#define BF_CLKCTRL_EMI_BUSY_REF_CPU_V(e) BF_CLKCTRL_EMI_BUSY_REF_CPU(BV_CLKCTRL_EMI_BUSY_REF_CPU__##e) +#define BFM_CLKCTRL_EMI_BUSY_REF_CPU_V(v) BM_CLKCTRL_EMI_BUSY_REF_CPU +#define BP_CLKCTRL_EMI_BUSY_SYNC_MODE 26 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x4000000 +#define BF_CLKCTRL_EMI_BUSY_SYNC_MODE(v) (((v) & 0x1) << 26) +#define BFM_CLKCTRL_EMI_BUSY_SYNC_MODE(v) BM_CLKCTRL_EMI_BUSY_SYNC_MODE +#define BF_CLKCTRL_EMI_BUSY_SYNC_MODE_V(e) BF_CLKCTRL_EMI_BUSY_SYNC_MODE(BV_CLKCTRL_EMI_BUSY_SYNC_MODE__##e) +#define BFM_CLKCTRL_EMI_BUSY_SYNC_MODE_V(v) BM_CLKCTRL_EMI_BUSY_SYNC_MODE +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x3fc0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) (((v) & 0xff) << 18) +#define BFM_CLKCTRL_EMI_RSRVD3(v) BM_CLKCTRL_EMI_RSRVD3 +#define BF_CLKCTRL_EMI_RSRVD3_V(e) BF_CLKCTRL_EMI_RSRVD3(BV_CLKCTRL_EMI_RSRVD3__##e) +#define BFM_CLKCTRL_EMI_RSRVD3_V(v) BM_CLKCTRL_EMI_RSRVD3 +#define BP_CLKCTRL_EMI_BUSY_DCC_RESYNC 17 +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x20000 +#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(v) (((v) & 0x1) << 17) +#define BFM_CLKCTRL_EMI_BUSY_DCC_RESYNC(v) BM_CLKCTRL_EMI_BUSY_DCC_RESYNC +#define BF_CLKCTRL_EMI_BUSY_DCC_RESYNC_V(e) BF_CLKCTRL_EMI_BUSY_DCC_RESYNC(BV_CLKCTRL_EMI_BUSY_DCC_RESYNC__##e) +#define BFM_CLKCTRL_EMI_BUSY_DCC_RESYNC_V(v) BM_CLKCTRL_EMI_BUSY_DCC_RESYNC +#define BP_CLKCTRL_EMI_DCC_RESYNC_ENABLE 16 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x10000 +#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) (((v) & 0x1) << 16) +#define BFM_CLKCTRL_EMI_DCC_RESYNC_ENABLE(v) BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE +#define BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE_V(e) BF_CLKCTRL_EMI_DCC_RESYNC_ENABLE(BV_CLKCTRL_EMI_DCC_RESYNC_ENABLE__##e) +#define BFM_CLKCTRL_EMI_DCC_RESYNC_ENABLE_V(v) BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0xf000 +#define BF_CLKCTRL_EMI_RSRVD2(v) (((v) & 0xf) << 12) +#define BFM_CLKCTRL_EMI_RSRVD2(v) BM_CLKCTRL_EMI_RSRVD2 +#define BF_CLKCTRL_EMI_RSRVD2_V(e) BF_CLKCTRL_EMI_RSRVD2(BV_CLKCTRL_EMI_RSRVD2__##e) +#define BFM_CLKCTRL_EMI_RSRVD2_V(v) BM_CLKCTRL_EMI_RSRVD2 +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0xf00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) (((v) & 0xf) << 8) +#define BFM_CLKCTRL_EMI_DIV_XTAL(v) BM_CLKCTRL_EMI_DIV_XTAL +#define BF_CLKCTRL_EMI_DIV_XTAL_V(e) BF_CLKCTRL_EMI_DIV_XTAL(BV_CLKCTRL_EMI_DIV_XTAL__##e) +#define BFM_CLKCTRL_EMI_DIV_XTAL_V(v) BM_CLKCTRL_EMI_DIV_XTAL +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0xc0 +#define BF_CLKCTRL_EMI_RSRVD1(v) (((v) & 0x3) << 6) +#define BFM_CLKCTRL_EMI_RSRVD1(v) BM_CLKCTRL_EMI_RSRVD1 +#define BF_CLKCTRL_EMI_RSRVD1_V(e) BF_CLKCTRL_EMI_RSRVD1(BV_CLKCTRL_EMI_RSRVD1__##e) +#define BFM_CLKCTRL_EMI_RSRVD1_V(v) BM_CLKCTRL_EMI_RSRVD1 +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x3f +#define BF_CLKCTRL_EMI_DIV_EMI(v) (((v) & 0x3f) << 0) +#define BFM_CLKCTRL_EMI_DIV_EMI(v) BM_CLKCTRL_EMI_DIV_EMI +#define BF_CLKCTRL_EMI_DIV_EMI_V(e) BF_CLKCTRL_EMI_DIV_EMI(BV_CLKCTRL_EMI_DIV_EMI__##e) +#define BFM_CLKCTRL_EMI_DIV_EMI_V(v) BM_CLKCTRL_EMI_DIV_EMI + +#define HW_CLKCTRL_IR HW(CLKCTRL_IR) +#define HWA_CLKCTRL_IR (0x80040000 + 0xb0) +#define HWT_CLKCTRL_IR HWIO_32_RW +#define HWN_CLKCTRL_IR CLKCTRL_IR +#define HWI_CLKCTRL_IR +#define BP_CLKCTRL_IR_CLKGATE 31 +#define BM_CLKCTRL_IR_CLKGATE 0x80000000 +#define BF_CLKCTRL_IR_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_IR_CLKGATE(v) BM_CLKCTRL_IR_CLKGATE +#define BF_CLKCTRL_IR_CLKGATE_V(e) BF_CLKCTRL_IR_CLKGATE(BV_CLKCTRL_IR_CLKGATE__##e) +#define BFM_CLKCTRL_IR_CLKGATE_V(v) BM_CLKCTRL_IR_CLKGATE +#define BP_CLKCTRL_IR_RSRVD3 30 +#define BM_CLKCTRL_IR_RSRVD3 0x40000000 +#define BF_CLKCTRL_IR_RSRVD3(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_IR_RSRVD3(v) BM_CLKCTRL_IR_RSRVD3 +#define BF_CLKCTRL_IR_RSRVD3_V(e) BF_CLKCTRL_IR_RSRVD3(BV_CLKCTRL_IR_RSRVD3__##e) +#define BFM_CLKCTRL_IR_RSRVD3_V(v) BM_CLKCTRL_IR_RSRVD3 +#define BP_CLKCTRL_IR_AUTO_DIV 29 +#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 +#define BF_CLKCTRL_IR_AUTO_DIV(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_IR_AUTO_DIV(v) BM_CLKCTRL_IR_AUTO_DIV +#define BF_CLKCTRL_IR_AUTO_DIV_V(e) BF_CLKCTRL_IR_AUTO_DIV(BV_CLKCTRL_IR_AUTO_DIV__##e) +#define BFM_CLKCTRL_IR_AUTO_DIV_V(v) BM_CLKCTRL_IR_AUTO_DIV +#define BP_CLKCTRL_IR_IR_BUSY 28 +#define BM_CLKCTRL_IR_IR_BUSY 0x10000000 +#define BF_CLKCTRL_IR_IR_BUSY(v) (((v) & 0x1) << 28) +#define BFM_CLKCTRL_IR_IR_BUSY(v) BM_CLKCTRL_IR_IR_BUSY +#define BF_CLKCTRL_IR_IR_BUSY_V(e) BF_CLKCTRL_IR_IR_BUSY(BV_CLKCTRL_IR_IR_BUSY__##e) +#define BFM_CLKCTRL_IR_IR_BUSY_V(v) BM_CLKCTRL_IR_IR_BUSY +#define BP_CLKCTRL_IR_IROV_BUSY 27 +#define BM_CLKCTRL_IR_IROV_BUSY 0x8000000 +#define BF_CLKCTRL_IR_IROV_BUSY(v) (((v) & 0x1) << 27) +#define BFM_CLKCTRL_IR_IROV_BUSY(v) BM_CLKCTRL_IR_IROV_BUSY +#define BF_CLKCTRL_IR_IROV_BUSY_V(e) BF_CLKCTRL_IR_IROV_BUSY(BV_CLKCTRL_IR_IROV_BUSY__##e) +#define BFM_CLKCTRL_IR_IROV_BUSY_V(v) BM_CLKCTRL_IR_IROV_BUSY +#define BP_CLKCTRL_IR_RSRVD2 25 +#define BM_CLKCTRL_IR_RSRVD2 0x6000000 +#define BF_CLKCTRL_IR_RSRVD2(v) (((v) & 0x3) << 25) +#define BFM_CLKCTRL_IR_RSRVD2(v) BM_CLKCTRL_IR_RSRVD2 +#define BF_CLKCTRL_IR_RSRVD2_V(e) BF_CLKCTRL_IR_RSRVD2(BV_CLKCTRL_IR_RSRVD2__##e) +#define BFM_CLKCTRL_IR_RSRVD2_V(v) BM_CLKCTRL_IR_RSRVD2 +#define BP_CLKCTRL_IR_IROV_DIV 16 +#define BM_CLKCTRL_IR_IROV_DIV 0x1ff0000 +#define BF_CLKCTRL_IR_IROV_DIV(v) (((v) & 0x1ff) << 16) +#define BFM_CLKCTRL_IR_IROV_DIV(v) BM_CLKCTRL_IR_IROV_DIV +#define BF_CLKCTRL_IR_IROV_DIV_V(e) BF_CLKCTRL_IR_IROV_DIV(BV_CLKCTRL_IR_IROV_DIV__##e) +#define BFM_CLKCTRL_IR_IROV_DIV_V(v) BM_CLKCTRL_IR_IROV_DIV +#define BP_CLKCTRL_IR_RSRVD1 10 +#define BM_CLKCTRL_IR_RSRVD1 0xfc00 +#define BF_CLKCTRL_IR_RSRVD1(v) (((v) & 0x3f) << 10) +#define BFM_CLKCTRL_IR_RSRVD1(v) BM_CLKCTRL_IR_RSRVD1 +#define BF_CLKCTRL_IR_RSRVD1_V(e) BF_CLKCTRL_IR_RSRVD1(BV_CLKCTRL_IR_RSRVD1__##e) +#define BFM_CLKCTRL_IR_RSRVD1_V(v) BM_CLKCTRL_IR_RSRVD1 +#define BP_CLKCTRL_IR_IR_DIV 0 +#define BM_CLKCTRL_IR_IR_DIV 0x3ff +#define BF_CLKCTRL_IR_IR_DIV(v) (((v) & 0x3ff) << 0) +#define BFM_CLKCTRL_IR_IR_DIV(v) BM_CLKCTRL_IR_IR_DIV +#define BF_CLKCTRL_IR_IR_DIV_V(e) BF_CLKCTRL_IR_IR_DIV(BV_CLKCTRL_IR_IR_DIV__##e) +#define BFM_CLKCTRL_IR_IR_DIV_V(v) BM_CLKCTRL_IR_IR_DIV + +#define HW_CLKCTRL_SAIF HW(CLKCTRL_SAIF) +#define HWA_CLKCTRL_SAIF (0x80040000 + 0xc0) +#define HWT_CLKCTRL_SAIF HWIO_32_RW +#define HWN_CLKCTRL_SAIF CLKCTRL_SAIF +#define HWI_CLKCTRL_SAIF +#define BP_CLKCTRL_SAIF_CLKGATE 31 +#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 +#define BF_CLKCTRL_SAIF_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_SAIF_CLKGATE(v) BM_CLKCTRL_SAIF_CLKGATE +#define BF_CLKCTRL_SAIF_CLKGATE_V(e) BF_CLKCTRL_SAIF_CLKGATE(BV_CLKCTRL_SAIF_CLKGATE__##e) +#define BFM_CLKCTRL_SAIF_CLKGATE_V(v) BM_CLKCTRL_SAIF_CLKGATE +#define BP_CLKCTRL_SAIF_RSRVD2 30 +#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000 +#define BF_CLKCTRL_SAIF_RSRVD2(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_SAIF_RSRVD2(v) BM_CLKCTRL_SAIF_RSRVD2 +#define BF_CLKCTRL_SAIF_RSRVD2_V(e) BF_CLKCTRL_SAIF_RSRVD2(BV_CLKCTRL_SAIF_RSRVD2__##e) +#define BFM_CLKCTRL_SAIF_RSRVD2_V(v) BM_CLKCTRL_SAIF_RSRVD2 +#define BP_CLKCTRL_SAIF_BUSY 29 +#define BM_CLKCTRL_SAIF_BUSY 0x20000000 +#define BF_CLKCTRL_SAIF_BUSY(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_SAIF_BUSY(v) BM_CLKCTRL_SAIF_BUSY +#define BF_CLKCTRL_SAIF_BUSY_V(e) BF_CLKCTRL_SAIF_BUSY(BV_CLKCTRL_SAIF_BUSY__##e) +#define BFM_CLKCTRL_SAIF_BUSY_V(v) BM_CLKCTRL_SAIF_BUSY +#define BP_CLKCTRL_SAIF_RSRVD1 17 +#define BM_CLKCTRL_SAIF_RSRVD1 0x1ffe0000 +#define BF_CLKCTRL_SAIF_RSRVD1(v) (((v) & 0xfff) << 17) +#define BFM_CLKCTRL_SAIF_RSRVD1(v) BM_CLKCTRL_SAIF_RSRVD1 +#define BF_CLKCTRL_SAIF_RSRVD1_V(e) BF_CLKCTRL_SAIF_RSRVD1(BV_CLKCTRL_SAIF_RSRVD1__##e) +#define BFM_CLKCTRL_SAIF_RSRVD1_V(v) BM_CLKCTRL_SAIF_RSRVD1 +#define BP_CLKCTRL_SAIF_DIV_FRAC_EN 16 +#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x10000 +#define BF_CLKCTRL_SAIF_DIV_FRAC_EN(v) (((v) & 0x1) << 16) +#define BFM_CLKCTRL_SAIF_DIV_FRAC_EN(v) BM_CLKCTRL_SAIF_DIV_FRAC_EN +#define BF_CLKCTRL_SAIF_DIV_FRAC_EN_V(e) BF_CLKCTRL_SAIF_DIV_FRAC_EN(BV_CLKCTRL_SAIF_DIV_FRAC_EN__##e) +#define BFM_CLKCTRL_SAIF_DIV_FRAC_EN_V(v) BM_CLKCTRL_SAIF_DIV_FRAC_EN +#define BP_CLKCTRL_SAIF_DIV 0 +#define BM_CLKCTRL_SAIF_DIV 0xffff +#define BF_CLKCTRL_SAIF_DIV(v) (((v) & 0xffff) << 0) +#define BFM_CLKCTRL_SAIF_DIV(v) BM_CLKCTRL_SAIF_DIV +#define BF_CLKCTRL_SAIF_DIV_V(e) BF_CLKCTRL_SAIF_DIV(BV_CLKCTRL_SAIF_DIV__##e) +#define BFM_CLKCTRL_SAIF_DIV_V(v) BM_CLKCTRL_SAIF_DIV + +#define HW_CLKCTRL_TV HW(CLKCTRL_TV) +#define HWA_CLKCTRL_TV (0x80040000 + 0xd0) +#define HWT_CLKCTRL_TV HWIO_32_RW +#define HWN_CLKCTRL_TV CLKCTRL_TV +#define HWI_CLKCTRL_TV +#define BP_CLKCTRL_TV_CLK_TV108M_GATE 31 +#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 +#define BF_CLKCTRL_TV_CLK_TV108M_GATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_TV_CLK_TV108M_GATE(v) BM_CLKCTRL_TV_CLK_TV108M_GATE +#define BF_CLKCTRL_TV_CLK_TV108M_GATE_V(e) BF_CLKCTRL_TV_CLK_TV108M_GATE(BV_CLKCTRL_TV_CLK_TV108M_GATE__##e) +#define BFM_CLKCTRL_TV_CLK_TV108M_GATE_V(v) BM_CLKCTRL_TV_CLK_TV108M_GATE +#define BP_CLKCTRL_TV_CLK_TV_GATE 30 +#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 +#define BF_CLKCTRL_TV_CLK_TV_GATE(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_TV_CLK_TV_GATE(v) BM_CLKCTRL_TV_CLK_TV_GATE +#define BF_CLKCTRL_TV_CLK_TV_GATE_V(e) BF_CLKCTRL_TV_CLK_TV_GATE(BV_CLKCTRL_TV_CLK_TV_GATE__##e) +#define BFM_CLKCTRL_TV_CLK_TV_GATE_V(v) BM_CLKCTRL_TV_CLK_TV_GATE +#define BP_CLKCTRL_TV_RSRVD 0 +#define BM_CLKCTRL_TV_RSRVD 0x3fffffff +#define BF_CLKCTRL_TV_RSRVD(v) (((v) & 0x3fffffff) << 0) +#define BFM_CLKCTRL_TV_RSRVD(v) BM_CLKCTRL_TV_RSRVD +#define BF_CLKCTRL_TV_RSRVD_V(e) BF_CLKCTRL_TV_RSRVD(BV_CLKCTRL_TV_RSRVD__##e) +#define BFM_CLKCTRL_TV_RSRVD_V(v) BM_CLKCTRL_TV_RSRVD + +#define HW_CLKCTRL_ETM HW(CLKCTRL_ETM) +#define HWA_CLKCTRL_ETM (0x80040000 + 0xe0) +#define HWT_CLKCTRL_ETM HWIO_32_RW +#define HWN_CLKCTRL_ETM CLKCTRL_ETM +#define HWI_CLKCTRL_ETM +#define BP_CLKCTRL_ETM_CLKGATE 31 +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BF_CLKCTRL_ETM_CLKGATE(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_ETM_CLKGATE(v) BM_CLKCTRL_ETM_CLKGATE +#define BF_CLKCTRL_ETM_CLKGATE_V(e) BF_CLKCTRL_ETM_CLKGATE(BV_CLKCTRL_ETM_CLKGATE__##e) +#define BFM_CLKCTRL_ETM_CLKGATE_V(v) BM_CLKCTRL_ETM_CLKGATE +#define BP_CLKCTRL_ETM_RSRVD2 30 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BF_CLKCTRL_ETM_RSRVD2(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_ETM_RSRVD2(v) BM_CLKCTRL_ETM_RSRVD2 +#define BF_CLKCTRL_ETM_RSRVD2_V(e) BF_CLKCTRL_ETM_RSRVD2(BV_CLKCTRL_ETM_RSRVD2__##e) +#define BFM_CLKCTRL_ETM_RSRVD2_V(v) BM_CLKCTRL_ETM_RSRVD2 +#define BP_CLKCTRL_ETM_BUSY 29 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BF_CLKCTRL_ETM_BUSY(v) (((v) & 0x1) << 29) +#define BFM_CLKCTRL_ETM_BUSY(v) BM_CLKCTRL_ETM_BUSY +#define BF_CLKCTRL_ETM_BUSY_V(e) BF_CLKCTRL_ETM_BUSY(BV_CLKCTRL_ETM_BUSY__##e) +#define BFM_CLKCTRL_ETM_BUSY_V(v) BM_CLKCTRL_ETM_BUSY +#define BP_CLKCTRL_ETM_RSRVD1 7 +#define BM_CLKCTRL_ETM_RSRVD1 0x1fffff80 +#define BF_CLKCTRL_ETM_RSRVD1(v) (((v) & 0x3fffff) << 7) +#define BFM_CLKCTRL_ETM_RSRVD1(v) BM_CLKCTRL_ETM_RSRVD1 +#define BF_CLKCTRL_ETM_RSRVD1_V(e) BF_CLKCTRL_ETM_RSRVD1(BV_CLKCTRL_ETM_RSRVD1__##e) +#define BFM_CLKCTRL_ETM_RSRVD1_V(v) BM_CLKCTRL_ETM_RSRVD1 +#define BP_CLKCTRL_ETM_DIV_FRAC_EN 6 +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x40 +#define BF_CLKCTRL_ETM_DIV_FRAC_EN(v) (((v) & 0x1) << 6) +#define BFM_CLKCTRL_ETM_DIV_FRAC_EN(v) BM_CLKCTRL_ETM_DIV_FRAC_EN +#define BF_CLKCTRL_ETM_DIV_FRAC_EN_V(e) BF_CLKCTRL_ETM_DIV_FRAC_EN(BV_CLKCTRL_ETM_DIV_FRAC_EN__##e) +#define BFM_CLKCTRL_ETM_DIV_FRAC_EN_V(v) BM_CLKCTRL_ETM_DIV_FRAC_EN +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x3f +#define BF_CLKCTRL_ETM_DIV(v) (((v) & 0x3f) << 0) +#define BFM_CLKCTRL_ETM_DIV(v) BM_CLKCTRL_ETM_DIV +#define BF_CLKCTRL_ETM_DIV_V(e) BF_CLKCTRL_ETM_DIV(BV_CLKCTRL_ETM_DIV__##e) +#define BFM_CLKCTRL_ETM_DIV_V(v) BM_CLKCTRL_ETM_DIV + +#define HW_CLKCTRL_FRAC HW(CLKCTRL_FRAC) +#define HWA_CLKCTRL_FRAC (0x80040000 + 0xf0) +#define HWT_CLKCTRL_FRAC HWIO_32_RW +#define HWN_CLKCTRL_FRAC CLKCTRL_FRAC +#define HWI_CLKCTRL_FRAC +#define HW_CLKCTRL_FRAC_SET HW(CLKCTRL_FRAC_SET) +#define HWA_CLKCTRL_FRAC_SET (HWA_CLKCTRL_FRAC + 0x4) +#define HWT_CLKCTRL_FRAC_SET HWIO_32_WO +#define HWN_CLKCTRL_FRAC_SET CLKCTRL_FRAC +#define HWI_CLKCTRL_FRAC_SET +#define HW_CLKCTRL_FRAC_CLR HW(CLKCTRL_FRAC_CLR) +#define HWA_CLKCTRL_FRAC_CLR (HWA_CLKCTRL_FRAC + 0x8) +#define HWT_CLKCTRL_FRAC_CLR HWIO_32_WO +#define HWN_CLKCTRL_FRAC_CLR CLKCTRL_FRAC +#define HWI_CLKCTRL_FRAC_CLR +#define HW_CLKCTRL_FRAC_TOG HW(CLKCTRL_FRAC_TOG) +#define HWA_CLKCTRL_FRAC_TOG (HWA_CLKCTRL_FRAC + 0xc) +#define HWT_CLKCTRL_FRAC_TOG HWIO_32_WO +#define HWN_CLKCTRL_FRAC_TOG CLKCTRL_FRAC +#define HWI_CLKCTRL_FRAC_TOG +#define BP_CLKCTRL_FRAC_CLKGATEIO 31 +#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 +#define BF_CLKCTRL_FRAC_CLKGATEIO(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_FRAC_CLKGATEIO(v) BM_CLKCTRL_FRAC_CLKGATEIO +#define BF_CLKCTRL_FRAC_CLKGATEIO_V(e) BF_CLKCTRL_FRAC_CLKGATEIO(BV_CLKCTRL_FRAC_CLKGATEIO__##e) +#define BFM_CLKCTRL_FRAC_CLKGATEIO_V(v) BM_CLKCTRL_FRAC_CLKGATEIO +#define BP_CLKCTRL_FRAC_IO_STABLE 30 +#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 +#define BF_CLKCTRL_FRAC_IO_STABLE(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_FRAC_IO_STABLE(v) BM_CLKCTRL_FRAC_IO_STABLE +#define BF_CLKCTRL_FRAC_IO_STABLE_V(e) BF_CLKCTRL_FRAC_IO_STABLE(BV_CLKCTRL_FRAC_IO_STABLE__##e) +#define BFM_CLKCTRL_FRAC_IO_STABLE_V(v) BM_CLKCTRL_FRAC_IO_STABLE +#define BP_CLKCTRL_FRAC_IOFRAC 24 +#define BM_CLKCTRL_FRAC_IOFRAC 0x3f000000 +#define BF_CLKCTRL_FRAC_IOFRAC(v) (((v) & 0x3f) << 24) +#define BFM_CLKCTRL_FRAC_IOFRAC(v) BM_CLKCTRL_FRAC_IOFRAC +#define BF_CLKCTRL_FRAC_IOFRAC_V(e) BF_CLKCTRL_FRAC_IOFRAC(BV_CLKCTRL_FRAC_IOFRAC__##e) +#define BFM_CLKCTRL_FRAC_IOFRAC_V(v) BM_CLKCTRL_FRAC_IOFRAC +#define BP_CLKCTRL_FRAC_CLKGATEPIX 23 +#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x800000 +#define BF_CLKCTRL_FRAC_CLKGATEPIX(v) (((v) & 0x1) << 23) +#define BFM_CLKCTRL_FRAC_CLKGATEPIX(v) BM_CLKCTRL_FRAC_CLKGATEPIX +#define BF_CLKCTRL_FRAC_CLKGATEPIX_V(e) BF_CLKCTRL_FRAC_CLKGATEPIX(BV_CLKCTRL_FRAC_CLKGATEPIX__##e) +#define BFM_CLKCTRL_FRAC_CLKGATEPIX_V(v) BM_CLKCTRL_FRAC_CLKGATEPIX +#define BP_CLKCTRL_FRAC_PIX_STABLE 22 +#define BM_CLKCTRL_FRAC_PIX_STABLE 0x400000 +#define BF_CLKCTRL_FRAC_PIX_STABLE(v) (((v) & 0x1) << 22) +#define BFM_CLKCTRL_FRAC_PIX_STABLE(v) BM_CLKCTRL_FRAC_PIX_STABLE +#define BF_CLKCTRL_FRAC_PIX_STABLE_V(e) BF_CLKCTRL_FRAC_PIX_STABLE(BV_CLKCTRL_FRAC_PIX_STABLE__##e) +#define BFM_CLKCTRL_FRAC_PIX_STABLE_V(v) BM_CLKCTRL_FRAC_PIX_STABLE +#define BP_CLKCTRL_FRAC_PIXFRAC 16 +#define BM_CLKCTRL_FRAC_PIXFRAC 0x3f0000 +#define BF_CLKCTRL_FRAC_PIXFRAC(v) (((v) & 0x3f) << 16) +#define BFM_CLKCTRL_FRAC_PIXFRAC(v) BM_CLKCTRL_FRAC_PIXFRAC +#define BF_CLKCTRL_FRAC_PIXFRAC_V(e) BF_CLKCTRL_FRAC_PIXFRAC(BV_CLKCTRL_FRAC_PIXFRAC__##e) +#define BFM_CLKCTRL_FRAC_PIXFRAC_V(v) BM_CLKCTRL_FRAC_PIXFRAC +#define BP_CLKCTRL_FRAC_CLKGATEEMI 15 +#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x8000 +#define BF_CLKCTRL_FRAC_CLKGATEEMI(v) (((v) & 0x1) << 15) +#define BFM_CLKCTRL_FRAC_CLKGATEEMI(v) BM_CLKCTRL_FRAC_CLKGATEEMI +#define BF_CLKCTRL_FRAC_CLKGATEEMI_V(e) BF_CLKCTRL_FRAC_CLKGATEEMI(BV_CLKCTRL_FRAC_CLKGATEEMI__##e) +#define BFM_CLKCTRL_FRAC_CLKGATEEMI_V(v) BM_CLKCTRL_FRAC_CLKGATEEMI +#define BP_CLKCTRL_FRAC_EMI_STABLE 14 +#define BM_CLKCTRL_FRAC_EMI_STABLE 0x4000 +#define BF_CLKCTRL_FRAC_EMI_STABLE(v) (((v) & 0x1) << 14) +#define BFM_CLKCTRL_FRAC_EMI_STABLE(v) BM_CLKCTRL_FRAC_EMI_STABLE +#define BF_CLKCTRL_FRAC_EMI_STABLE_V(e) BF_CLKCTRL_FRAC_EMI_STABLE(BV_CLKCTRL_FRAC_EMI_STABLE__##e) +#define BFM_CLKCTRL_FRAC_EMI_STABLE_V(v) BM_CLKCTRL_FRAC_EMI_STABLE +#define BP_CLKCTRL_FRAC_EMIFRAC 8 +#define BM_CLKCTRL_FRAC_EMIFRAC 0x3f00 +#define BF_CLKCTRL_FRAC_EMIFRAC(v) (((v) & 0x3f) << 8) +#define BFM_CLKCTRL_FRAC_EMIFRAC(v) BM_CLKCTRL_FRAC_EMIFRAC +#define BF_CLKCTRL_FRAC_EMIFRAC_V(e) BF_CLKCTRL_FRAC_EMIFRAC(BV_CLKCTRL_FRAC_EMIFRAC__##e) +#define BFM_CLKCTRL_FRAC_EMIFRAC_V(v) BM_CLKCTRL_FRAC_EMIFRAC +#define BP_CLKCTRL_FRAC_CLKGATECPU 7 +#define BM_CLKCTRL_FRAC_CLKGATECPU 0x80 +#define BF_CLKCTRL_FRAC_CLKGATECPU(v) (((v) & 0x1) << 7) +#define BFM_CLKCTRL_FRAC_CLKGATECPU(v) BM_CLKCTRL_FRAC_CLKGATECPU +#define BF_CLKCTRL_FRAC_CLKGATECPU_V(e) BF_CLKCTRL_FRAC_CLKGATECPU(BV_CLKCTRL_FRAC_CLKGATECPU__##e) +#define BFM_CLKCTRL_FRAC_CLKGATECPU_V(v) BM_CLKCTRL_FRAC_CLKGATECPU +#define BP_CLKCTRL_FRAC_CPU_STABLE 6 +#define BM_CLKCTRL_FRAC_CPU_STABLE 0x40 +#define BF_CLKCTRL_FRAC_CPU_STABLE(v) (((v) & 0x1) << 6) +#define BFM_CLKCTRL_FRAC_CPU_STABLE(v) BM_CLKCTRL_FRAC_CPU_STABLE +#define BF_CLKCTRL_FRAC_CPU_STABLE_V(e) BF_CLKCTRL_FRAC_CPU_STABLE(BV_CLKCTRL_FRAC_CPU_STABLE__##e) +#define BFM_CLKCTRL_FRAC_CPU_STABLE_V(v) BM_CLKCTRL_FRAC_CPU_STABLE +#define BP_CLKCTRL_FRAC_CPUFRAC 0 +#define BM_CLKCTRL_FRAC_CPUFRAC 0x3f +#define BF_CLKCTRL_FRAC_CPUFRAC(v) (((v) & 0x3f) << 0) +#define BFM_CLKCTRL_FRAC_CPUFRAC(v) BM_CLKCTRL_FRAC_CPUFRAC +#define BF_CLKCTRL_FRAC_CPUFRAC_V(e) BF_CLKCTRL_FRAC_CPUFRAC(BV_CLKCTRL_FRAC_CPUFRAC__##e) +#define BFM_CLKCTRL_FRAC_CPUFRAC_V(v) BM_CLKCTRL_FRAC_CPUFRAC + +#define HW_CLKCTRL_FRAC1 HW(CLKCTRL_FRAC1) +#define HWA_CLKCTRL_FRAC1 (0x80040000 + 0x100) +#define HWT_CLKCTRL_FRAC1 HWIO_32_RW +#define HWN_CLKCTRL_FRAC1 CLKCTRL_FRAC1 +#define HWI_CLKCTRL_FRAC1 +#define HW_CLKCTRL_FRAC1_SET HW(CLKCTRL_FRAC1_SET) +#define HWA_CLKCTRL_FRAC1_SET (HWA_CLKCTRL_FRAC1 + 0x4) +#define HWT_CLKCTRL_FRAC1_SET HWIO_32_WO +#define HWN_CLKCTRL_FRAC1_SET CLKCTRL_FRAC1 +#define HWI_CLKCTRL_FRAC1_SET +#define HW_CLKCTRL_FRAC1_CLR HW(CLKCTRL_FRAC1_CLR) +#define HWA_CLKCTRL_FRAC1_CLR (HWA_CLKCTRL_FRAC1 + 0x8) +#define HWT_CLKCTRL_FRAC1_CLR HWIO_32_WO +#define HWN_CLKCTRL_FRAC1_CLR CLKCTRL_FRAC1 +#define HWI_CLKCTRL_FRAC1_CLR +#define HW_CLKCTRL_FRAC1_TOG HW(CLKCTRL_FRAC1_TOG) +#define HWA_CLKCTRL_FRAC1_TOG (HWA_CLKCTRL_FRAC1 + 0xc) +#define HWT_CLKCTRL_FRAC1_TOG HWIO_32_WO +#define HWN_CLKCTRL_FRAC1_TOG CLKCTRL_FRAC1 +#define HWI_CLKCTRL_FRAC1_TOG +#define BP_CLKCTRL_FRAC1_CLKGATEVID 31 +#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 +#define BF_CLKCTRL_FRAC1_CLKGATEVID(v) (((v) & 0x1) << 31) +#define BFM_CLKCTRL_FRAC1_CLKGATEVID(v) BM_CLKCTRL_FRAC1_CLKGATEVID +#define BF_CLKCTRL_FRAC1_CLKGATEVID_V(e) BF_CLKCTRL_FRAC1_CLKGATEVID(BV_CLKCTRL_FRAC1_CLKGATEVID__##e) +#define BFM_CLKCTRL_FRAC1_CLKGATEVID_V(v) BM_CLKCTRL_FRAC1_CLKGATEVID +#define BP_CLKCTRL_FRAC1_VID_STABLE 30 +#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 +#define BF_CLKCTRL_FRAC1_VID_STABLE(v) (((v) & 0x1) << 30) +#define BFM_CLKCTRL_FRAC1_VID_STABLE(v) BM_CLKCTRL_FRAC1_VID_STABLE +#define BF_CLKCTRL_FRAC1_VID_STABLE_V(e) BF_CLKCTRL_FRAC1_VID_STABLE(BV_CLKCTRL_FRAC1_VID_STABLE__##e) +#define BFM_CLKCTRL_FRAC1_VID_STABLE_V(v) BM_CLKCTRL_FRAC1_VID_STABLE +#define BP_CLKCTRL_FRAC1_RSRVD1 0 +#define BM_CLKCTRL_FRAC1_RSRVD1 0x3fffffff +#define BF_CLKCTRL_FRAC1_RSRVD1(v) (((v) & 0x3fffffff) << 0) +#define BFM_CLKCTRL_FRAC1_RSRVD1(v) BM_CLKCTRL_FRAC1_RSRVD1 +#define BF_CLKCTRL_FRAC1_RSRVD1_V(e) BF_CLKCTRL_FRAC1_RSRVD1(BV_CLKCTRL_FRAC1_RSRVD1__##e) +#define BFM_CLKCTRL_FRAC1_RSRVD1_V(v) BM_CLKCTRL_FRAC1_RSRVD1 + +#define HW_CLKCTRL_CLKSEQ HW(CLKCTRL_CLKSEQ) +#define HWA_CLKCTRL_CLKSEQ (0x80040000 + 0x110) +#define HWT_CLKCTRL_CLKSEQ HWIO_32_RW +#define HWN_CLKCTRL_CLKSEQ CLKCTRL_CLKSEQ +#define HWI_CLKCTRL_CLKSEQ +#define HW_CLKCTRL_CLKSEQ_SET HW(CLKCTRL_CLKSEQ_SET) +#define HWA_CLKCTRL_CLKSEQ_SET (HWA_CLKCTRL_CLKSEQ + 0x4) +#define HWT_CLKCTRL_CLKSEQ_SET HWIO_32_WO +#define HWN_CLKCTRL_CLKSEQ_SET CLKCTRL_CLKSEQ +#define HWI_CLKCTRL_CLKSEQ_SET +#define HW_CLKCTRL_CLKSEQ_CLR HW(CLKCTRL_CLKSEQ_CLR) +#define HWA_CLKCTRL_CLKSEQ_CLR (HWA_CLKCTRL_CLKSEQ + 0x8) +#define HWT_CLKCTRL_CLKSEQ_CLR HWIO_32_WO +#define HWN_CLKCTRL_CLKSEQ_CLR CLKCTRL_CLKSEQ +#define HWI_CLKCTRL_CLKSEQ_CLR +#define HW_CLKCTRL_CLKSEQ_TOG HW(CLKCTRL_CLKSEQ_TOG) +#define HWA_CLKCTRL_CLKSEQ_TOG (HWA_CLKCTRL_CLKSEQ + 0xc) +#define HWT_CLKCTRL_CLKSEQ_TOG HWIO_32_WO +#define HWN_CLKCTRL_CLKSEQ_TOG CLKCTRL_CLKSEQ +#define HWI_CLKCTRL_CLKSEQ_TOG +#define BP_CLKCTRL_CLKSEQ_RSRVD1 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xfffffe00 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) (((v) & 0x7fffff) << 9) +#define BFM_CLKCTRL_CLKSEQ_RSRVD1(v) BM_CLKCTRL_CLKSEQ_RSRVD1 +#define BF_CLKCTRL_CLKSEQ_RSRVD1_V(e) BF_CLKCTRL_CLKSEQ_RSRVD1(BV_CLKCTRL_CLKSEQ_RSRVD1__##e) +#define BFM_CLKCTRL_CLKSEQ_RSRVD1_V(v) BM_CLKCTRL_CLKSEQ_RSRVD1 +#define BP_CLKCTRL_CLKSEQ_BYPASS_ETM 8 +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x100 +#define BF_CLKCTRL_CLKSEQ_BYPASS_ETM(v) (((v) & 0x1) << 8) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_ETM(v) BM_CLKCTRL_CLKSEQ_BYPASS_ETM +#define BF_CLKCTRL_CLKSEQ_BYPASS_ETM_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_ETM(BV_CLKCTRL_CLKSEQ_BYPASS_ETM__##e) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_ETM_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_ETM +#define BP_CLKCTRL_CLKSEQ_BYPASS_CPU 7 +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x80 +#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU(v) (((v) & 0x1) << 7) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_CPU(v) BM_CLKCTRL_CLKSEQ_BYPASS_CPU +#define BF_CLKCTRL_CLKSEQ_BYPASS_CPU_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_CPU(BV_CLKCTRL_CLKSEQ_BYPASS_CPU__##e) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_CPU_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_CPU +#define BP_CLKCTRL_CLKSEQ_BYPASS_EMI 6 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x40 +#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI(v) (((v) & 0x1) << 6) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_EMI(v) BM_CLKCTRL_CLKSEQ_BYPASS_EMI +#define BF_CLKCTRL_CLKSEQ_BYPASS_EMI_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_EMI(BV_CLKCTRL_CLKSEQ_BYPASS_EMI__##e) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_EMI_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_EMI +#define BP_CLKCTRL_CLKSEQ_BYPASS_SSP 5 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x20 +#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP(v) (((v) & 0x1) << 5) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_SSP(v) BM_CLKCTRL_CLKSEQ_BYPASS_SSP +#define BF_CLKCTRL_CLKSEQ_BYPASS_SSP_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_SSP(BV_CLKCTRL_CLKSEQ_BYPASS_SSP__##e) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_SSP_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_SSP +#define BP_CLKCTRL_CLKSEQ_BYPASS_GPMI 4 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x10 +#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(v) (((v) & 0x1) << 4) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_GPMI(v) BM_CLKCTRL_CLKSEQ_BYPASS_GPMI +#define BF_CLKCTRL_CLKSEQ_BYPASS_GPMI_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_GPMI(BV_CLKCTRL_CLKSEQ_BYPASS_GPMI__##e) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_GPMI_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_GPMI +#define BP_CLKCTRL_CLKSEQ_BYPASS_IR 3 +#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x8 +#define BF_CLKCTRL_CLKSEQ_BYPASS_IR(v) (((v) & 0x1) << 3) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_IR(v) BM_CLKCTRL_CLKSEQ_BYPASS_IR +#define BF_CLKCTRL_CLKSEQ_BYPASS_IR_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_IR(BV_CLKCTRL_CLKSEQ_BYPASS_IR__##e) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_IR_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_IR +#define BP_CLKCTRL_CLKSEQ_RSRVD0 2 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x4 +#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) (((v) & 0x1) << 2) +#define BFM_CLKCTRL_CLKSEQ_RSRVD0(v) BM_CLKCTRL_CLKSEQ_RSRVD0 +#define BF_CLKCTRL_CLKSEQ_RSRVD0_V(e) BF_CLKCTRL_CLKSEQ_RSRVD0(BV_CLKCTRL_CLKSEQ_RSRVD0__##e) +#define BFM_CLKCTRL_CLKSEQ_RSRVD0_V(v) BM_CLKCTRL_CLKSEQ_RSRVD0 +#define BP_CLKCTRL_CLKSEQ_BYPASS_PIX 1 +#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x2 +#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX(v) (((v) & 0x1) << 1) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_PIX(v) BM_CLKCTRL_CLKSEQ_BYPASS_PIX +#define BF_CLKCTRL_CLKSEQ_BYPASS_PIX_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_PIX(BV_CLKCTRL_CLKSEQ_BYPASS_PIX__##e) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_PIX_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_PIX +#define BP_CLKCTRL_CLKSEQ_BYPASS_SAIF 0 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x1 +#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(v) (((v) & 0x1) << 0) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_SAIF(v) BM_CLKCTRL_CLKSEQ_BYPASS_SAIF +#define BF_CLKCTRL_CLKSEQ_BYPASS_SAIF_V(e) BF_CLKCTRL_CLKSEQ_BYPASS_SAIF(BV_CLKCTRL_CLKSEQ_BYPASS_SAIF__##e) +#define BFM_CLKCTRL_CLKSEQ_BYPASS_SAIF_V(v) BM_CLKCTRL_CLKSEQ_BYPASS_SAIF + +#define HW_CLKCTRL_RESET HW(CLKCTRL_RESET) +#define HWA_CLKCTRL_RESET (0x80040000 + 0x120) +#define HWT_CLKCTRL_RESET HWIO_32_RW +#define HWN_CLKCTRL_RESET CLKCTRL_RESET +#define HWI_CLKCTRL_RESET +#define BP_CLKCTRL_RESET_RSRVD 2 +#define BM_CLKCTRL_RESET_RSRVD 0xfffffffc +#define BF_CLKCTRL_RESET_RSRVD(v) (((v) & 0x3fffffff) << 2) +#define BFM_CLKCTRL_RESET_RSRVD(v) BM_CLKCTRL_RESET_RSRVD +#define BF_CLKCTRL_RESET_RSRVD_V(e) BF_CLKCTRL_RESET_RSRVD(BV_CLKCTRL_RESET_RSRVD__##e) +#define BFM_CLKCTRL_RESET_RSRVD_V(v) BM_CLKCTRL_RESET_RSRVD +#define BP_CLKCTRL_RESET_CHIP 1 +#define BM_CLKCTRL_RESET_CHIP 0x2 +#define BF_CLKCTRL_RESET_CHIP(v) (((v) & 0x1) << 1) +#define BFM_CLKCTRL_RESET_CHIP(v) BM_CLKCTRL_RESET_CHIP +#define BF_CLKCTRL_RESET_CHIP_V(e) BF_CLKCTRL_RESET_CHIP(BV_CLKCTRL_RESET_CHIP__##e) +#define BFM_CLKCTRL_RESET_CHIP_V(v) BM_CLKCTRL_RESET_CHIP +#define BP_CLKCTRL_RESET_DIG 0 +#define BM_CLKCTRL_RESET_DIG 0x1 +#define BF_CLKCTRL_RESET_DIG(v) (((v) & 0x1) << 0) +#define BFM_CLKCTRL_RESET_DIG(v) BM_CLKCTRL_RESET_DIG +#define BF_CLKCTRL_RESET_DIG_V(e) BF_CLKCTRL_RESET_DIG(BV_CLKCTRL_RESET_DIG__##e) +#define BFM_CLKCTRL_RESET_DIG_V(v) BM_CLKCTRL_RESET_DIG + +#define HW_CLKCTRL_STATUS HW(CLKCTRL_STATUS) +#define HWA_CLKCTRL_STATUS (0x80040000 + 0x130) +#define HWT_CLKCTRL_STATUS HWIO_32_RW +#define HWN_CLKCTRL_STATUS CLKCTRL_STATUS +#define HWI_CLKCTRL_STATUS +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xc0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) (((v) & 0x3) << 30) +#define BFM_CLKCTRL_STATUS_CPU_LIMIT(v) BM_CLKCTRL_STATUS_CPU_LIMIT +#define BF_CLKCTRL_STATUS_CPU_LIMIT_V(e) BF_CLKCTRL_STATUS_CPU_LIMIT(BV_CLKCTRL_STATUS_CPU_LIMIT__##e) +#define BFM_CLKCTRL_STATUS_CPU_LIMIT_V(v) BM_CLKCTRL_STATUS_CPU_LIMIT +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3fffffff +#define BF_CLKCTRL_STATUS_RSRVD(v) (((v) & 0x3fffffff) << 0) +#define BFM_CLKCTRL_STATUS_RSRVD(v) BM_CLKCTRL_STATUS_RSRVD +#define BF_CLKCTRL_STATUS_RSRVD_V(e) BF_CLKCTRL_STATUS_RSRVD(BV_CLKCTRL_STATUS_RSRVD__##e) +#define BFM_CLKCTRL_STATUS_RSRVD_V(v) BM_CLKCTRL_STATUS_RSRVD + +#define HW_CLKCTRL_VERSION HW(CLKCTRL_VERSION) +#define HWA_CLKCTRL_VERSION (0x80040000 + 0x140) +#define HWT_CLKCTRL_VERSION HWIO_32_RW +#define HWN_CLKCTRL_VERSION CLKCTRL_VERSION +#define HWI_CLKCTRL_VERSION +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xff000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) (((v) & 0xff) << 24) +#define BFM_CLKCTRL_VERSION_MAJOR(v) BM_CLKCTRL_VERSION_MAJOR +#define BF_CLKCTRL_VERSION_MAJOR_V(e) BF_CLKCTRL_VERSION_MAJOR(BV_CLKCTRL_VERSION_MAJOR__##e) +#define BFM_CLKCTRL_VERSION_MAJOR_V(v) BM_CLKCTRL_VERSION_MAJOR +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0xff0000 +#define BF_CLKCTRL_VERSION_MINOR(v) (((v) & 0xff) << 16) +#define BFM_CLKCTRL_VERSION_MINOR(v) BM_CLKCTRL_VERSION_MINOR +#define BF_CLKCTRL_VERSION_MINOR_V(e) BF_CLKCTRL_VERSION_MINOR(BV_CLKCTRL_VERSION_MINOR__##e) +#define BFM_CLKCTRL_VERSION_MINOR_V(v) BM_CLKCTRL_VERSION_MINOR +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0xffff +#define BF_CLKCTRL_VERSION_STEP(v) (((v) & 0xffff) << 0) +#define BFM_CLKCTRL_VERSION_STEP(v) BM_CLKCTRL_VERSION_STEP +#define BF_CLKCTRL_VERSION_STEP_V(e) BF_CLKCTRL_VERSION_STEP(BV_CLKCTRL_VERSION_STEP__##e) +#define BFM_CLKCTRL_VERSION_STEP_V(v) BM_CLKCTRL_VERSION_STEP + +#endif /* __HEADERGEN_IMX233_CLKCTRL_H__*/ diff --git a/firmware/target/arm/imx233/regs/imx233/dcp.h b/firmware/target/arm/imx233/regs/imx233/dcp.h new file mode 100644 index 0000000000..ec3cf123c8 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/dcp.h @@ -0,0 +1,1334 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * imx233 version: 2.4.0 + * imx233 authors: Amaury Pouly + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_IMX233_DCP_H__ +#define __HEADERGEN_IMX233_DCP_H__ + +#define HW_DCP_CTRL HW(DCP_CTRL) +#define HWA_DCP_CTRL (0x80028000 + 0x0) +#define HWT_DCP_CTRL HWIO_32_RW +#define HWN_DCP_CTRL DCP_CTRL +#define HWI_DCP_CTRL +#define HW_DCP_CTRL_SET HW(DCP_CTRL_SET) +#define HWA_DCP_CTRL_SET (HWA_DCP_CTRL + 0x4) +#define HWT_DCP_CTRL_SET HWIO_32_WO +#define HWN_DCP_CTRL_SET DCP_CTRL +#define HWI_DCP_CTRL_SET +#define HW_DCP_CTRL_CLR HW(DCP_CTRL_CLR) +#define HWA_DCP_CTRL_CLR (HWA_DCP_CTRL + 0x8) +#define HWT_DCP_CTRL_CLR HWIO_32_WO +#define HWN_DCP_CTRL_CLR DCP_CTRL +#define HWI_DCP_CTRL_CLR +#define HW_DCP_CTRL_TOG HW(DCP_CTRL_TOG) +#define HWA_DCP_CTRL_TOG (HWA_DCP_CTRL + 0xc) +#define HWT_DCP_CTRL_TOG HWIO_32_WO +#define HWN_DCP_CTRL_TOG DCP_CTRL +#define HWI_DCP_CTRL_TOG +#define BP_DCP_CTRL_SFTRST 31 +#define BM_DCP_CTRL_SFTRST 0x80000000 +#define BF_DCP_CTRL_SFTRST(v) (((v) & 0x1) << 31) +#define BFM_DCP_CTRL_SFTRST(v) BM_DCP_CTRL_SFTRST +#define BF_DCP_CTRL_SFTRST_V(e) BF_DCP_CTRL_SFTRST(BV_DCP_CTRL_SFTRST__##e) +#define BFM_DCP_CTRL_SFTRST_V(v) BM_DCP_CTRL_SFTRST +#define BP_DCP_CTRL_CLKGATE 30 +#define BM_DCP_CTRL_CLKGATE 0x40000000 +#define BF_DCP_CTRL_CLKGATE(v) (((v) & 0x1) << 30) +#define BFM_DCP_CTRL_CLKGATE(v) BM_DCP_CTRL_CLKGATE +#define BF_DCP_CTRL_CLKGATE_V(e) BF_DCP_CTRL_CLKGATE(BV_DCP_CTRL_CLKGATE__##e) +#define BFM_DCP_CTRL_CLKGATE_V(v) BM_DCP_CTRL_CLKGATE +#define BP_DCP_CTRL_PRESENT_CRYPTO 29 +#define BM_DCP_CTRL_PRESENT_CRYPTO 0x20000000 +#define BV_DCP_CTRL_PRESENT_CRYPTO__Present 0x1 +#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent 0x0 +#define BF_DCP_CTRL_PRESENT_CRYPTO(v) (((v) & 0x1) << 29) +#define BFM_DCP_CTRL_PRESENT_CRYPTO(v) BM_DCP_CTRL_PRESENT_CRYPTO +#define BF_DCP_CTRL_PRESENT_CRYPTO_V(e) BF_DCP_CTRL_PRESENT_CRYPTO(BV_DCP_CTRL_PRESENT_CRYPTO__##e) +#define BFM_DCP_CTRL_PRESENT_CRYPTO_V(v) BM_DCP_CTRL_PRESENT_CRYPTO +#define BP_DCP_CTRL_PRESENT_CSC 28 +#define BM_DCP_CTRL_PRESENT_CSC 0x10000000 +#define BV_DCP_CTRL_PRESENT_CSC__Present 0x1 +#define BV_DCP_CTRL_PRESENT_CSC__Absent 0x0 +#define BF_DCP_CTRL_PRESENT_CSC(v) (((v) & 0x1) << 28) +#define BFM_DCP_CTRL_PRESENT_CSC(v) BM_DCP_CTRL_PRESENT_CSC +#define BF_DCP_CTRL_PRESENT_CSC_V(e) BF_DCP_CTRL_PRESENT_CSC(BV_DCP_CTRL_PRESENT_CSC__##e) +#define BFM_DCP_CTRL_PRESENT_CSC_V(v) BM_DCP_CTRL_PRESENT_CSC +#define BP_DCP_CTRL_RSVD1 24 +#define BM_DCP_CTRL_RSVD1 0xf000000 +#define BF_DCP_CTRL_RSVD1(v) (((v) & 0xf) << 24) +#define BFM_DCP_CTRL_RSVD1(v) BM_DCP_CTRL_RSVD1 +#define BF_DCP_CTRL_RSVD1_V(e) BF_DCP_CTRL_RSVD1(BV_DCP_CTRL_RSVD1__##e) +#define BFM_DCP_CTRL_RSVD1_V(v) BM_DCP_CTRL_RSVD1 +#define BP_DCP_CTRL_GATHER_RESIDUAL_WRITES 23 +#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x800000 +#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(v) (((v) & 0x1) << 23) +#define BFM_DCP_CTRL_GATHER_RESIDUAL_WRITES(v) BM_DCP_CTRL_GATHER_RESIDUAL_WRITES +#define BF_DCP_CTRL_GATHER_RESIDUAL_WRITES_V(e) BF_DCP_CTRL_GATHER_RESIDUAL_WRITES(BV_DCP_CTRL_GATHER_RESIDUAL_WRITES__##e) +#define BFM_DCP_CTRL_GATHER_RESIDUAL_WRITES_V(v) BM_DCP_CTRL_GATHER_RESIDUAL_WRITES +#define BP_DCP_CTRL_ENABLE_CONTEXT_CACHING 22 +#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x400000 +#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(v) (((v) & 0x1) << 22) +#define BFM_DCP_CTRL_ENABLE_CONTEXT_CACHING(v) BM_DCP_CTRL_ENABLE_CONTEXT_CACHING +#define BF_DCP_CTRL_ENABLE_CONTEXT_CACHING_V(e) BF_DCP_CTRL_ENABLE_CONTEXT_CACHING(BV_DCP_CTRL_ENABLE_CONTEXT_CACHING__##e) +#define BFM_DCP_CTRL_ENABLE_CONTEXT_CACHING_V(v) BM_DCP_CTRL_ENABLE_CONTEXT_CACHING +#define BP_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 21 +#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 0x200000 +#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v) (((v) & 0x1) << 21) +#define BFM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(v) BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING +#define BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING_V(e) BF_DCP_CTRL_ENABLE_CONTEXT_SWITCHING(BV_DCP_CTRL_ENABLE_CONTEXT_SWITCHING__##e) +#define BFM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING_V(v) BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING +#define BP_DCP_CTRL_RSVD0 9 +#define BM_DCP_CTRL_RSVD0 0x1ffe00 +#define BF_DCP_CTRL_RSVD0(v) (((v) & 0xfff) << 9) +#define BFM_DCP_CTRL_RSVD0(v) BM_DCP_CTRL_RSVD0 +#define BF_DCP_CTRL_RSVD0_V(e) BF_DCP_CTRL_RSVD0(BV_DCP_CTRL_RSVD0__##e) +#define BFM_DCP_CTRL_RSVD0_V(v) BM_DCP_CTRL_RSVD0 +#define BP_DCP_CTRL_CSC_INTERRUPT_ENABLE 8 +#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE 0x100 +#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(v) (((v) & 0x1) << 8) +#define BFM_DCP_CTRL_CSC_INTERRUPT_ENABLE(v) BM_DCP_CTRL_CSC_INTERRUPT_ENABLE +#define BF_DCP_CTRL_CSC_INTERRUPT_ENABLE_V(e) BF_DCP_CTRL_CSC_INTERRUPT_ENABLE(BV_DCP_CTRL_CSC_INTERRUPT_ENABLE__##e) +#define BFM_DCP_CTRL_CSC_INTERRUPT_ENABLE_V(v) BM_DCP_CTRL_CSC_INTERRUPT_ENABLE +#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 +#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0xff +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 0x1 +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 0x2 +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 0x4 +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3 0x8 +#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v) (((v) & 0xff) << 0) +#define BFM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v) BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE +#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(e) BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__##e) +#define BFM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_V(v) BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE + +#define HW_DCP_STAT HW(DCP_STAT) +#define HWA_DCP_STAT (0x80028000 + 0x10) +#define HWT_DCP_STAT HWIO_32_RW +#define HWN_DCP_STAT DCP_STAT +#define HWI_DCP_STAT +#define HW_DCP_STAT_SET HW(DCP_STAT_SET) +#define HWA_DCP_STAT_SET (HWA_DCP_STAT + 0x4) +#define HWT_DCP_STAT_SET HWIO_32_WO +#define HWN_DCP_STAT_SET DCP_STAT +#define HWI_DCP_STAT_SET +#define HW_DCP_STAT_CLR HW(DCP_STAT_CLR) +#define HWA_DCP_STAT_CLR (HWA_DCP_STAT + 0x8) +#define HWT_DCP_STAT_CLR HWIO_32_WO +#define HWN_DCP_STAT_CLR DCP_STAT +#define HWI_DCP_STAT_CLR +#define HW_DCP_STAT_TOG HW(DCP_STAT_TOG) +#define HWA_DCP_STAT_TOG (HWA_DCP_STAT + 0xc) +#define HWT_DCP_STAT_TOG HWIO_32_WO +#define HWN_DCP_STAT_TOG DCP_STAT +#define HWI_DCP_STAT_TOG +#define BP_DCP_STAT_RSVD2 29 +#define BM_DCP_STAT_RSVD2 0xe0000000 +#define BF_DCP_STAT_RSVD2(v) (((v) & 0x7) << 29) +#define BFM_DCP_STAT_RSVD2(v) BM_DCP_STAT_RSVD2 +#define BF_DCP_STAT_RSVD2_V(e) BF_DCP_STAT_RSVD2(BV_DCP_STAT_RSVD2__##e) +#define BFM_DCP_STAT_RSVD2_V(v) BM_DCP_STAT_RSVD2 +#define BP_DCP_STAT_OTP_KEY_READY 28 +#define BM_DCP_STAT_OTP_KEY_READY 0x10000000 +#define BF_DCP_STAT_OTP_KEY_READY(v) (((v) & 0x1) << 28) +#define BFM_DCP_STAT_OTP_KEY_READY(v) BM_DCP_STAT_OTP_KEY_READY +#define BF_DCP_STAT_OTP_KEY_READY_V(e) BF_DCP_STAT_OTP_KEY_READY(BV_DCP_STAT_OTP_KEY_READY__##e) +#define BFM_DCP_STAT_OTP_KEY_READY_V(v) BM_DCP_STAT_OTP_KEY_READY +#define BP_DCP_STAT_CUR_CHANNEL 24 +#define BM_DCP_STAT_CUR_CHANNEL 0xf000000 +#define BV_DCP_STAT_CUR_CHANNEL__None 0x0 +#define BV_DCP_STAT_CUR_CHANNEL__CH0 0x1 +#define BV_DCP_STAT_CUR_CHANNEL__CH1 0x2 +#define BV_DCP_STAT_CUR_CHANNEL__CH2 0x3 +#define BV_DCP_STAT_CUR_CHANNEL__CH3 0x4 +#define BV_DCP_STAT_CUR_CHANNEL__CSC 0x8 +#define BF_DCP_STAT_CUR_CHANNEL(v) (((v) & 0xf) << 24) +#define BFM_DCP_STAT_CUR_CHANNEL(v) BM_DCP_STAT_CUR_CHANNEL +#define BF_DCP_STAT_CUR_CHANNEL_V(e) BF_DCP_STAT_CUR_CHANNEL(BV_DCP_STAT_CUR_CHANNEL__##e) +#define BFM_DCP_STAT_CUR_CHANNEL_V(v) BM_DCP_STAT_CUR_CHANNEL +#define BP_DCP_STAT_READY_CHANNELS 16 +#define BM_DCP_STAT_READY_CHANNELS 0xff0000 +#define BV_DCP_STAT_READY_CHANNELS__CH0 0x1 +#define BV_DCP_STAT_READY_CHANNELS__CH1 0x2 +#define BV_DCP_STAT_READY_CHANNELS__CH2 0x4 +#define BV_DCP_STAT_READY_CHANNELS__CH3 0x8 +#define BF_DCP_STAT_READY_CHANNELS(v) (((v) & 0xff) << 16) +#define BFM_DCP_STAT_READY_CHANNELS(v) BM_DCP_STAT_READY_CHANNELS +#define BF_DCP_STAT_READY_CHANNELS_V(e) BF_DCP_STAT_READY_CHANNELS(BV_DCP_STAT_READY_CHANNELS__##e) +#define BFM_DCP_STAT_READY_CHANNELS_V(v) BM_DCP_STAT_READY_CHANNELS +#define BP_DCP_STAT_RSVD1 9 +#define BM_DCP_STAT_RSVD1 0xfe00 +#define BF_DCP_STAT_RSVD1(v) (((v) & 0x7f) << 9) +#define BFM_DCP_STAT_RSVD1(v) BM_DCP_STAT_RSVD1 +#define BF_DCP_STAT_RSVD1_V(e) BF_DCP_STAT_RSVD1(BV_DCP_STAT_RSVD1__##e) +#define BFM_DCP_STAT_RSVD1_V(v) BM_DCP_STAT_RSVD1 +#define BP_DCP_STAT_CSCIRQ 8 +#define BM_DCP_STAT_CSCIRQ 0x100 +#define BF_DCP_STAT_CSCIRQ(v) (((v) & 0x1) << 8) +#define BFM_DCP_STAT_CSCIRQ(v) BM_DCP_STAT_CSCIRQ +#define BF_DCP_STAT_CSCIRQ_V(e) BF_DCP_STAT_CSCIRQ(BV_DCP_STAT_CSCIRQ__##e) +#define BFM_DCP_STAT_CSCIRQ_V(v) BM_DCP_STAT_CSCIRQ +#define BP_DCP_STAT_RSVD0 4 +#define BM_DCP_STAT_RSVD0 0xf0 +#define BF_DCP_STAT_RSVD0(v) (((v) & 0xf) << 4) +#define BFM_DCP_STAT_RSVD0(v) BM_DCP_STAT_RSVD0 +#define BF_DCP_STAT_RSVD0_V(e) BF_DCP_STAT_RSVD0(BV_DCP_STAT_RSVD0__##e) +#define BFM_DCP_STAT_RSVD0_V(v) BM_DCP_STAT_RSVD0 +#define BP_DCP_STAT_IRQ 0 +#define BM_DCP_STAT_IRQ 0xf +#define BF_DCP_STAT_IRQ(v) (((v) & 0xf) << 0) +#define BFM_DCP_STAT_IRQ(v) BM_DCP_STAT_IRQ +#define BF_DCP_STAT_IRQ_V(e) BF_DCP_STAT_IRQ(BV_DCP_STAT_IRQ__##e) +#define BFM_DCP_STAT_IRQ_V(v) BM_DCP_STAT_IRQ + +#define HW_DCP_CHANNELCTRL HW(DCP_CHANNELCTRL) +#define HWA_DCP_CHANNELCTRL (0x80028000 + 0x20) +#define HWT_DCP_CHANNELCTRL HWIO_32_RW +#define HWN_DCP_CHANNELCTRL DCP_CHANNELCTRL +#define HWI_DCP_CHANNELCTRL +#define HW_DCP_CHANNELCTRL_SET HW(DCP_CHANNELCTRL_SET) +#define HWA_DCP_CHANNELCTRL_SET (HWA_DCP_CHANNELCTRL + 0x4) +#define HWT_DCP_CHANNELCTRL_SET HWIO_32_WO +#define HWN_DCP_CHANNELCTRL_SET DCP_CHANNELCTRL +#define HWI_DCP_CHANNELCTRL_SET +#define HW_DCP_CHANNELCTRL_CLR HW(DCP_CHANNELCTRL_CLR) +#define HWA_DCP_CHANNELCTRL_CLR (HWA_DCP_CHANNELCTRL + 0x8) +#define HWT_DCP_CHANNELCTRL_CLR HWIO_32_WO +#define HWN_DCP_CHANNELCTRL_CLR DCP_CHANNELCTRL +#define HWI_DCP_CHANNELCTRL_CLR +#define HW_DCP_CHANNELCTRL_TOG HW(DCP_CHANNELCTRL_TOG) +#define HWA_DCP_CHANNELCTRL_TOG (HWA_DCP_CHANNELCTRL + 0xc) +#define HWT_DCP_CHANNELCTRL_TOG HWIO_32_WO +#define HWN_DCP_CHANNELCTRL_TOG DCP_CHANNELCTRL +#define HWI_DCP_CHANNELCTRL_TOG +#define BP_DCP_CHANNELCTRL_RSVD 19 +#define BM_DCP_CHANNELCTRL_RSVD 0xfff80000 +#define BF_DCP_CHANNELCTRL_RSVD(v) (((v) & 0x1fff) << 19) +#define BFM_DCP_CHANNELCTRL_RSVD(v) BM_DCP_CHANNELCTRL_RSVD +#define BF_DCP_CHANNELCTRL_RSVD_V(e) BF_DCP_CHANNELCTRL_RSVD(BV_DCP_CHANNELCTRL_RSVD__##e) +#define BFM_DCP_CHANNELCTRL_RSVD_V(v) BM_DCP_CHANNELCTRL_RSVD +#define BP_DCP_CHANNELCTRL_CSC_PRIORITY 17 +#define BM_DCP_CHANNELCTRL_CSC_PRIORITY 0x60000 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH 0x3 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED 0x2 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW 0x1 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND 0x0 +#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v) (((v) & 0x3) << 17) +#define BFM_DCP_CHANNELCTRL_CSC_PRIORITY(v) BM_DCP_CHANNELCTRL_CSC_PRIORITY +#define BF_DCP_CHANNELCTRL_CSC_PRIORITY_V(e) BF_DCP_CHANNELCTRL_CSC_PRIORITY(BV_DCP_CHANNELCTRL_CSC_PRIORITY__##e) +#define BFM_DCP_CHANNELCTRL_CSC_PRIORITY_V(v) BM_DCP_CHANNELCTRL_CSC_PRIORITY +#define BP_DCP_CHANNELCTRL_CH0_IRQ_MERGED 16 +#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED 0x10000 +#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v) (((v) & 0x1) << 16) +#define BFM_DCP_CHANNELCTRL_CH0_IRQ_MERGED(v) BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED +#define BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED_V(e) BF_DCP_CHANNELCTRL_CH0_IRQ_MERGED(BV_DCP_CHANNELCTRL_CH0_IRQ_MERGED__##e) +#define BFM_DCP_CHANNELCTRL_CH0_IRQ_MERGED_V(v) BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED +#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 8 +#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 0xff00 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0 0x1 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1 0x2 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2 0x4 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3 0x8 +#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v) (((v) & 0xff) << 8) +#define BFM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v) BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL +#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(e) BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__##e) +#define BFM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_V(v) BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL +#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 +#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0xff +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0 0x1 +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1 0x2 +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2 0x4 +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3 0x8 +#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v) (((v) & 0xff) << 0) +#define BFM_DCP_CHANNELCTRL_ENABLE_CHANNEL(v) BM_DCP_CHANNELCTRL_ENABLE_CHANNEL +#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(e) BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__##e) +#define BFM_DCP_CHANNELCTRL_ENABLE_CHANNEL_V(v) BM_DCP_CHANNELCTRL_ENABLE_CHANNEL + +#define HW_DCP_CAPABILITY0 HW(DCP_CAPABILITY0) +#define HWA_DCP_CAPABILITY0 (0x80028000 + 0x30) +#define HWT_DCP_CAPABILITY0 HWIO_32_RW +#define HWN_DCP_CAPABILITY0 DCP_CAPABILITY0 +#define HWI_DCP_CAPABILITY0 +#define BP_DCP_CAPABILITY0_DISABLE_DECRYPT 31 +#define BM_DCP_CAPABILITY0_DISABLE_DECRYPT 0x80000000 +#define BF_DCP_CAPABILITY0_DISABLE_DECRYPT(v) (((v) & 0x1) << 31) +#define BFM_DCP_CAPABILITY0_DISABLE_DECRYPT(v) BM_DCP_CAPABILITY0_DISABLE_DECRYPT +#define BF_DCP_CAPABILITY0_DISABLE_DECRYPT_V(e) BF_DCP_CAPABILITY0_DISABLE_DECRYPT(BV_DCP_CAPABILITY0_DISABLE_DECRYPT__##e) +#define BFM_DCP_CAPABILITY0_DISABLE_DECRYPT_V(v) BM_DCP_CAPABILITY0_DISABLE_DECRYPT +#define BP_DCP_CAPABILITY0_ENABLE_TZONE 30 +#define BM_DCP_CAPABILITY0_ENABLE_TZONE 0x40000000 +#define BF_DCP_CAPABILITY0_ENABLE_TZONE(v) (((v) & 0x1) << 30) +#define BFM_DCP_CAPABILITY0_ENABLE_TZONE(v) BM_DCP_CAPABILITY0_ENABLE_TZONE +#define BF_DCP_CAPABILITY0_ENABLE_TZONE_V(e) BF_DCP_CAPABILITY0_ENABLE_TZONE(BV_DCP_CAPABILITY0_ENABLE_TZONE__##e) +#define BFM_DCP_CAPABILITY0_ENABLE_TZONE_V(v) BM_DCP_CAPABILITY0_ENABLE_TZONE +#define BP_DCP_CAPABILITY0_RSVD 12 +#define BM_DCP_CAPABILITY0_RSVD 0x3ffff000 +#define BF_DCP_CAPABILITY0_RSVD(v) (((v) & 0x3ffff) << 12) +#define BFM_DCP_CAPABILITY0_RSVD(v) BM_DCP_CAPABILITY0_RSVD +#define BF_DCP_CAPABILITY0_RSVD_V(e) BF_DCP_CAPABILITY0_RSVD(BV_DCP_CAPABILITY0_RSVD__##e) +#define BFM_DCP_CAPABILITY0_RSVD_V(v) BM_DCP_CAPABILITY0_RSVD +#define BP_DCP_CAPABILITY0_NUM_CHANNELS 8 +#define BM_DCP_CAPABILITY0_NUM_CHANNELS 0xf00 +#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v) (((v) & 0xf) << 8) +#define BFM_DCP_CAPABILITY0_NUM_CHANNELS(v) BM_DCP_CAPABILITY0_NUM_CHANNELS +#define BF_DCP_CAPABILITY0_NUM_CHANNELS_V(e) BF_DCP_CAPABILITY0_NUM_CHANNELS(BV_DCP_CAPABILITY0_NUM_CHANNELS__##e) +#define BFM_DCP_CAPABILITY0_NUM_CHANNELS_V(v) BM_DCP_CAPABILITY0_NUM_CHANNELS +#define BP_DCP_CAPABILITY0_NUM_KEYS 0 +#define BM_DCP_CAPABILITY0_NUM_KEYS 0xff +#define BF_DCP_CAPABILITY0_NUM_KEYS(v) (((v) & 0xff) << 0) +#define BFM_DCP_CAPABILITY0_NUM_KEYS(v) BM_DCP_CAPABILITY0_NUM_KEYS +#define BF_DCP_CAPABILITY0_NUM_KEYS_V(e) BF_DCP_CAPABILITY0_NUM_KEYS(BV_DCP_CAPABILITY0_NUM_KEYS__##e) +#define BFM_DCP_CAPABILITY0_NUM_KEYS_V(v) BM_DCP_CAPABILITY0_NUM_KEYS + +#define HW_DCP_CAPABILITY1 HW(DCP_CAPABILITY1) +#define HWA_DCP_CAPABILITY1 (0x80028000 + 0x40) +#define HWT_DCP_CAPABILITY1 HWIO_32_RW +#define HWN_DCP_CAPABILITY1 DCP_CAPABILITY1 +#define HWI_DCP_CAPABILITY1 +#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS 16 +#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS 0xffff0000 +#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1 0x1 +#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32 0x2 +#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v) (((v) & 0xffff) << 16) +#define BFM_DCP_CAPABILITY1_HASH_ALGORITHMS(v) BM_DCP_CAPABILITY1_HASH_ALGORITHMS +#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS_V(e) BF_DCP_CAPABILITY1_HASH_ALGORITHMS(BV_DCP_CAPABILITY1_HASH_ALGORITHMS__##e) +#define BFM_DCP_CAPABILITY1_HASH_ALGORITHMS_V(v) BM_DCP_CAPABILITY1_HASH_ALGORITHMS +#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0 +#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0xffff +#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128 0x1 +#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v) (((v) & 0xffff) << 0) +#define BFM_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v) BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS +#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(e) BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__##e) +#define BFM_DCP_CAPABILITY1_CIPHER_ALGORITHMS_V(v) BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS + +#define HW_DCP_CONTEXT HW(DCP_CONTEXT) +#define HWA_DCP_CONTEXT (0x80028000 + 0x50) +#define HWT_DCP_CONTEXT HWIO_32_RW +#define HWN_DCP_CONTEXT DCP_CONTEXT +#define HWI_DCP_CONTEXT +#define BP_DCP_CONTEXT_ADDR 0 +#define BM_DCP_CONTEXT_ADDR 0xffffffff +#define BF_DCP_CONTEXT_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_CONTEXT_ADDR(v) BM_DCP_CONTEXT_ADDR +#define BF_DCP_CONTEXT_ADDR_V(e) BF_DCP_CONTEXT_ADDR(BV_DCP_CONTEXT_ADDR__##e) +#define BFM_DCP_CONTEXT_ADDR_V(v) BM_DCP_CONTEXT_ADDR + +#define HW_DCP_KEY HW(DCP_KEY) +#define HWA_DCP_KEY (0x80028000 + 0x60) +#define HWT_DCP_KEY HWIO_32_RW +#define HWN_DCP_KEY DCP_KEY +#define HWI_DCP_KEY +#define BP_DCP_KEY_RSVD 8 +#define BM_DCP_KEY_RSVD 0xffffff00 +#define BF_DCP_KEY_RSVD(v) (((v) & 0xffffff) << 8) +#define BFM_DCP_KEY_RSVD(v) BM_DCP_KEY_RSVD +#define BF_DCP_KEY_RSVD_V(e) BF_DCP_KEY_RSVD(BV_DCP_KEY_RSVD__##e) +#define BFM_DCP_KEY_RSVD_V(v) BM_DCP_KEY_RSVD +#define BP_DCP_KEY_RSVD_INDEX 6 +#define BM_DCP_KEY_RSVD_INDEX 0xc0 +#define BF_DCP_KEY_RSVD_INDEX(v) (((v) & 0x3) << 6) +#define BFM_DCP_KEY_RSVD_INDEX(v) BM_DCP_KEY_RSVD_INDEX +#define BF_DCP_KEY_RSVD_INDEX_V(e) BF_DCP_KEY_RSVD_INDEX(BV_DCP_KEY_RSVD_INDEX__##e) +#define BFM_DCP_KEY_RSVD_INDEX_V(v) BM_DCP_KEY_RSVD_INDEX +#define BP_DCP_KEY_INDEX 4 +#define BM_DCP_KEY_INDEX 0x30 +#define BF_DCP_KEY_INDEX(v) (((v) & 0x3) << 4) +#define BFM_DCP_KEY_INDEX(v) BM_DCP_KEY_INDEX +#define BF_DCP_KEY_INDEX_V(e) BF_DCP_KEY_INDEX(BV_DCP_KEY_INDEX__##e) +#define BFM_DCP_KEY_INDEX_V(v) BM_DCP_KEY_INDEX +#define BP_DCP_KEY_RSVD_SUBWORD 2 +#define BM_DCP_KEY_RSVD_SUBWORD 0xc +#define BF_DCP_KEY_RSVD_SUBWORD(v) (((v) & 0x3) << 2) +#define BFM_DCP_KEY_RSVD_SUBWORD(v) BM_DCP_KEY_RSVD_SUBWORD +#define BF_DCP_KEY_RSVD_SUBWORD_V(e) BF_DCP_KEY_RSVD_SUBWORD(BV_DCP_KEY_RSVD_SUBWORD__##e) +#define BFM_DCP_KEY_RSVD_SUBWORD_V(v) BM_DCP_KEY_RSVD_SUBWORD +#define BP_DCP_KEY_SUBWORD 0 +#define BM_DCP_KEY_SUBWORD 0x3 +#define BF_DCP_KEY_SUBWORD(v) (((v) & 0x3) << 0) +#define BFM_DCP_KEY_SUBWORD(v) BM_DCP_KEY_SUBWORD +#define BF_DCP_KEY_SUBWORD_V(e) BF_DCP_KEY_SUBWORD(BV_DCP_KEY_SUBWORD__##e) +#define BFM_DCP_KEY_SUBWORD_V(v) BM_DCP_KEY_SUBWORD + +#define HW_DCP_KEYDATA HW(DCP_KEYDATA) +#define HWA_DCP_KEYDATA (0x80028000 + 0x70) +#define HWT_DCP_KEYDATA HWIO_32_RW +#define HWN_DCP_KEYDATA DCP_KEYDATA +#define HWI_DCP_KEYDATA +#define BP_DCP_KEYDATA_DATA 0 +#define BM_DCP_KEYDATA_DATA 0xffffffff +#define BF_DCP_KEYDATA_DATA(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_KEYDATA_DATA(v) BM_DCP_KEYDATA_DATA +#define BF_DCP_KEYDATA_DATA_V(e) BF_DCP_KEYDATA_DATA(BV_DCP_KEYDATA_DATA__##e) +#define BFM_DCP_KEYDATA_DATA_V(v) BM_DCP_KEYDATA_DATA + +#define HW_DCP_PACKET0 HW(DCP_PACKET0) +#define HWA_DCP_PACKET0 (0x80028000 + 0x80) +#define HWT_DCP_PACKET0 HWIO_32_RW +#define HWN_DCP_PACKET0 DCP_PACKET0 +#define HWI_DCP_PACKET0 +#define BP_DCP_PACKET0_ADDR 0 +#define BM_DCP_PACKET0_ADDR 0xffffffff +#define BF_DCP_PACKET0_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_PACKET0_ADDR(v) BM_DCP_PACKET0_ADDR +#define BF_DCP_PACKET0_ADDR_V(e) BF_DCP_PACKET0_ADDR(BV_DCP_PACKET0_ADDR__##e) +#define BFM_DCP_PACKET0_ADDR_V(v) BM_DCP_PACKET0_ADDR + +#define HW_DCP_PACKET1 HW(DCP_PACKET1) +#define HWA_DCP_PACKET1 (0x80028000 + 0x90) +#define HWT_DCP_PACKET1 HWIO_32_RW +#define HWN_DCP_PACKET1 DCP_PACKET1 +#define HWI_DCP_PACKET1 +#define BP_DCP_PACKET1_TAG 24 +#define BM_DCP_PACKET1_TAG 0xff000000 +#define BF_DCP_PACKET1_TAG(v) (((v) & 0xff) << 24) +#define BFM_DCP_PACKET1_TAG(v) BM_DCP_PACKET1_TAG +#define BF_DCP_PACKET1_TAG_V(e) BF_DCP_PACKET1_TAG(BV_DCP_PACKET1_TAG__##e) +#define BFM_DCP_PACKET1_TAG_V(v) BM_DCP_PACKET1_TAG +#define BP_DCP_PACKET1_OUTPUT_WORDSWAP 23 +#define BM_DCP_PACKET1_OUTPUT_WORDSWAP 0x800000 +#define BF_DCP_PACKET1_OUTPUT_WORDSWAP(v) (((v) & 0x1) << 23) +#define BFM_DCP_PACKET1_OUTPUT_WORDSWAP(v) BM_DCP_PACKET1_OUTPUT_WORDSWAP +#define BF_DCP_PACKET1_OUTPUT_WORDSWAP_V(e) BF_DCP_PACKET1_OUTPUT_WORDSWAP(BV_DCP_PACKET1_OUTPUT_WORDSWAP__##e) +#define BFM_DCP_PACKET1_OUTPUT_WORDSWAP_V(v) BM_DCP_PACKET1_OUTPUT_WORDSWAP +#define BP_DCP_PACKET1_OUTPUT_BYTESWAP 22 +#define BM_DCP_PACKET1_OUTPUT_BYTESWAP 0x400000 +#define BF_DCP_PACKET1_OUTPUT_BYTESWAP(v) (((v) & 0x1) << 22) +#define BFM_DCP_PACKET1_OUTPUT_BYTESWAP(v) BM_DCP_PACKET1_OUTPUT_BYTESWAP +#define BF_DCP_PACKET1_OUTPUT_BYTESWAP_V(e) BF_DCP_PACKET1_OUTPUT_BYTESWAP(BV_DCP_PACKET1_OUTPUT_BYTESWAP__##e) +#define BFM_DCP_PACKET1_OUTPUT_BYTESWAP_V(v) BM_DCP_PACKET1_OUTPUT_BYTESWAP +#define BP_DCP_PACKET1_INPUT_WORDSWAP 21 +#define BM_DCP_PACKET1_INPUT_WORDSWAP 0x200000 +#define BF_DCP_PACKET1_INPUT_WORDSWAP(v) (((v) & 0x1) << 21) +#define BFM_DCP_PACKET1_INPUT_WORDSWAP(v) BM_DCP_PACKET1_INPUT_WORDSWAP +#define BF_DCP_PACKET1_INPUT_WORDSWAP_V(e) BF_DCP_PACKET1_INPUT_WORDSWAP(BV_DCP_PACKET1_INPUT_WORDSWAP__##e) +#define BFM_DCP_PACKET1_INPUT_WORDSWAP_V(v) BM_DCP_PACKET1_INPUT_WORDSWAP +#define BP_DCP_PACKET1_INPUT_BYTESWAP 20 +#define BM_DCP_PACKET1_INPUT_BYTESWAP 0x100000 +#define BF_DCP_PACKET1_INPUT_BYTESWAP(v) (((v) & 0x1) << 20) +#define BFM_DCP_PACKET1_INPUT_BYTESWAP(v) BM_DCP_PACKET1_INPUT_BYTESWAP +#define BF_DCP_PACKET1_INPUT_BYTESWAP_V(e) BF_DCP_PACKET1_INPUT_BYTESWAP(BV_DCP_PACKET1_INPUT_BYTESWAP__##e) +#define BFM_DCP_PACKET1_INPUT_BYTESWAP_V(v) BM_DCP_PACKET1_INPUT_BYTESWAP +#define BP_DCP_PACKET1_KEY_WORDSWAP 19 +#define BM_DCP_PACKET1_KEY_WORDSWAP 0x80000 +#define BF_DCP_PACKET1_KEY_WORDSWAP(v) (((v) & 0x1) << 19) +#define BFM_DCP_PACKET1_KEY_WORDSWAP(v) BM_DCP_PACKET1_KEY_WORDSWAP +#define BF_DCP_PACKET1_KEY_WORDSWAP_V(e) BF_DCP_PACKET1_KEY_WORDSWAP(BV_DCP_PACKET1_KEY_WORDSWAP__##e) +#define BFM_DCP_PACKET1_KEY_WORDSWAP_V(v) BM_DCP_PACKET1_KEY_WORDSWAP +#define BP_DCP_PACKET1_KEY_BYTESWAP 18 +#define BM_DCP_PACKET1_KEY_BYTESWAP 0x40000 +#define BF_DCP_PACKET1_KEY_BYTESWAP(v) (((v) & 0x1) << 18) +#define BFM_DCP_PACKET1_KEY_BYTESWAP(v) BM_DCP_PACKET1_KEY_BYTESWAP +#define BF_DCP_PACKET1_KEY_BYTESWAP_V(e) BF_DCP_PACKET1_KEY_BYTESWAP(BV_DCP_PACKET1_KEY_BYTESWAP__##e) +#define BFM_DCP_PACKET1_KEY_BYTESWAP_V(v) BM_DCP_PACKET1_KEY_BYTESWAP +#define BP_DCP_PACKET1_TEST_SEMA_IRQ 17 +#define BM_DCP_PACKET1_TEST_SEMA_IRQ 0x20000 +#define BF_DCP_PACKET1_TEST_SEMA_IRQ(v) (((v) & 0x1) << 17) +#define BFM_DCP_PACKET1_TEST_SEMA_IRQ(v) BM_DCP_PACKET1_TEST_SEMA_IRQ +#define BF_DCP_PACKET1_TEST_SEMA_IRQ_V(e) BF_DCP_PACKET1_TEST_SEMA_IRQ(BV_DCP_PACKET1_TEST_SEMA_IRQ__##e) +#define BFM_DCP_PACKET1_TEST_SEMA_IRQ_V(v) BM_DCP_PACKET1_TEST_SEMA_IRQ +#define BP_DCP_PACKET1_CONSTANT_FILL 16 +#define BM_DCP_PACKET1_CONSTANT_FILL 0x10000 +#define BF_DCP_PACKET1_CONSTANT_FILL(v) (((v) & 0x1) << 16) +#define BFM_DCP_PACKET1_CONSTANT_FILL(v) BM_DCP_PACKET1_CONSTANT_FILL +#define BF_DCP_PACKET1_CONSTANT_FILL_V(e) BF_DCP_PACKET1_CONSTANT_FILL(BV_DCP_PACKET1_CONSTANT_FILL__##e) +#define BFM_DCP_PACKET1_CONSTANT_FILL_V(v) BM_DCP_PACKET1_CONSTANT_FILL +#define BP_DCP_PACKET1_HASH_OUTPUT 15 +#define BM_DCP_PACKET1_HASH_OUTPUT 0x8000 +#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT 0x0 +#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT 0x1 +#define BF_DCP_PACKET1_HASH_OUTPUT(v) (((v) & 0x1) << 15) +#define BFM_DCP_PACKET1_HASH_OUTPUT(v) BM_DCP_PACKET1_HASH_OUTPUT +#define BF_DCP_PACKET1_HASH_OUTPUT_V(e) BF_DCP_PACKET1_HASH_OUTPUT(BV_DCP_PACKET1_HASH_OUTPUT__##e) +#define BFM_DCP_PACKET1_HASH_OUTPUT_V(v) BM_DCP_PACKET1_HASH_OUTPUT +#define BP_DCP_PACKET1_CHECK_HASH 14 +#define BM_DCP_PACKET1_CHECK_HASH 0x4000 +#define BF_DCP_PACKET1_CHECK_HASH(v) (((v) & 0x1) << 14) +#define BFM_DCP_PACKET1_CHECK_HASH(v) BM_DCP_PACKET1_CHECK_HASH +#define BF_DCP_PACKET1_CHECK_HASH_V(e) BF_DCP_PACKET1_CHECK_HASH(BV_DCP_PACKET1_CHECK_HASH__##e) +#define BFM_DCP_PACKET1_CHECK_HASH_V(v) BM_DCP_PACKET1_CHECK_HASH +#define BP_DCP_PACKET1_HASH_TERM 13 +#define BM_DCP_PACKET1_HASH_TERM 0x2000 +#define BF_DCP_PACKET1_HASH_TERM(v) (((v) & 0x1) << 13) +#define BFM_DCP_PACKET1_HASH_TERM(v) BM_DCP_PACKET1_HASH_TERM +#define BF_DCP_PACKET1_HASH_TERM_V(e) BF_DCP_PACKET1_HASH_TERM(BV_DCP_PACKET1_HASH_TERM__##e) +#define BFM_DCP_PACKET1_HASH_TERM_V(v) BM_DCP_PACKET1_HASH_TERM +#define BP_DCP_PACKET1_HASH_INIT 12 +#define BM_DCP_PACKET1_HASH_INIT 0x1000 +#define BF_DCP_PACKET1_HASH_INIT(v) (((v) & 0x1) << 12) +#define BFM_DCP_PACKET1_HASH_INIT(v) BM_DCP_PACKET1_HASH_INIT +#define BF_DCP_PACKET1_HASH_INIT_V(e) BF_DCP_PACKET1_HASH_INIT(BV_DCP_PACKET1_HASH_INIT__##e) +#define BFM_DCP_PACKET1_HASH_INIT_V(v) BM_DCP_PACKET1_HASH_INIT +#define BP_DCP_PACKET1_PAYLOAD_KEY 11 +#define BM_DCP_PACKET1_PAYLOAD_KEY 0x800 +#define BF_DCP_PACKET1_PAYLOAD_KEY(v) (((v) & 0x1) << 11) +#define BFM_DCP_PACKET1_PAYLOAD_KEY(v) BM_DCP_PACKET1_PAYLOAD_KEY +#define BF_DCP_PACKET1_PAYLOAD_KEY_V(e) BF_DCP_PACKET1_PAYLOAD_KEY(BV_DCP_PACKET1_PAYLOAD_KEY__##e) +#define BFM_DCP_PACKET1_PAYLOAD_KEY_V(v) BM_DCP_PACKET1_PAYLOAD_KEY +#define BP_DCP_PACKET1_OTP_KEY 10 +#define BM_DCP_PACKET1_OTP_KEY 0x400 +#define BF_DCP_PACKET1_OTP_KEY(v) (((v) & 0x1) << 10) +#define BFM_DCP_PACKET1_OTP_KEY(v) BM_DCP_PACKET1_OTP_KEY +#define BF_DCP_PACKET1_OTP_KEY_V(e) BF_DCP_PACKET1_OTP_KEY(BV_DCP_PACKET1_OTP_KEY__##e) +#define BFM_DCP_PACKET1_OTP_KEY_V(v) BM_DCP_PACKET1_OTP_KEY +#define BP_DCP_PACKET1_CIPHER_INIT 9 +#define BM_DCP_PACKET1_CIPHER_INIT 0x200 +#define BF_DCP_PACKET1_CIPHER_INIT(v) (((v) & 0x1) << 9) +#define BFM_DCP_PACKET1_CIPHER_INIT(v) BM_DCP_PACKET1_CIPHER_INIT +#define BF_DCP_PACKET1_CIPHER_INIT_V(e) BF_DCP_PACKET1_CIPHER_INIT(BV_DCP_PACKET1_CIPHER_INIT__##e) +#define BFM_DCP_PACKET1_CIPHER_INIT_V(v) BM_DCP_PACKET1_CIPHER_INIT +#define BP_DCP_PACKET1_CIPHER_ENCRYPT 8 +#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x100 +#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT 0x1 +#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT 0x0 +#define BF_DCP_PACKET1_CIPHER_ENCRYPT(v) (((v) & 0x1) << 8) +#define BFM_DCP_PACKET1_CIPHER_ENCRYPT(v) BM_DCP_PACKET1_CIPHER_ENCRYPT +#define BF_DCP_PACKET1_CIPHER_ENCRYPT_V(e) BF_DCP_PACKET1_CIPHER_ENCRYPT(BV_DCP_PACKET1_CIPHER_ENCRYPT__##e) +#define BFM_DCP_PACKET1_CIPHER_ENCRYPT_V(v) BM_DCP_PACKET1_CIPHER_ENCRYPT +#define BP_DCP_PACKET1_ENABLE_BLIT 7 +#define BM_DCP_PACKET1_ENABLE_BLIT 0x80 +#define BF_DCP_PACKET1_ENABLE_BLIT(v) (((v) & 0x1) << 7) +#define BFM_DCP_PACKET1_ENABLE_BLIT(v) BM_DCP_PACKET1_ENABLE_BLIT +#define BF_DCP_PACKET1_ENABLE_BLIT_V(e) BF_DCP_PACKET1_ENABLE_BLIT(BV_DCP_PACKET1_ENABLE_BLIT__##e) +#define BFM_DCP_PACKET1_ENABLE_BLIT_V(v) BM_DCP_PACKET1_ENABLE_BLIT +#define BP_DCP_PACKET1_ENABLE_HASH 6 +#define BM_DCP_PACKET1_ENABLE_HASH 0x40 +#define BF_DCP_PACKET1_ENABLE_HASH(v) (((v) & 0x1) << 6) +#define BFM_DCP_PACKET1_ENABLE_HASH(v) BM_DCP_PACKET1_ENABLE_HASH +#define BF_DCP_PACKET1_ENABLE_HASH_V(e) BF_DCP_PACKET1_ENABLE_HASH(BV_DCP_PACKET1_ENABLE_HASH__##e) +#define BFM_DCP_PACKET1_ENABLE_HASH_V(v) BM_DCP_PACKET1_ENABLE_HASH +#define BP_DCP_PACKET1_ENABLE_CIPHER 5 +#define BM_DCP_PACKET1_ENABLE_CIPHER 0x20 +#define BF_DCP_PACKET1_ENABLE_CIPHER(v) (((v) & 0x1) << 5) +#define BFM_DCP_PACKET1_ENABLE_CIPHER(v) BM_DCP_PACKET1_ENABLE_CIPHER +#define BF_DCP_PACKET1_ENABLE_CIPHER_V(e) BF_DCP_PACKET1_ENABLE_CIPHER(BV_DCP_PACKET1_ENABLE_CIPHER__##e) +#define BFM_DCP_PACKET1_ENABLE_CIPHER_V(v) BM_DCP_PACKET1_ENABLE_CIPHER +#define BP_DCP_PACKET1_ENABLE_MEMCOPY 4 +#define BM_DCP_PACKET1_ENABLE_MEMCOPY 0x10 +#define BF_DCP_PACKET1_ENABLE_MEMCOPY(v) (((v) & 0x1) << 4) +#define BFM_DCP_PACKET1_ENABLE_MEMCOPY(v) BM_DCP_PACKET1_ENABLE_MEMCOPY +#define BF_DCP_PACKET1_ENABLE_MEMCOPY_V(e) BF_DCP_PACKET1_ENABLE_MEMCOPY(BV_DCP_PACKET1_ENABLE_MEMCOPY__##e) +#define BFM_DCP_PACKET1_ENABLE_MEMCOPY_V(v) BM_DCP_PACKET1_ENABLE_MEMCOPY +#define BP_DCP_PACKET1_CHAIN_CONTIGUOUS 3 +#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x8 +#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS(v) (((v) & 0x1) << 3) +#define BFM_DCP_PACKET1_CHAIN_CONTIGUOUS(v) BM_DCP_PACKET1_CHAIN_CONTIGUOUS +#define BF_DCP_PACKET1_CHAIN_CONTIGUOUS_V(e) BF_DCP_PACKET1_CHAIN_CONTIGUOUS(BV_DCP_PACKET1_CHAIN_CONTIGUOUS__##e) +#define BFM_DCP_PACKET1_CHAIN_CONTIGUOUS_V(v) BM_DCP_PACKET1_CHAIN_CONTIGUOUS +#define BP_DCP_PACKET1_CHAIN 2 +#define BM_DCP_PACKET1_CHAIN 0x4 +#define BF_DCP_PACKET1_CHAIN(v) (((v) & 0x1) << 2) +#define BFM_DCP_PACKET1_CHAIN(v) BM_DCP_PACKET1_CHAIN +#define BF_DCP_PACKET1_CHAIN_V(e) BF_DCP_PACKET1_CHAIN(BV_DCP_PACKET1_CHAIN__##e) +#define BFM_DCP_PACKET1_CHAIN_V(v) BM_DCP_PACKET1_CHAIN +#define BP_DCP_PACKET1_DECR_SEMAPHORE 1 +#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x2 +#define BF_DCP_PACKET1_DECR_SEMAPHORE(v) (((v) & 0x1) << 1) +#define BFM_DCP_PACKET1_DECR_SEMAPHORE(v) BM_DCP_PACKET1_DECR_SEMAPHORE +#define BF_DCP_PACKET1_DECR_SEMAPHORE_V(e) BF_DCP_PACKET1_DECR_SEMAPHORE(BV_DCP_PACKET1_DECR_SEMAPHORE__##e) +#define BFM_DCP_PACKET1_DECR_SEMAPHORE_V(v) BM_DCP_PACKET1_DECR_SEMAPHORE +#define BP_DCP_PACKET1_INTERRUPT 0 +#define BM_DCP_PACKET1_INTERRUPT 0x1 +#define BF_DCP_PACKET1_INTERRUPT(v) (((v) & 0x1) << 0) +#define BFM_DCP_PACKET1_INTERRUPT(v) BM_DCP_PACKET1_INTERRUPT +#define BF_DCP_PACKET1_INTERRUPT_V(e) BF_DCP_PACKET1_INTERRUPT(BV_DCP_PACKET1_INTERRUPT__##e) +#define BFM_DCP_PACKET1_INTERRUPT_V(v) BM_DCP_PACKET1_INTERRUPT + +#define HW_DCP_PACKET2 HW(DCP_PACKET2) +#define HWA_DCP_PACKET2 (0x80028000 + 0xa0) +#define HWT_DCP_PACKET2 HWIO_32_RW +#define HWN_DCP_PACKET2 DCP_PACKET2 +#define HWI_DCP_PACKET2 +#define BP_DCP_PACKET2_CIPHER_CFG 24 +#define BM_DCP_PACKET2_CIPHER_CFG 0xff000000 +#define BF_DCP_PACKET2_CIPHER_CFG(v) (((v) & 0xff) << 24) +#define BFM_DCP_PACKET2_CIPHER_CFG(v) BM_DCP_PACKET2_CIPHER_CFG +#define BF_DCP_PACKET2_CIPHER_CFG_V(e) BF_DCP_PACKET2_CIPHER_CFG(BV_DCP_PACKET2_CIPHER_CFG__##e) +#define BFM_DCP_PACKET2_CIPHER_CFG_V(v) BM_DCP_PACKET2_CIPHER_CFG +#define BP_DCP_PACKET2_RSVD 20 +#define BM_DCP_PACKET2_RSVD 0xf00000 +#define BF_DCP_PACKET2_RSVD(v) (((v) & 0xf) << 20) +#define BFM_DCP_PACKET2_RSVD(v) BM_DCP_PACKET2_RSVD +#define BF_DCP_PACKET2_RSVD_V(e) BF_DCP_PACKET2_RSVD(BV_DCP_PACKET2_RSVD__##e) +#define BFM_DCP_PACKET2_RSVD_V(v) BM_DCP_PACKET2_RSVD +#define BP_DCP_PACKET2_HASH_SELECT 16 +#define BM_DCP_PACKET2_HASH_SELECT 0xf0000 +#define BV_DCP_PACKET2_HASH_SELECT__SHA1 0x0 +#define BV_DCP_PACKET2_HASH_SELECT__CRC32 0x1 +#define BF_DCP_PACKET2_HASH_SELECT(v) (((v) & 0xf) << 16) +#define BFM_DCP_PACKET2_HASH_SELECT(v) BM_DCP_PACKET2_HASH_SELECT +#define BF_DCP_PACKET2_HASH_SELECT_V(e) BF_DCP_PACKET2_HASH_SELECT(BV_DCP_PACKET2_HASH_SELECT__##e) +#define BFM_DCP_PACKET2_HASH_SELECT_V(v) BM_DCP_PACKET2_HASH_SELECT +#define BP_DCP_PACKET2_KEY_SELECT 8 +#define BM_DCP_PACKET2_KEY_SELECT 0xff00 +#define BF_DCP_PACKET2_KEY_SELECT(v) (((v) & 0xff) << 8) +#define BFM_DCP_PACKET2_KEY_SELECT(v) BM_DCP_PACKET2_KEY_SELECT +#define BF_DCP_PACKET2_KEY_SELECT_V(e) BF_DCP_PACKET2_KEY_SELECT(BV_DCP_PACKET2_KEY_SELECT__##e) +#define BFM_DCP_PACKET2_KEY_SELECT_V(v) BM_DCP_PACKET2_KEY_SELECT +#define BP_DCP_PACKET2_CIPHER_MODE 4 +#define BM_DCP_PACKET2_CIPHER_MODE 0xf0 +#define BV_DCP_PACKET2_CIPHER_MODE__ECB 0x0 +#define BV_DCP_PACKET2_CIPHER_MODE__CBC 0x1 +#define BF_DCP_PACKET2_CIPHER_MODE(v) (((v) & 0xf) << 4) +#define BFM_DCP_PACKET2_CIPHER_MODE(v) BM_DCP_PACKET2_CIPHER_MODE +#define BF_DCP_PACKET2_CIPHER_MODE_V(e) BF_DCP_PACKET2_CIPHER_MODE(BV_DCP_PACKET2_CIPHER_MODE__##e) +#define BFM_DCP_PACKET2_CIPHER_MODE_V(v) BM_DCP_PACKET2_CIPHER_MODE +#define BP_DCP_PACKET2_CIPHER_SELECT 0 +#define BM_DCP_PACKET2_CIPHER_SELECT 0xf +#define BV_DCP_PACKET2_CIPHER_SELECT__AES128 0x0 +#define BF_DCP_PACKET2_CIPHER_SELECT(v) (((v) & 0xf) << 0) +#define BFM_DCP_PACKET2_CIPHER_SELECT(v) BM_DCP_PACKET2_CIPHER_SELECT +#define BF_DCP_PACKET2_CIPHER_SELECT_V(e) BF_DCP_PACKET2_CIPHER_SELECT(BV_DCP_PACKET2_CIPHER_SELECT__##e) +#define BFM_DCP_PACKET2_CIPHER_SELECT_V(v) BM_DCP_PACKET2_CIPHER_SELECT + +#define HW_DCP_PACKET3 HW(DCP_PACKET3) +#define HWA_DCP_PACKET3 (0x80028000 + 0xb0) +#define HWT_DCP_PACKET3 HWIO_32_RW +#define HWN_DCP_PACKET3 DCP_PACKET3 +#define HWI_DCP_PACKET3 +#define BP_DCP_PACKET3_ADDR 0 +#define BM_DCP_PACKET3_ADDR 0xffffffff +#define BF_DCP_PACKET3_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_PACKET3_ADDR(v) BM_DCP_PACKET3_ADDR +#define BF_DCP_PACKET3_ADDR_V(e) BF_DCP_PACKET3_ADDR(BV_DCP_PACKET3_ADDR__##e) +#define BFM_DCP_PACKET3_ADDR_V(v) BM_DCP_PACKET3_ADDR + +#define HW_DCP_PACKET4 HW(DCP_PACKET4) +#define HWA_DCP_PACKET4 (0x80028000 + 0xc0) +#define HWT_DCP_PACKET4 HWIO_32_RW +#define HWN_DCP_PACKET4 DCP_PACKET4 +#define HWI_DCP_PACKET4 +#define BP_DCP_PACKET4_ADDR 0 +#define BM_DCP_PACKET4_ADDR 0xffffffff +#define BF_DCP_PACKET4_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_PACKET4_ADDR(v) BM_DCP_PACKET4_ADDR +#define BF_DCP_PACKET4_ADDR_V(e) BF_DCP_PACKET4_ADDR(BV_DCP_PACKET4_ADDR__##e) +#define BFM_DCP_PACKET4_ADDR_V(v) BM_DCP_PACKET4_ADDR + +#define HW_DCP_PACKET5 HW(DCP_PACKET5) +#define HWA_DCP_PACKET5 (0x80028000 + 0xd0) +#define HWT_DCP_PACKET5 HWIO_32_RW +#define HWN_DCP_PACKET5 DCP_PACKET5 +#define HWI_DCP_PACKET5 +#define BP_DCP_PACKET5_COUNT 0 +#define BM_DCP_PACKET5_COUNT 0xffffffff +#define BF_DCP_PACKET5_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_PACKET5_COUNT(v) BM_DCP_PACKET5_COUNT +#define BF_DCP_PACKET5_COUNT_V(e) BF_DCP_PACKET5_COUNT(BV_DCP_PACKET5_COUNT__##e) +#define BFM_DCP_PACKET5_COUNT_V(v) BM_DCP_PACKET5_COUNT + +#define HW_DCP_PACKET6 HW(DCP_PACKET6) +#define HWA_DCP_PACKET6 (0x80028000 + 0xe0) +#define HWT_DCP_PACKET6 HWIO_32_RW +#define HWN_DCP_PACKET6 DCP_PACKET6 +#define HWI_DCP_PACKET6 +#define BP_DCP_PACKET6_ADDR 0 +#define BM_DCP_PACKET6_ADDR 0xffffffff +#define BF_DCP_PACKET6_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_PACKET6_ADDR(v) BM_DCP_PACKET6_ADDR +#define BF_DCP_PACKET6_ADDR_V(e) BF_DCP_PACKET6_ADDR(BV_DCP_PACKET6_ADDR__##e) +#define BFM_DCP_PACKET6_ADDR_V(v) BM_DCP_PACKET6_ADDR + +#define HW_DCP_CHnCMDPTR(_n1) HW(DCP_CHnCMDPTR(_n1)) +#define HWA_DCP_CHnCMDPTR(_n1) (0x80028000 + 0x100 + (_n1) * 0x40) +#define HWT_DCP_CHnCMDPTR(_n1) HWIO_32_RW +#define HWN_DCP_CHnCMDPTR(_n1) DCP_CHnCMDPTR +#define HWI_DCP_CHnCMDPTR(_n1) (_n1) +#define BP_DCP_CHnCMDPTR_ADDR 0 +#define BM_DCP_CHnCMDPTR_ADDR 0xffffffff +#define BF_DCP_CHnCMDPTR_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_CHnCMDPTR_ADDR(v) BM_DCP_CHnCMDPTR_ADDR +#define BF_DCP_CHnCMDPTR_ADDR_V(e) BF_DCP_CHnCMDPTR_ADDR(BV_DCP_CHnCMDPTR_ADDR__##e) +#define BFM_DCP_CHnCMDPTR_ADDR_V(v) BM_DCP_CHnCMDPTR_ADDR + +#define HW_DCP_CHnSEMA(_n1) HW(DCP_CHnSEMA(_n1)) +#define HWA_DCP_CHnSEMA(_n1) (0x80028000 + 0x110 + (_n1) * 0x40) +#define HWT_DCP_CHnSEMA(_n1) HWIO_32_RW +#define HWN_DCP_CHnSEMA(_n1) DCP_CHnSEMA +#define HWI_DCP_CHnSEMA(_n1) (_n1) +#define BP_DCP_CHnSEMA_RSVD2 24 +#define BM_DCP_CHnSEMA_RSVD2 0xff000000 +#define BF_DCP_CHnSEMA_RSVD2(v) (((v) & 0xff) << 24) +#define BFM_DCP_CHnSEMA_RSVD2(v) BM_DCP_CHnSEMA_RSVD2 +#define BF_DCP_CHnSEMA_RSVD2_V(e) BF_DCP_CHnSEMA_RSVD2(BV_DCP_CHnSEMA_RSVD2__##e) +#define BFM_DCP_CHnSEMA_RSVD2_V(v) BM_DCP_CHnSEMA_RSVD2 +#define BP_DCP_CHnSEMA_VALUE 16 +#define BM_DCP_CHnSEMA_VALUE 0xff0000 +#define BF_DCP_CHnSEMA_VALUE(v) (((v) & 0xff) << 16) +#define BFM_DCP_CHnSEMA_VALUE(v) BM_DCP_CHnSEMA_VALUE +#define BF_DCP_CHnSEMA_VALUE_V(e) BF_DCP_CHnSEMA_VALUE(BV_DCP_CHnSEMA_VALUE__##e) +#define BFM_DCP_CHnSEMA_VALUE_V(v) BM_DCP_CHnSEMA_VALUE +#define BP_DCP_CHnSEMA_RSVD1 8 +#define BM_DCP_CHnSEMA_RSVD1 0xff00 +#define BF_DCP_CHnSEMA_RSVD1(v) (((v) & 0xff) << 8) +#define BFM_DCP_CHnSEMA_RSVD1(v) BM_DCP_CHnSEMA_RSVD1 +#define BF_DCP_CHnSEMA_RSVD1_V(e) BF_DCP_CHnSEMA_RSVD1(BV_DCP_CHnSEMA_RSVD1__##e) +#define BFM_DCP_CHnSEMA_RSVD1_V(v) BM_DCP_CHnSEMA_RSVD1 +#define BP_DCP_CHnSEMA_INCREMENT 0 +#define BM_DCP_CHnSEMA_INCREMENT 0xff +#define BF_DCP_CHnSEMA_INCREMENT(v) (((v) & 0xff) << 0) +#define BFM_DCP_CHnSEMA_INCREMENT(v) BM_DCP_CHnSEMA_INCREMENT +#define BF_DCP_CHnSEMA_INCREMENT_V(e) BF_DCP_CHnSEMA_INCREMENT(BV_DCP_CHnSEMA_INCREMENT__##e) +#define BFM_DCP_CHnSEMA_INCREMENT_V(v) BM_DCP_CHnSEMA_INCREMENT + +#define HW_DCP_CHnSTAT(_n1) HW(DCP_CHnSTAT(_n1)) +#define HWA_DCP_CHnSTAT(_n1) (0x80028000 + 0x120 + (_n1) * 0x40) +#define HWT_DCP_CHnSTAT(_n1) HWIO_32_RW +#define HWN_DCP_CHnSTAT(_n1) DCP_CHnSTAT +#define HWI_DCP_CHnSTAT(_n1) (_n1) +#define HW_DCP_CHnSTAT_SET(_n1) HW(DCP_CHnSTAT_SET(_n1)) +#define HWA_DCP_CHnSTAT_SET(_n1) (HWA_DCP_CHnSTAT(_n1) + 0x4) +#define HWT_DCP_CHnSTAT_SET(_n1) HWIO_32_WO +#define HWN_DCP_CHnSTAT_SET(_n1) DCP_CHnSTAT +#define HWI_DCP_CHnSTAT_SET(_n1) (_n1) +#define HW_DCP_CHnSTAT_CLR(_n1) HW(DCP_CHnSTAT_CLR(_n1)) +#define HWA_DCP_CHnSTAT_CLR(_n1) (HWA_DCP_CHnSTAT(_n1) + 0x8) +#define HWT_DCP_CHnSTAT_CLR(_n1) HWIO_32_WO +#define HWN_DCP_CHnSTAT_CLR(_n1) DCP_CHnSTAT +#define HWI_DCP_CHnSTAT_CLR(_n1) (_n1) +#define HW_DCP_CHnSTAT_TOG(_n1) HW(DCP_CHnSTAT_TOG(_n1)) +#define HWA_DCP_CHnSTAT_TOG(_n1) (HWA_DCP_CHnSTAT(_n1) + 0xc) +#define HWT_DCP_CHnSTAT_TOG(_n1) HWIO_32_WO +#define HWN_DCP_CHnSTAT_TOG(_n1) DCP_CHnSTAT +#define HWI_DCP_CHnSTAT_TOG(_n1) (_n1) +#define BP_DCP_CHnSTAT_TAG 24 +#define BM_DCP_CHnSTAT_TAG 0xff000000 +#define BF_DCP_CHnSTAT_TAG(v) (((v) & 0xff) << 24) +#define BFM_DCP_CHnSTAT_TAG(v) BM_DCP_CHnSTAT_TAG +#define BF_DCP_CHnSTAT_TAG_V(e) BF_DCP_CHnSTAT_TAG(BV_DCP_CHnSTAT_TAG__##e) +#define BFM_DCP_CHnSTAT_TAG_V(v) BM_DCP_CHnSTAT_TAG +#define BP_DCP_CHnSTAT_ERROR_CODE 16 +#define BM_DCP_CHnSTAT_ERROR_CODE 0xff0000 +#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0 0x1 +#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN 0x2 +#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR 0x3 +#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR 0x4 +#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE 0x5 +#define BF_DCP_CHnSTAT_ERROR_CODE(v) (((v) & 0xff) << 16) +#define BFM_DCP_CHnSTAT_ERROR_CODE(v) BM_DCP_CHnSTAT_ERROR_CODE +#define BF_DCP_CHnSTAT_ERROR_CODE_V(e) BF_DCP_CHnSTAT_ERROR_CODE(BV_DCP_CHnSTAT_ERROR_CODE__##e) +#define BFM_DCP_CHnSTAT_ERROR_CODE_V(v) BM_DCP_CHnSTAT_ERROR_CODE +#define BP_DCP_CHnSTAT_RSVD0 7 +#define BM_DCP_CHnSTAT_RSVD0 0xff80 +#define BF_DCP_CHnSTAT_RSVD0(v) (((v) & 0x1ff) << 7) +#define BFM_DCP_CHnSTAT_RSVD0(v) BM_DCP_CHnSTAT_RSVD0 +#define BF_DCP_CHnSTAT_RSVD0_V(e) BF_DCP_CHnSTAT_RSVD0(BV_DCP_CHnSTAT_RSVD0__##e) +#define BFM_DCP_CHnSTAT_RSVD0_V(v) BM_DCP_CHnSTAT_RSVD0 +#define BP_DCP_CHnSTAT_ERROR_PAGEFAULT 6 +#define BM_DCP_CHnSTAT_ERROR_PAGEFAULT 0x40 +#define BF_DCP_CHnSTAT_ERROR_PAGEFAULT(v) (((v) & 0x1) << 6) +#define BFM_DCP_CHnSTAT_ERROR_PAGEFAULT(v) BM_DCP_CHnSTAT_ERROR_PAGEFAULT +#define BF_DCP_CHnSTAT_ERROR_PAGEFAULT_V(e) BF_DCP_CHnSTAT_ERROR_PAGEFAULT(BV_DCP_CHnSTAT_ERROR_PAGEFAULT__##e) +#define BFM_DCP_CHnSTAT_ERROR_PAGEFAULT_V(v) BM_DCP_CHnSTAT_ERROR_PAGEFAULT +#define BP_DCP_CHnSTAT_ERROR_DST 5 +#define BM_DCP_CHnSTAT_ERROR_DST 0x20 +#define BF_DCP_CHnSTAT_ERROR_DST(v) (((v) & 0x1) << 5) +#define BFM_DCP_CHnSTAT_ERROR_DST(v) BM_DCP_CHnSTAT_ERROR_DST +#define BF_DCP_CHnSTAT_ERROR_DST_V(e) BF_DCP_CHnSTAT_ERROR_DST(BV_DCP_CHnSTAT_ERROR_DST__##e) +#define BFM_DCP_CHnSTAT_ERROR_DST_V(v) BM_DCP_CHnSTAT_ERROR_DST +#define BP_DCP_CHnSTAT_ERROR_SRC 4 +#define BM_DCP_CHnSTAT_ERROR_SRC 0x10 +#define BF_DCP_CHnSTAT_ERROR_SRC(v) (((v) & 0x1) << 4) +#define BFM_DCP_CHnSTAT_ERROR_SRC(v) BM_DCP_CHnSTAT_ERROR_SRC +#define BF_DCP_CHnSTAT_ERROR_SRC_V(e) BF_DCP_CHnSTAT_ERROR_SRC(BV_DCP_CHnSTAT_ERROR_SRC__##e) +#define BFM_DCP_CHnSTAT_ERROR_SRC_V(v) BM_DCP_CHnSTAT_ERROR_SRC +#define BP_DCP_CHnSTAT_ERROR_PACKET 3 +#define BM_DCP_CHnSTAT_ERROR_PACKET 0x8 +#define BF_DCP_CHnSTAT_ERROR_PACKET(v) (((v) & 0x1) << 3) +#define BFM_DCP_CHnSTAT_ERROR_PACKET(v) BM_DCP_CHnSTAT_ERROR_PACKET +#define BF_DCP_CHnSTAT_ERROR_PACKET_V(e) BF_DCP_CHnSTAT_ERROR_PACKET(BV_DCP_CHnSTAT_ERROR_PACKET__##e) +#define BFM_DCP_CHnSTAT_ERROR_PACKET_V(v) BM_DCP_CHnSTAT_ERROR_PACKET +#define BP_DCP_CHnSTAT_ERROR_SETUP 2 +#define BM_DCP_CHnSTAT_ERROR_SETUP 0x4 +#define BF_DCP_CHnSTAT_ERROR_SETUP(v) (((v) & 0x1) << 2) +#define BFM_DCP_CHnSTAT_ERROR_SETUP(v) BM_DCP_CHnSTAT_ERROR_SETUP +#define BF_DCP_CHnSTAT_ERROR_SETUP_V(e) BF_DCP_CHnSTAT_ERROR_SETUP(BV_DCP_CHnSTAT_ERROR_SETUP__##e) +#define BFM_DCP_CHnSTAT_ERROR_SETUP_V(v) BM_DCP_CHnSTAT_ERROR_SETUP +#define BP_DCP_CHnSTAT_HASH_MISMATCH 1 +#define BM_DCP_CHnSTAT_HASH_MISMATCH 0x2 +#define BF_DCP_CHnSTAT_HASH_MISMATCH(v) (((v) & 0x1) << 1) +#define BFM_DCP_CHnSTAT_HASH_MISMATCH(v) BM_DCP_CHnSTAT_HASH_MISMATCH +#define BF_DCP_CHnSTAT_HASH_MISMATCH_V(e) BF_DCP_CHnSTAT_HASH_MISMATCH(BV_DCP_CHnSTAT_HASH_MISMATCH__##e) +#define BFM_DCP_CHnSTAT_HASH_MISMATCH_V(v) BM_DCP_CHnSTAT_HASH_MISMATCH +#define BP_DCP_CHnSTAT_RSVD_COMPLETE 0 +#define BM_DCP_CHnSTAT_RSVD_COMPLETE 0x1 +#define BF_DCP_CHnSTAT_RSVD_COMPLETE(v) (((v) & 0x1) << 0) +#define BFM_DCP_CHnSTAT_RSVD_COMPLETE(v) BM_DCP_CHnSTAT_RSVD_COMPLETE +#define BF_DCP_CHnSTAT_RSVD_COMPLETE_V(e) BF_DCP_CHnSTAT_RSVD_COMPLETE(BV_DCP_CHnSTAT_RSVD_COMPLETE__##e) +#define BFM_DCP_CHnSTAT_RSVD_COMPLETE_V(v) BM_DCP_CHnSTAT_RSVD_COMPLETE + +#define HW_DCP_CHnOPTS(_n1) HW(DCP_CHnOPTS(_n1)) +#define HWA_DCP_CHnOPTS(_n1) (0x80028000 + 0x130 + (_n1) * 0x40) +#define HWT_DCP_CHnOPTS(_n1) HWIO_32_RW +#define HWN_DCP_CHnOPTS(_n1) DCP_CHnOPTS +#define HWI_DCP_CHnOPTS(_n1) (_n1) +#define HW_DCP_CHnOPTS_SET(_n1) HW(DCP_CHnOPTS_SET(_n1)) +#define HWA_DCP_CHnOPTS_SET(_n1) (HWA_DCP_CHnOPTS(_n1) + 0x4) +#define HWT_DCP_CHnOPTS_SET(_n1) HWIO_32_WO +#define HWN_DCP_CHnOPTS_SET(_n1) DCP_CHnOPTS +#define HWI_DCP_CHnOPTS_SET(_n1) (_n1) +#define HW_DCP_CHnOPTS_CLR(_n1) HW(DCP_CHnOPTS_CLR(_n1)) +#define HWA_DCP_CHnOPTS_CLR(_n1) (HWA_DCP_CHnOPTS(_n1) + 0x8) +#define HWT_DCP_CHnOPTS_CLR(_n1) HWIO_32_WO +#define HWN_DCP_CHnOPTS_CLR(_n1) DCP_CHnOPTS +#define HWI_DCP_CHnOPTS_CLR(_n1) (_n1) +#define HW_DCP_CHnOPTS_TOG(_n1) HW(DCP_CHnOPTS_TOG(_n1)) +#define HWA_DCP_CHnOPTS_TOG(_n1) (HWA_DCP_CHnOPTS(_n1) + 0xc) +#define HWT_DCP_CHnOPTS_TOG(_n1) HWIO_32_WO +#define HWN_DCP_CHnOPTS_TOG(_n1) DCP_CHnOPTS +#define HWI_DCP_CHnOPTS_TOG(_n1) (_n1) +#define BP_DCP_CHnOPTS_RSVD 16 +#define BM_DCP_CHnOPTS_RSVD 0xffff0000 +#define BF_DCP_CHnOPTS_RSVD(v) (((v) & 0xffff) << 16) +#define BFM_DCP_CHnOPTS_RSVD(v) BM_DCP_CHnOPTS_RSVD +#define BF_DCP_CHnOPTS_RSVD_V(e) BF_DCP_CHnOPTS_RSVD(BV_DCP_CHnOPTS_RSVD__##e) +#define BFM_DCP_CHnOPTS_RSVD_V(v) BM_DCP_CHnOPTS_RSVD +#define BP_DCP_CHnOPTS_RECOVERY_TIMER 0 +#define BM_DCP_CHnOPTS_RECOVERY_TIMER 0xffff +#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v) (((v) & 0xffff) << 0) +#define BFM_DCP_CHnOPTS_RECOVERY_TIMER(v) BM_DCP_CHnOPTS_RECOVERY_TIMER +#define BF_DCP_CHnOPTS_RECOVERY_TIMER_V(e) BF_DCP_CHnOPTS_RECOVERY_TIMER(BV_DCP_CHnOPTS_RECOVERY_TIMER__##e) +#define BFM_DCP_CHnOPTS_RECOVERY_TIMER_V(v) BM_DCP_CHnOPTS_RECOVERY_TIMER + +#define HW_DCP_CSCCTRL0 HW(DCP_CSCCTRL0) +#define HWA_DCP_CSCCTRL0 (0x80028000 + 0x300) +#define HWT_DCP_CSCCTRL0 HWIO_32_RW +#define HWN_DCP_CSCCTRL0 DCP_CSCCTRL0 +#define HWI_DCP_CSCCTRL0 +#define HW_DCP_CSCCTRL0_SET HW(DCP_CSCCTRL0_SET) +#define HWA_DCP_CSCCTRL0_SET (HWA_DCP_CSCCTRL0 + 0x4) +#define HWT_DCP_CSCCTRL0_SET HWIO_32_WO +#define HWN_DCP_CSCCTRL0_SET DCP_CSCCTRL0 +#define HWI_DCP_CSCCTRL0_SET +#define HW_DCP_CSCCTRL0_CLR HW(DCP_CSCCTRL0_CLR) +#define HWA_DCP_CSCCTRL0_CLR (HWA_DCP_CSCCTRL0 + 0x8) +#define HWT_DCP_CSCCTRL0_CLR HWIO_32_WO +#define HWN_DCP_CSCCTRL0_CLR DCP_CSCCTRL0 +#define HWI_DCP_CSCCTRL0_CLR +#define HW_DCP_CSCCTRL0_TOG HW(DCP_CSCCTRL0_TOG) +#define HWA_DCP_CSCCTRL0_TOG (HWA_DCP_CSCCTRL0 + 0xc) +#define HWT_DCP_CSCCTRL0_TOG HWIO_32_WO +#define HWN_DCP_CSCCTRL0_TOG DCP_CSCCTRL0 +#define HWI_DCP_CSCCTRL0_TOG +#define BP_DCP_CSCCTRL0_RSVD1 16 +#define BM_DCP_CSCCTRL0_RSVD1 0xffff0000 +#define BF_DCP_CSCCTRL0_RSVD1(v) (((v) & 0xffff) << 16) +#define BFM_DCP_CSCCTRL0_RSVD1(v) BM_DCP_CSCCTRL0_RSVD1 +#define BF_DCP_CSCCTRL0_RSVD1_V(e) BF_DCP_CSCCTRL0_RSVD1(BV_DCP_CSCCTRL0_RSVD1__##e) +#define BFM_DCP_CSCCTRL0_RSVD1_V(v) BM_DCP_CSCCTRL0_RSVD1 +#define BP_DCP_CSCCTRL0_CLIP 15 +#define BM_DCP_CSCCTRL0_CLIP 0x8000 +#define BF_DCP_CSCCTRL0_CLIP(v) (((v) & 0x1) << 15) +#define BFM_DCP_CSCCTRL0_CLIP(v) BM_DCP_CSCCTRL0_CLIP +#define BF_DCP_CSCCTRL0_CLIP_V(e) BF_DCP_CSCCTRL0_CLIP(BV_DCP_CSCCTRL0_CLIP__##e) +#define BFM_DCP_CSCCTRL0_CLIP_V(v) BM_DCP_CSCCTRL0_CLIP +#define BP_DCP_CSCCTRL0_UPSAMPLE 14 +#define BM_DCP_CSCCTRL0_UPSAMPLE 0x4000 +#define BF_DCP_CSCCTRL0_UPSAMPLE(v) (((v) & 0x1) << 14) +#define BFM_DCP_CSCCTRL0_UPSAMPLE(v) BM_DCP_CSCCTRL0_UPSAMPLE +#define BF_DCP_CSCCTRL0_UPSAMPLE_V(e) BF_DCP_CSCCTRL0_UPSAMPLE(BV_DCP_CSCCTRL0_UPSAMPLE__##e) +#define BFM_DCP_CSCCTRL0_UPSAMPLE_V(v) BM_DCP_CSCCTRL0_UPSAMPLE +#define BP_DCP_CSCCTRL0_SCALE 13 +#define BM_DCP_CSCCTRL0_SCALE 0x2000 +#define BF_DCP_CSCCTRL0_SCALE(v) (((v) & 0x1) << 13) +#define BFM_DCP_CSCCTRL0_SCALE(v) BM_DCP_CSCCTRL0_SCALE +#define BF_DCP_CSCCTRL0_SCALE_V(e) BF_DCP_CSCCTRL0_SCALE(BV_DCP_CSCCTRL0_SCALE__##e) +#define BFM_DCP_CSCCTRL0_SCALE_V(v) BM_DCP_CSCCTRL0_SCALE +#define BP_DCP_CSCCTRL0_ROTATE 12 +#define BM_DCP_CSCCTRL0_ROTATE 0x1000 +#define BF_DCP_CSCCTRL0_ROTATE(v) (((v) & 0x1) << 12) +#define BFM_DCP_CSCCTRL0_ROTATE(v) BM_DCP_CSCCTRL0_ROTATE +#define BF_DCP_CSCCTRL0_ROTATE_V(e) BF_DCP_CSCCTRL0_ROTATE(BV_DCP_CSCCTRL0_ROTATE__##e) +#define BFM_DCP_CSCCTRL0_ROTATE_V(v) BM_DCP_CSCCTRL0_ROTATE +#define BP_DCP_CSCCTRL0_SUBSAMPLE 11 +#define BM_DCP_CSCCTRL0_SUBSAMPLE 0x800 +#define BF_DCP_CSCCTRL0_SUBSAMPLE(v) (((v) & 0x1) << 11) +#define BFM_DCP_CSCCTRL0_SUBSAMPLE(v) BM_DCP_CSCCTRL0_SUBSAMPLE +#define BF_DCP_CSCCTRL0_SUBSAMPLE_V(e) BF_DCP_CSCCTRL0_SUBSAMPLE(BV_DCP_CSCCTRL0_SUBSAMPLE__##e) +#define BFM_DCP_CSCCTRL0_SUBSAMPLE_V(v) BM_DCP_CSCCTRL0_SUBSAMPLE +#define BP_DCP_CSCCTRL0_DELTA 10 +#define BM_DCP_CSCCTRL0_DELTA 0x400 +#define BF_DCP_CSCCTRL0_DELTA(v) (((v) & 0x1) << 10) +#define BFM_DCP_CSCCTRL0_DELTA(v) BM_DCP_CSCCTRL0_DELTA +#define BF_DCP_CSCCTRL0_DELTA_V(e) BF_DCP_CSCCTRL0_DELTA(BV_DCP_CSCCTRL0_DELTA__##e) +#define BFM_DCP_CSCCTRL0_DELTA_V(v) BM_DCP_CSCCTRL0_DELTA +#define BP_DCP_CSCCTRL0_RGB_FORMAT 8 +#define BM_DCP_CSCCTRL0_RGB_FORMAT 0x300 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565 0x0 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__YCbCrI 0x1 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24 0x2 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I 0x3 +#define BF_DCP_CSCCTRL0_RGB_FORMAT(v) (((v) & 0x3) << 8) +#define BFM_DCP_CSCCTRL0_RGB_FORMAT(v) BM_DCP_CSCCTRL0_RGB_FORMAT +#define BF_DCP_CSCCTRL0_RGB_FORMAT_V(e) BF_DCP_CSCCTRL0_RGB_FORMAT(BV_DCP_CSCCTRL0_RGB_FORMAT__##e) +#define BFM_DCP_CSCCTRL0_RGB_FORMAT_V(v) BM_DCP_CSCCTRL0_RGB_FORMAT +#define BP_DCP_CSCCTRL0_YUV_FORMAT 4 +#define BM_DCP_CSCCTRL0_YUV_FORMAT 0xf0 +#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420 0x0 +#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422 0x2 +#define BF_DCP_CSCCTRL0_YUV_FORMAT(v) (((v) & 0xf) << 4) +#define BFM_DCP_CSCCTRL0_YUV_FORMAT(v) BM_DCP_CSCCTRL0_YUV_FORMAT +#define BF_DCP_CSCCTRL0_YUV_FORMAT_V(e) BF_DCP_CSCCTRL0_YUV_FORMAT(BV_DCP_CSCCTRL0_YUV_FORMAT__##e) +#define BFM_DCP_CSCCTRL0_YUV_FORMAT_V(v) BM_DCP_CSCCTRL0_YUV_FORMAT +#define BP_DCP_CSCCTRL0_RSVD0 1 +#define BM_DCP_CSCCTRL0_RSVD0 0xe +#define BF_DCP_CSCCTRL0_RSVD0(v) (((v) & 0x7) << 1) +#define BFM_DCP_CSCCTRL0_RSVD0(v) BM_DCP_CSCCTRL0_RSVD0 +#define BF_DCP_CSCCTRL0_RSVD0_V(e) BF_DCP_CSCCTRL0_RSVD0(BV_DCP_CSCCTRL0_RSVD0__##e) +#define BFM_DCP_CSCCTRL0_RSVD0_V(v) BM_DCP_CSCCTRL0_RSVD0 +#define BP_DCP_CSCCTRL0_ENABLE 0 +#define BM_DCP_CSCCTRL0_ENABLE 0x1 +#define BF_DCP_CSCCTRL0_ENABLE(v) (((v) & 0x1) << 0) +#define BFM_DCP_CSCCTRL0_ENABLE(v) BM_DCP_CSCCTRL0_ENABLE +#define BF_DCP_CSCCTRL0_ENABLE_V(e) BF_DCP_CSCCTRL0_ENABLE(BV_DCP_CSCCTRL0_ENABLE__##e) +#define BFM_DCP_CSCCTRL0_ENABLE_V(v) BM_DCP_CSCCTRL0_ENABLE + +#define HW_DCP_CSCSTAT HW(DCP_CSCSTAT) +#define HWA_DCP_CSCSTAT (0x80028000 + 0x310) +#define HWT_DCP_CSCSTAT HWIO_32_RW +#define HWN_DCP_CSCSTAT DCP_CSCSTAT +#define HWI_DCP_CSCSTAT +#define HW_DCP_CSCSTAT_SET HW(DCP_CSCSTAT_SET) +#define HWA_DCP_CSCSTAT_SET (HWA_DCP_CSCSTAT + 0x4) +#define HWT_DCP_CSCSTAT_SET HWIO_32_WO +#define HWN_DCP_CSCSTAT_SET DCP_CSCSTAT +#define HWI_DCP_CSCSTAT_SET +#define HW_DCP_CSCSTAT_CLR HW(DCP_CSCSTAT_CLR) +#define HWA_DCP_CSCSTAT_CLR (HWA_DCP_CSCSTAT + 0x8) +#define HWT_DCP_CSCSTAT_CLR HWIO_32_WO +#define HWN_DCP_CSCSTAT_CLR DCP_CSCSTAT +#define HWI_DCP_CSCSTAT_CLR +#define HW_DCP_CSCSTAT_TOG HW(DCP_CSCSTAT_TOG) +#define HWA_DCP_CSCSTAT_TOG (HWA_DCP_CSCSTAT + 0xc) +#define HWT_DCP_CSCSTAT_TOG HWIO_32_WO +#define HWN_DCP_CSCSTAT_TOG DCP_CSCSTAT +#define HWI_DCP_CSCSTAT_TOG +#define BP_DCP_CSCSTAT_RSVD3 24 +#define BM_DCP_CSCSTAT_RSVD3 0xff000000 +#define BF_DCP_CSCSTAT_RSVD3(v) (((v) & 0xff) << 24) +#define BFM_DCP_CSCSTAT_RSVD3(v) BM_DCP_CSCSTAT_RSVD3 +#define BF_DCP_CSCSTAT_RSVD3_V(e) BF_DCP_CSCSTAT_RSVD3(BV_DCP_CSCSTAT_RSVD3__##e) +#define BFM_DCP_CSCSTAT_RSVD3_V(v) BM_DCP_CSCSTAT_RSVD3 +#define BP_DCP_CSCSTAT_ERROR_CODE 16 +#define BM_DCP_CSCSTAT_ERROR_CODE 0xff0000 +#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x1 +#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x2 +#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x3 +#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x4 +#define BF_DCP_CSCSTAT_ERROR_CODE(v) (((v) & 0xff) << 16) +#define BFM_DCP_CSCSTAT_ERROR_CODE(v) BM_DCP_CSCSTAT_ERROR_CODE +#define BF_DCP_CSCSTAT_ERROR_CODE_V(e) BF_DCP_CSCSTAT_ERROR_CODE(BV_DCP_CSCSTAT_ERROR_CODE__##e) +#define BFM_DCP_CSCSTAT_ERROR_CODE_V(v) BM_DCP_CSCSTAT_ERROR_CODE +#define BP_DCP_CSCSTAT_RSVD2 7 +#define BM_DCP_CSCSTAT_RSVD2 0xff80 +#define BF_DCP_CSCSTAT_RSVD2(v) (((v) & 0x1ff) << 7) +#define BFM_DCP_CSCSTAT_RSVD2(v) BM_DCP_CSCSTAT_RSVD2 +#define BF_DCP_CSCSTAT_RSVD2_V(e) BF_DCP_CSCSTAT_RSVD2(BV_DCP_CSCSTAT_RSVD2__##e) +#define BFM_DCP_CSCSTAT_RSVD2_V(v) BM_DCP_CSCSTAT_RSVD2 +#define BP_DCP_CSCSTAT_ERROR_PAGEFAULT 6 +#define BM_DCP_CSCSTAT_ERROR_PAGEFAULT 0x40 +#define BF_DCP_CSCSTAT_ERROR_PAGEFAULT(v) (((v) & 0x1) << 6) +#define BFM_DCP_CSCSTAT_ERROR_PAGEFAULT(v) BM_DCP_CSCSTAT_ERROR_PAGEFAULT +#define BF_DCP_CSCSTAT_ERROR_PAGEFAULT_V(e) BF_DCP_CSCSTAT_ERROR_PAGEFAULT(BV_DCP_CSCSTAT_ERROR_PAGEFAULT__##e) +#define BFM_DCP_CSCSTAT_ERROR_PAGEFAULT_V(v) BM_DCP_CSCSTAT_ERROR_PAGEFAULT +#define BP_DCP_CSCSTAT_ERROR_DST 5 +#define BM_DCP_CSCSTAT_ERROR_DST 0x20 +#define BF_DCP_CSCSTAT_ERROR_DST(v) (((v) & 0x1) << 5) +#define BFM_DCP_CSCSTAT_ERROR_DST(v) BM_DCP_CSCSTAT_ERROR_DST +#define BF_DCP_CSCSTAT_ERROR_DST_V(e) BF_DCP_CSCSTAT_ERROR_DST(BV_DCP_CSCSTAT_ERROR_DST__##e) +#define BFM_DCP_CSCSTAT_ERROR_DST_V(v) BM_DCP_CSCSTAT_ERROR_DST +#define BP_DCP_CSCSTAT_ERROR_SRC 4 +#define BM_DCP_CSCSTAT_ERROR_SRC 0x10 +#define BF_DCP_CSCSTAT_ERROR_SRC(v) (((v) & 0x1) << 4) +#define BFM_DCP_CSCSTAT_ERROR_SRC(v) BM_DCP_CSCSTAT_ERROR_SRC +#define BF_DCP_CSCSTAT_ERROR_SRC_V(e) BF_DCP_CSCSTAT_ERROR_SRC(BV_DCP_CSCSTAT_ERROR_SRC__##e) +#define BFM_DCP_CSCSTAT_ERROR_SRC_V(v) BM_DCP_CSCSTAT_ERROR_SRC +#define BP_DCP_CSCSTAT_RSVD1 3 +#define BM_DCP_CSCSTAT_RSVD1 0x8 +#define BF_DCP_CSCSTAT_RSVD1(v) (((v) & 0x1) << 3) +#define BFM_DCP_CSCSTAT_RSVD1(v) BM_DCP_CSCSTAT_RSVD1 +#define BF_DCP_CSCSTAT_RSVD1_V(e) BF_DCP_CSCSTAT_RSVD1(BV_DCP_CSCSTAT_RSVD1__##e) +#define BFM_DCP_CSCSTAT_RSVD1_V(v) BM_DCP_CSCSTAT_RSVD1 +#define BP_DCP_CSCSTAT_ERROR_SETUP 2 +#define BM_DCP_CSCSTAT_ERROR_SETUP 0x4 +#define BF_DCP_CSCSTAT_ERROR_SETUP(v) (((v) & 0x1) << 2) +#define BFM_DCP_CSCSTAT_ERROR_SETUP(v) BM_DCP_CSCSTAT_ERROR_SETUP +#define BF_DCP_CSCSTAT_ERROR_SETUP_V(e) BF_DCP_CSCSTAT_ERROR_SETUP(BV_DCP_CSCSTAT_ERROR_SETUP__##e) +#define BFM_DCP_CSCSTAT_ERROR_SETUP_V(v) BM_DCP_CSCSTAT_ERROR_SETUP +#define BP_DCP_CSCSTAT_RSVD0 1 +#define BM_DCP_CSCSTAT_RSVD0 0x2 +#define BF_DCP_CSCSTAT_RSVD0(v) (((v) & 0x1) << 1) +#define BFM_DCP_CSCSTAT_RSVD0(v) BM_DCP_CSCSTAT_RSVD0 +#define BF_DCP_CSCSTAT_RSVD0_V(e) BF_DCP_CSCSTAT_RSVD0(BV_DCP_CSCSTAT_RSVD0__##e) +#define BFM_DCP_CSCSTAT_RSVD0_V(v) BM_DCP_CSCSTAT_RSVD0 +#define BP_DCP_CSCSTAT_COMPLETE 0 +#define BM_DCP_CSCSTAT_COMPLETE 0x1 +#define BF_DCP_CSCSTAT_COMPLETE(v) (((v) & 0x1) << 0) +#define BFM_DCP_CSCSTAT_COMPLETE(v) BM_DCP_CSCSTAT_COMPLETE +#define BF_DCP_CSCSTAT_COMPLETE_V(e) BF_DCP_CSCSTAT_COMPLETE(BV_DCP_CSCSTAT_COMPLETE__##e) +#define BFM_DCP_CSCSTAT_COMPLETE_V(v) BM_DCP_CSCSTAT_COMPLETE + +#define HW_DCP_CSCOUTBUFPARAM HW(DCP_CSCOUTBUFPARAM) +#define HWA_DCP_CSCOUTBUFPARAM (0x80028000 + 0x320) +#define HWT_DCP_CSCOUTBUFPARAM HWIO_32_RW +#define HWN_DCP_CSCOUTBUFPARAM DCP_CSCOUTBUFPARAM +#define HWI_DCP_CSCOUTBUFPARAM +#define BP_DCP_CSCOUTBUFPARAM_RSVD1 24 +#define BM_DCP_CSCOUTBUFPARAM_RSVD1 0xff000000 +#define BF_DCP_CSCOUTBUFPARAM_RSVD1(v) (((v) & 0xff) << 24) +#define BFM_DCP_CSCOUTBUFPARAM_RSVD1(v) BM_DCP_CSCOUTBUFPARAM_RSVD1 +#define BF_DCP_CSCOUTBUFPARAM_RSVD1_V(e) BF_DCP_CSCOUTBUFPARAM_RSVD1(BV_DCP_CSCOUTBUFPARAM_RSVD1__##e) +#define BFM_DCP_CSCOUTBUFPARAM_RSVD1_V(v) BM_DCP_CSCOUTBUFPARAM_RSVD1 +#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE 12 +#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE 0xfff000 +#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) (((v) & 0xfff) << 12) +#define BFM_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE +#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE_V(e) BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(BV_DCP_CSCOUTBUFPARAM_FIELD_SIZE__##e) +#define BFM_DCP_CSCOUTBUFPARAM_FIELD_SIZE_V(v) BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE +#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE 0 +#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE 0xfff +#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_DCP_CSCOUTBUFPARAM_LINE_SIZE(v) BM_DCP_CSCOUTBUFPARAM_LINE_SIZE +#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE_V(e) BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(BV_DCP_CSCOUTBUFPARAM_LINE_SIZE__##e) +#define BFM_DCP_CSCOUTBUFPARAM_LINE_SIZE_V(v) BM_DCP_CSCOUTBUFPARAM_LINE_SIZE + +#define HW_DCP_CSCINBUFPARAM HW(DCP_CSCINBUFPARAM) +#define HWA_DCP_CSCINBUFPARAM (0x80028000 + 0x330) +#define HWT_DCP_CSCINBUFPARAM HWIO_32_RW +#define HWN_DCP_CSCINBUFPARAM DCP_CSCINBUFPARAM +#define HWI_DCP_CSCINBUFPARAM +#define BP_DCP_CSCINBUFPARAM_RSVD1 12 +#define BM_DCP_CSCINBUFPARAM_RSVD1 0xfffff000 +#define BF_DCP_CSCINBUFPARAM_RSVD1(v) (((v) & 0xfffff) << 12) +#define BFM_DCP_CSCINBUFPARAM_RSVD1(v) BM_DCP_CSCINBUFPARAM_RSVD1 +#define BF_DCP_CSCINBUFPARAM_RSVD1_V(e) BF_DCP_CSCINBUFPARAM_RSVD1(BV_DCP_CSCINBUFPARAM_RSVD1__##e) +#define BFM_DCP_CSCINBUFPARAM_RSVD1_V(v) BM_DCP_CSCINBUFPARAM_RSVD1 +#define BP_DCP_CSCINBUFPARAM_LINE_SIZE 0 +#define BM_DCP_CSCINBUFPARAM_LINE_SIZE 0xfff +#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v) (((v) & 0xfff) << 0) +#define BFM_DCP_CSCINBUFPARAM_LINE_SIZE(v) BM_DCP_CSCINBUFPARAM_LINE_SIZE +#define BF_DCP_CSCINBUFPARAM_LINE_SIZE_V(e) BF_DCP_CSCINBUFPARAM_LINE_SIZE(BV_DCP_CSCINBUFPARAM_LINE_SIZE__##e) +#define BFM_DCP_CSCINBUFPARAM_LINE_SIZE_V(v) BM_DCP_CSCINBUFPARAM_LINE_SIZE + +#define HW_DCP_CSCRGB HW(DCP_CSCRGB) +#define HWA_DCP_CSCRGB (0x80028000 + 0x340) +#define HWT_DCP_CSCRGB HWIO_32_RW +#define HWN_DCP_CSCRGB DCP_CSCRGB +#define HWI_DCP_CSCRGB +#define BP_DCP_CSCRGB_ADDR 0 +#define BM_DCP_CSCRGB_ADDR 0xffffffff +#define BF_DCP_CSCRGB_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_CSCRGB_ADDR(v) BM_DCP_CSCRGB_ADDR +#define BF_DCP_CSCRGB_ADDR_V(e) BF_DCP_CSCRGB_ADDR(BV_DCP_CSCRGB_ADDR__##e) +#define BFM_DCP_CSCRGB_ADDR_V(v) BM_DCP_CSCRGB_ADDR + +#define HW_DCP_CSCLUMA HW(DCP_CSCLUMA) +#define HWA_DCP_CSCLUMA (0x80028000 + 0x350) +#define HWT_DCP_CSCLUMA HWIO_32_RW +#define HWN_DCP_CSCLUMA DCP_CSCLUMA +#define HWI_DCP_CSCLUMA +#define BP_DCP_CSCLUMA_ADDR 0 +#define BM_DCP_CSCLUMA_ADDR 0xffffffff +#define BF_DCP_CSCLUMA_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_CSCLUMA_ADDR(v) BM_DCP_CSCLUMA_ADDR +#define BF_DCP_CSCLUMA_ADDR_V(e) BF_DCP_CSCLUMA_ADDR(BV_DCP_CSCLUMA_ADDR__##e) +#define BFM_DCP_CSCLUMA_ADDR_V(v) BM_DCP_CSCLUMA_ADDR + +#define HW_DCP_CSCCHROMAU HW(DCP_CSCCHROMAU) +#define HWA_DCP_CSCCHROMAU (0x80028000 + 0x360) +#define HWT_DCP_CSCCHROMAU HWIO_32_RW +#define HWN_DCP_CSCCHROMAU DCP_CSCCHROMAU +#define HWI_DCP_CSCCHROMAU +#define BP_DCP_CSCCHROMAU_ADDR 0 +#define BM_DCP_CSCCHROMAU_ADDR 0xffffffff +#define BF_DCP_CSCCHROMAU_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_CSCCHROMAU_ADDR(v) BM_DCP_CSCCHROMAU_ADDR +#define BF_DCP_CSCCHROMAU_ADDR_V(e) BF_DCP_CSCCHROMAU_ADDR(BV_DCP_CSCCHROMAU_ADDR__##e) +#define BFM_DCP_CSCCHROMAU_ADDR_V(v) BM_DCP_CSCCHROMAU_ADDR + +#define HW_DCP_CSCCHROMAV HW(DCP_CSCCHROMAV) +#define HWA_DCP_CSCCHROMAV (0x80028000 + 0x370) +#define HWT_DCP_CSCCHROMAV HWIO_32_RW +#define HWN_DCP_CSCCHROMAV DCP_CSCCHROMAV +#define HWI_DCP_CSCCHROMAV +#define BP_DCP_CSCCHROMAV_ADDR 0 +#define BM_DCP_CSCCHROMAV_ADDR 0xffffffff +#define BF_DCP_CSCCHROMAV_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_CSCCHROMAV_ADDR(v) BM_DCP_CSCCHROMAV_ADDR +#define BF_DCP_CSCCHROMAV_ADDR_V(e) BF_DCP_CSCCHROMAV_ADDR(BV_DCP_CSCCHROMAV_ADDR__##e) +#define BFM_DCP_CSCCHROMAV_ADDR_V(v) BM_DCP_CSCCHROMAV_ADDR + +#define HW_DCP_CSCCOEFF0 HW(DCP_CSCCOEFF0) +#define HWA_DCP_CSCCOEFF0 (0x80028000 + 0x380) +#define HWT_DCP_CSCCOEFF0 HWIO_32_RW +#define HWN_DCP_CSCCOEFF0 DCP_CSCCOEFF0 +#define HWI_DCP_CSCCOEFF0 +#define BP_DCP_CSCCOEFF0_RSVD1 26 +#define BM_DCP_CSCCOEFF0_RSVD1 0xfc000000 +#define BF_DCP_CSCCOEFF0_RSVD1(v) (((v) & 0x3f) << 26) +#define BFM_DCP_CSCCOEFF0_RSVD1(v) BM_DCP_CSCCOEFF0_RSVD1 +#define BF_DCP_CSCCOEFF0_RSVD1_V(e) BF_DCP_CSCCOEFF0_RSVD1(BV_DCP_CSCCOEFF0_RSVD1__##e) +#define BFM_DCP_CSCCOEFF0_RSVD1_V(v) BM_DCP_CSCCOEFF0_RSVD1 +#define BP_DCP_CSCCOEFF0_C0 16 +#define BM_DCP_CSCCOEFF0_C0 0x3ff0000 +#define BF_DCP_CSCCOEFF0_C0(v) (((v) & 0x3ff) << 16) +#define BFM_DCP_CSCCOEFF0_C0(v) BM_DCP_CSCCOEFF0_C0 +#define BF_DCP_CSCCOEFF0_C0_V(e) BF_DCP_CSCCOEFF0_C0(BV_DCP_CSCCOEFF0_C0__##e) +#define BFM_DCP_CSCCOEFF0_C0_V(v) BM_DCP_CSCCOEFF0_C0 +#define BP_DCP_CSCCOEFF0_UV_OFFSET 8 +#define BM_DCP_CSCCOEFF0_UV_OFFSET 0xff00 +#define BF_DCP_CSCCOEFF0_UV_OFFSET(v) (((v) & 0xff) << 8) +#define BFM_DCP_CSCCOEFF0_UV_OFFSET(v) BM_DCP_CSCCOEFF0_UV_OFFSET +#define BF_DCP_CSCCOEFF0_UV_OFFSET_V(e) BF_DCP_CSCCOEFF0_UV_OFFSET(BV_DCP_CSCCOEFF0_UV_OFFSET__##e) +#define BFM_DCP_CSCCOEFF0_UV_OFFSET_V(v) BM_DCP_CSCCOEFF0_UV_OFFSET +#define BP_DCP_CSCCOEFF0_Y_OFFSET 0 +#define BM_DCP_CSCCOEFF0_Y_OFFSET 0xff +#define BF_DCP_CSCCOEFF0_Y_OFFSET(v) (((v) & 0xff) << 0) +#define BFM_DCP_CSCCOEFF0_Y_OFFSET(v) BM_DCP_CSCCOEFF0_Y_OFFSET +#define BF_DCP_CSCCOEFF0_Y_OFFSET_V(e) BF_DCP_CSCCOEFF0_Y_OFFSET(BV_DCP_CSCCOEFF0_Y_OFFSET__##e) +#define BFM_DCP_CSCCOEFF0_Y_OFFSET_V(v) BM_DCP_CSCCOEFF0_Y_OFFSET + +#define HW_DCP_CSCCOEFF1 HW(DCP_CSCCOEFF1) +#define HWA_DCP_CSCCOEFF1 (0x80028000 + 0x390) +#define HWT_DCP_CSCCOEFF1 HWIO_32_RW +#define HWN_DCP_CSCCOEFF1 DCP_CSCCOEFF1 +#define HWI_DCP_CSCCOEFF1 +#define BP_DCP_CSCCOEFF1_RSVD1 26 +#define BM_DCP_CSCCOEFF1_RSVD1 0xfc000000 +#define BF_DCP_CSCCOEFF1_RSVD1(v) (((v) & 0x3f) << 26) +#define BFM_DCP_CSCCOEFF1_RSVD1(v) BM_DCP_CSCCOEFF1_RSVD1 +#define BF_DCP_CSCCOEFF1_RSVD1_V(e) BF_DCP_CSCCOEFF1_RSVD1(BV_DCP_CSCCOEFF1_RSVD1__##e) +#define BFM_DCP_CSCCOEFF1_RSVD1_V(v) BM_DCP_CSCCOEFF1_RSVD1 +#define BP_DCP_CSCCOEFF1_C1 16 +#define BM_DCP_CSCCOEFF1_C1 0x3ff0000 +#define BF_DCP_CSCCOEFF1_C1(v) (((v) & 0x3ff) << 16) +#define BFM_DCP_CSCCOEFF1_C1(v) BM_DCP_CSCCOEFF1_C1 +#define BF_DCP_CSCCOEFF1_C1_V(e) BF_DCP_CSCCOEFF1_C1(BV_DCP_CSCCOEFF1_C1__##e) +#define BFM_DCP_CSCCOEFF1_C1_V(v) BM_DCP_CSCCOEFF1_C1 +#define BP_DCP_CSCCOEFF1_RSVD0 10 +#define BM_DCP_CSCCOEFF1_RSVD0 0xfc00 +#define BF_DCP_CSCCOEFF1_RSVD0(v) (((v) & 0x3f) << 10) +#define BFM_DCP_CSCCOEFF1_RSVD0(v) BM_DCP_CSCCOEFF1_RSVD0 +#define BF_DCP_CSCCOEFF1_RSVD0_V(e) BF_DCP_CSCCOEFF1_RSVD0(BV_DCP_CSCCOEFF1_RSVD0__##e) +#define BFM_DCP_CSCCOEFF1_RSVD0_V(v) BM_DCP_CSCCOEFF1_RSVD0 +#define BP_DCP_CSCCOEFF1_C4 0 +#define BM_DCP_CSCCOEFF1_C4 0x3ff +#define BF_DCP_CSCCOEFF1_C4(v) (((v) & 0x3ff) << 0) +#define BFM_DCP_CSCCOEFF1_C4(v) BM_DCP_CSCCOEFF1_C4 +#define BF_DCP_CSCCOEFF1_C4_V(e) BF_DCP_CSCCOEFF1_C4(BV_DCP_CSCCOEFF1_C4__##e) +#define BFM_DCP_CSCCOEFF1_C4_V(v) BM_DCP_CSCCOEFF1_C4 + +#define HW_DCP_CSCCOEFF2 HW(DCP_CSCCOEFF2) +#define HWA_DCP_CSCCOEFF2 (0x80028000 + 0x3a0) +#define HWT_DCP_CSCCOEFF2 HWIO_32_RW +#define HWN_DCP_CSCCOEFF2 DCP_CSCCOEFF2 +#define HWI_DCP_CSCCOEFF2 +#define BP_DCP_CSCCOEFF2_RSVD1 26 +#define BM_DCP_CSCCOEFF2_RSVD1 0xfc000000 +#define BF_DCP_CSCCOEFF2_RSVD1(v) (((v) & 0x3f) << 26) +#define BFM_DCP_CSCCOEFF2_RSVD1(v) BM_DCP_CSCCOEFF2_RSVD1 +#define BF_DCP_CSCCOEFF2_RSVD1_V(e) BF_DCP_CSCCOEFF2_RSVD1(BV_DCP_CSCCOEFF2_RSVD1__##e) +#define BFM_DCP_CSCCOEFF2_RSVD1_V(v) BM_DCP_CSCCOEFF2_RSVD1 +#define BP_DCP_CSCCOEFF2_C2 16 +#define BM_DCP_CSCCOEFF2_C2 0x3ff0000 +#define BF_DCP_CSCCOEFF2_C2(v) (((v) & 0x3ff) << 16) +#define BFM_DCP_CSCCOEFF2_C2(v) BM_DCP_CSCCOEFF2_C2 +#define BF_DCP_CSCCOEFF2_C2_V(e) BF_DCP_CSCCOEFF2_C2(BV_DCP_CSCCOEFF2_C2__##e) +#define BFM_DCP_CSCCOEFF2_C2_V(v) BM_DCP_CSCCOEFF2_C2 +#define BP_DCP_CSCCOEFF2_RSVD0 10 +#define BM_DCP_CSCCOEFF2_RSVD0 0xfc00 +#define BF_DCP_CSCCOEFF2_RSVD0(v) (((v) & 0x3f) << 10) +#define BFM_DCP_CSCCOEFF2_RSVD0(v) BM_DCP_CSCCOEFF2_RSVD0 +#define BF_DCP_CSCCOEFF2_RSVD0_V(e) BF_DCP_CSCCOEFF2_RSVD0(BV_DCP_CSCCOEFF2_RSVD0__##e) +#define BFM_DCP_CSCCOEFF2_RSVD0_V(v) BM_DCP_CSCCOEFF2_RSVD0 +#define BP_DCP_CSCCOEFF2_C3 0 +#define BM_DCP_CSCCOEFF2_C3 0x3ff +#define BF_DCP_CSCCOEFF2_C3(v) (((v) & 0x3ff) << 0) +#define BFM_DCP_CSCCOEFF2_C3(v) BM_DCP_CSCCOEFF2_C3 +#define BF_DCP_CSCCOEFF2_C3_V(e) BF_DCP_CSCCOEFF2_C3(BV_DCP_CSCCOEFF2_C3__##e) +#define BFM_DCP_CSCCOEFF2_C3_V(v) BM_DCP_CSCCOEFF2_C3 + +#define HW_DCP_CSCCLIP HW(DCP_CSCCLIP) +#define HWA_DCP_CSCCLIP (0x80028000 + 0x3d0) +#define HWT_DCP_CSCCLIP HWIO_32_RW +#define HWN_DCP_CSCCLIP DCP_CSCCLIP +#define HWI_DCP_CSCCLIP +#define BP_DCP_CSCCLIP_RSVD1 24 +#define BM_DCP_CSCCLIP_RSVD1 0xff000000 +#define BF_DCP_CSCCLIP_RSVD1(v) (((v) & 0xff) << 24) +#define BFM_DCP_CSCCLIP_RSVD1(v) BM_DCP_CSCCLIP_RSVD1 +#define BF_DCP_CSCCLIP_RSVD1_V(e) BF_DCP_CSCCLIP_RSVD1(BV_DCP_CSCCLIP_RSVD1__##e) +#define BFM_DCP_CSCCLIP_RSVD1_V(v) BM_DCP_CSCCLIP_RSVD1 +#define BP_DCP_CSCCLIP_HEIGHT 12 +#define BM_DCP_CSCCLIP_HEIGHT 0xfff000 +#define BF_DCP_CSCCLIP_HEIGHT(v) (((v) & 0xfff) << 12) +#define BFM_DCP_CSCCLIP_HEIGHT(v) BM_DCP_CSCCLIP_HEIGHT +#define BF_DCP_CSCCLIP_HEIGHT_V(e) BF_DCP_CSCCLIP_HEIGHT(BV_DCP_CSCCLIP_HEIGHT__##e) +#define BFM_DCP_CSCCLIP_HEIGHT_V(v) BM_DCP_CSCCLIP_HEIGHT +#define BP_DCP_CSCCLIP_WIDTH 0 +#define BM_DCP_CSCCLIP_WIDTH 0xfff +#define BF_DCP_CSCCLIP_WIDTH(v) (((v) & 0xfff) << 0) +#define BFM_DCP_CSCCLIP_WIDTH(v) BM_DCP_CSCCLIP_WIDTH +#define BF_DCP_CSCCLIP_WIDTH_V(e) BF_DCP_CSCCLIP_WIDTH(BV_DCP_CSCCLIP_WIDTH__##e) +#define BFM_DCP_CSCCLIP_WIDTH_V(v) BM_DCP_CSCCLIP_WIDTH + +#define HW_DCP_CSCXSCALE HW(DCP_CSCXSCALE) +#define HWA_DCP_CSCXSCALE (0x80028000 + 0x3e0) +#define HWT_DCP_CSCXSCALE HWIO_32_RW +#define HWN_DCP_CSCXSCALE DCP_CSCXSCALE +#define HWI_DCP_CSCXSCALE +#define BP_DCP_CSCXSCALE_RSVD1 26 +#define BM_DCP_CSCXSCALE_RSVD1 0xfc000000 +#define BF_DCP_CSCXSCALE_RSVD1(v) (((v) & 0x3f) << 26) +#define BFM_DCP_CSCXSCALE_RSVD1(v) BM_DCP_CSCXSCALE_RSVD1 +#define BF_DCP_CSCXSCALE_RSVD1_V(e) BF_DCP_CSCXSCALE_RSVD1(BV_DCP_CSCXSCALE_RSVD1__##e) +#define BFM_DCP_CSCXSCALE_RSVD1_V(v) BM_DCP_CSCXSCALE_RSVD1 +#define BP_DCP_CSCXSCALE_INT 24 +#define BM_DCP_CSCXSCALE_INT 0x3000000 +#define BF_DCP_CSCXSCALE_INT(v) (((v) & 0x3) << 24) +#define BFM_DCP_CSCXSCALE_INT(v) BM_DCP_CSCXSCALE_INT +#define BF_DCP_CSCXSCALE_INT_V(e) BF_DCP_CSCXSCALE_INT(BV_DCP_CSCXSCALE_INT__##e) +#define BFM_DCP_CSCXSCALE_INT_V(v) BM_DCP_CSCXSCALE_INT +#define BP_DCP_CSCXSCALE_FRAC 12 +#define BM_DCP_CSCXSCALE_FRAC 0xfff000 +#define BF_DCP_CSCXSCALE_FRAC(v) (((v) & 0xfff) << 12) +#define BFM_DCP_CSCXSCALE_FRAC(v) BM_DCP_CSCXSCALE_FRAC +#define BF_DCP_CSCXSCALE_FRAC_V(e) BF_DCP_CSCXSCALE_FRAC(BV_DCP_CSCXSCALE_FRAC__##e) +#define BFM_DCP_CSCXSCALE_FRAC_V(v) BM_DCP_CSCXSCALE_FRAC +#define BP_DCP_CSCXSCALE_WIDTH 0 +#define BM_DCP_CSCXSCALE_WIDTH 0xfff +#define BF_DCP_CSCXSCALE_WIDTH(v) (((v) & 0xfff) << 0) +#define BFM_DCP_CSCXSCALE_WIDTH(v) BM_DCP_CSCXSCALE_WIDTH +#define BF_DCP_CSCXSCALE_WIDTH_V(e) BF_DCP_CSCXSCALE_WIDTH(BV_DCP_CSCXSCALE_WIDTH__##e) +#define BFM_DCP_CSCXSCALE_WIDTH_V(v) BM_DCP_CSCXSCALE_WIDTH + +#define HW_DCP_CSCYSCALE HW(DCP_CSCYSCALE) +#define HWA_DCP_CSCYSCALE (0x80028000 + 0x3f0) +#define HWT_DCP_CSCYSCALE HWIO_32_RW +#define HWN_DCP_CSCYSCALE DCP_CSCYSCALE +#define HWI_DCP_CSCYSCALE +#define BP_DCP_CSCYSCALE_RSVD1 26 +#define BM_DCP_CSCYSCALE_RSVD1 0xfc000000 +#define BF_DCP_CSCYSCALE_RSVD1(v) (((v) & 0x3f) << 26) +#define BFM_DCP_CSCYSCALE_RSVD1(v) BM_DCP_CSCYSCALE_RSVD1 +#define BF_DCP_CSCYSCALE_RSVD1_V(e) BF_DCP_CSCYSCALE_RSVD1(BV_DCP_CSCYSCALE_RSVD1__##e) +#define BFM_DCP_CSCYSCALE_RSVD1_V(v) BM_DCP_CSCYSCALE_RSVD1 +#define BP_DCP_CSCYSCALE_INT 24 +#define BM_DCP_CSCYSCALE_INT 0x3000000 +#define BF_DCP_CSCYSCALE_INT(v) (((v) & 0x3) << 24) +#define BFM_DCP_CSCYSCALE_INT(v) BM_DCP_CSCYSCALE_INT +#define BF_DCP_CSCYSCALE_INT_V(e) BF_DCP_CSCYSCALE_INT(BV_DCP_CSCYSCALE_INT__##e) +#define BFM_DCP_CSCYSCALE_INT_V(v) BM_DCP_CSCYSCALE_INT +#define BP_DCP_CSCYSCALE_FRAC 12 +#define BM_DCP_CSCYSCALE_FRAC 0xfff000 +#define BF_DCP_CSCYSCALE_FRAC(v) (((v) & 0xfff) << 12) +#define BFM_DCP_CSCYSCALE_FRAC(v) BM_DCP_CSCYSCALE_FRAC +#define BF_DCP_CSCYSCALE_FRAC_V(e) BF_DCP_CSCYSCALE_FRAC(BV_DCP_CSCYSCALE_FRAC__##e) +#define BFM_DCP_CSCYSCALE_FRAC_V(v) BM_DCP_CSCYSCALE_FRAC +#define BP_DCP_CSCYSCALE_HEIGHT 0 +#define BM_DCP_CSCYSCALE_HEIGHT 0xfff +#define BF_DCP_CSCYSCALE_HEIGHT(v) (((v) & 0xfff) << 0) +#define BFM_DCP_CSCYSCALE_HEIGHT(v) BM_DCP_CSCYSCALE_HEIGHT +#define BF_DCP_CSCYSCALE_HEIGHT_V(e) BF_DCP_CSCYSCALE_HEIGHT(BV_DCP_CSCYSCALE_HEIGHT__##e) +#define BFM_DCP_CSCYSCALE_HEIGHT_V(v) BM_DCP_CSCYSCALE_HEIGHT + +#define HW_DCP_DBGSELECT HW(DCP_DBGSELECT) +#define HWA_DCP_DBGSELECT (0x80028000 + 0x400) +#define HWT_DCP_DBGSELECT HWIO_32_RW +#define HWN_DCP_DBGSELECT DCP_DBGSELECT +#define HWI_DCP_DBGSELECT +#define BP_DCP_DBGSELECT_RSVD 8 +#define BM_DCP_DBGSELECT_RSVD 0xffffff00 +#define BF_DCP_DBGSELECT_RSVD(v) (((v) & 0xffffff) << 8) +#define BFM_DCP_DBGSELECT_RSVD(v) BM_DCP_DBGSELECT_RSVD +#define BF_DCP_DBGSELECT_RSVD_V(e) BF_DCP_DBGSELECT_RSVD(BV_DCP_DBGSELECT_RSVD__##e) +#define BFM_DCP_DBGSELECT_RSVD_V(v) BM_DCP_DBGSELECT_RSVD +#define BP_DCP_DBGSELECT_INDEX 0 +#define BM_DCP_DBGSELECT_INDEX 0xff +#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x1 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13 +#define BF_DCP_DBGSELECT_INDEX(v) (((v) & 0xff) << 0) +#define BFM_DCP_DBGSELECT_INDEX(v) BM_DCP_DBGSELECT_INDEX +#define BF_DCP_DBGSELECT_INDEX_V(e) BF_DCP_DBGSELECT_INDEX(BV_DCP_DBGSELECT_INDEX__##e) +#define BFM_DCP_DBGSELECT_INDEX_V(v) BM_DCP_DBGSELECT_INDEX + +#define HW_DCP_DBGDATA HW(DCP_DBGDATA) +#define HWA_DCP_DBGDATA (0x80028000 + 0x410) +#define HWT_DCP_DBGDATA HWIO_32_RW +#define HWN_DCP_DBGDATA DCP_DBGDATA +#define HWI_DCP_DBGDATA +#define BP_DCP_DBGDATA_DATA 0 +#define BM_DCP_DBGDATA_DATA 0xffffffff +#define BF_DCP_DBGDATA_DATA(v) (((v) & 0xffffffff) << 0) +#define BFM_DCP_DBGDATA_DATA(v) BM_DCP_DBGDATA_DATA +#define BF_DCP_DBGDATA_DATA_V(e) BF_DCP_DBGDATA_DATA(BV_DCP_DBGDATA_DATA__##e) +#define BFM_DCP_DBGDATA_DATA_V(v) BM_DCP_DBGDATA_DATA + +#define HW_DCP_PAGETABLE HW(DCP_PAGETABLE) +#define HWA_DCP_PAGETABLE (0x80028000 + 0x420) +#define HWT_DCP_PAGETABLE HWIO_32_RW +#define HWN_DCP_PAGETABLE DCP_PAGETABLE +#define HWI_DCP_PAGETABLE +#define BP_DCP_PAGETABLE_BASE 2 +#define BM_DCP_PAGETABLE_BASE 0xfffffffc +#define BF_DCP_PAGETABLE_BASE(v) (((v) & 0x3fffffff) << 2) +#define BFM_DCP_PAGETABLE_BASE(v) BM_DCP_PAGETABLE_BASE +#define BF_DCP_PAGETABLE_BASE_V(e) BF_DCP_PAGETABLE_BASE(BV_DCP_PAGETABLE_BASE__##e) +#define BFM_DCP_PAGETABLE_BASE_V(v) BM_DCP_PAGETABLE_BASE +#define BP_DCP_PAGETABLE_FLUSH 1 +#define BM_DCP_PAGETABLE_FLUSH 0x2 +#define BF_DCP_PAGETABLE_FLUSH(v) (((v) & 0x1) << 1) +#define BFM_DCP_PAGETABLE_FLUSH(v) BM_DCP_PAGETABLE_FLUSH +#define BF_DCP_PAGETABLE_FLUSH_V(e) BF_DCP_PAGETABLE_FLUSH(BV_DCP_PAGETABLE_FLUSH__##e) +#define BFM_DCP_PAGETABLE_FLUSH_V(v) BM_DCP_PAGETABLE_FLUSH +#define BP_DCP_PAGETABLE_ENABLE 0 +#define BM_DCP_PAGETABLE_ENABLE 0x1 +#define BF_DCP_PAGETABLE_ENABLE(v) (((v) & 0x1) << 0) +#define BFM_DCP_PAGETABLE_ENABLE(v) BM_DCP_PAGETABLE_ENABLE +#define BF_DCP_PAGETABLE_ENABLE_V(e) BF_DCP_PAGETABLE_ENABLE(BV_DCP_PAGETABLE_ENABLE__##e) +#define BFM_DCP_PAGETABLE_ENABLE_V(v) BM_DCP_PAGETABLE_ENABLE + +#define HW_DCP_VERSION HW(DCP_VERSION) +#define HWA_DCP_VERSION (0x80028000 + 0x430) +#define HWT_DCP_VERSION HWIO_32_RW +#define HWN_DCP_VERSION DCP_VERSION +#define HWI_DCP_VERSION +#define BP_DCP_VERSION_MAJOR 24 +#define BM_DCP_VERSION_MAJOR 0xff000000 +#define BF_DCP_VERSION_MAJOR(v) (((v) & 0xff) << 24) +#define BFM_DCP_VERSION_MAJOR(v) BM_DCP_VERSION_MAJOR +#define BF_DCP_VERSION_MAJOR_V(e) BF_DCP_VERSION_MAJOR(BV_DCP_VERSION_MAJOR__##e) +#define BFM_DCP_VERSION_MAJOR_V(v) BM_DCP_VERSION_MAJOR +#define BP_DCP_VERSION_MINOR 16 +#define BM_DCP_VERSION_MINOR 0xff0000 +#define BF_DCP_VERSION_MINOR(v) (((v) & 0xff) << 16) +#define BFM_DCP_VERSION_MINOR(v) BM_DCP_VERSION_MINOR +#define BF_DCP_VERSION_MINOR_V(e) BF_DCP_VERSION_MINOR(BV_DCP_VERSION_MINOR__##e) +#define BFM_DCP_VERSION_MINOR_V(v) BM_DCP_VERSION_MINOR +#define BP_DCP_VERSION_STEP 0 +#define BM_DCP_VERSION_STEP 0xffff +#define BF_DCP_VERSION_STEP(v) (((v) & 0xffff) << 0) +#define BFM_DCP_VERSION_STEP(v) BM_DCP_VERSION_STEP +#define BF_DCP_VERSION_STEP_V(e) BF_DCP_VERSION_STEP(BV_DCP_VERSION_STEP__##e) +#define BFM_DCP_VERSION_STEP_V(v) BM_DCP_VERSION_STEP + +#endif /* __HEADERGEN_IMX233_DCP_H__*/ diff --git a/firmware/target/arm/imx233/regs/imx233/digctl.h b/firmware/target/arm/imx233/regs/imx233/digctl.h new file mode 100644 index 0000000000..d4bd27cf68 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/digctl.h @@ -0,0 +1,1661 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * imx233 version: 2.4.0 + * imx233 authors: Amaury Pouly + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_IMX233_DIGCTL_H__ +#define __HEADERGEN_IMX233_DIGCTL_H__ + +#define HW_DIGCTL_CTRL HW(DIGCTL_CTRL) +#define HWA_DIGCTL_CTRL (0x8001c000 + 0x0) +#define HWT_DIGCTL_CTRL HWIO_32_RW +#define HWN_DIGCTL_CTRL DIGCTL_CTRL +#define HWI_DIGCTL_CTRL +#define HW_DIGCTL_CTRL_SET HW(DIGCTL_CTRL_SET) +#define HWA_DIGCTL_CTRL_SET (HWA_DIGCTL_CTRL + 0x4) +#define HWT_DIGCTL_CTRL_SET HWIO_32_WO +#define HWN_DIGCTL_CTRL_SET DIGCTL_CTRL +#define HWI_DIGCTL_CTRL_SET +#define HW_DIGCTL_CTRL_CLR HW(DIGCTL_CTRL_CLR) +#define HWA_DIGCTL_CTRL_CLR (HWA_DIGCTL_CTRL + 0x8) +#define HWT_DIGCTL_CTRL_CLR HWIO_32_WO +#define HWN_DIGCTL_CTRL_CLR DIGCTL_CTRL +#define HWI_DIGCTL_CTRL_CLR +#define HW_DIGCTL_CTRL_TOG HW(DIGCTL_CTRL_TOG) +#define HWA_DIGCTL_CTRL_TOG (HWA_DIGCTL_CTRL + 0xc) +#define HWT_DIGCTL_CTRL_TOG HWIO_32_WO +#define HWN_DIGCTL_CTRL_TOG DIGCTL_CTRL +#define HWI_DIGCTL_CTRL_TOG +#define BP_DIGCTL_CTRL_RSVD3 31 +#define BM_DIGCTL_CTRL_RSVD3 0x80000000 +#define BF_DIGCTL_CTRL_RSVD3(v) (((v) & 0x1) << 31) +#define BFM_DIGCTL_CTRL_RSVD3(v) BM_DIGCTL_CTRL_RSVD3 +#define BF_DIGCTL_CTRL_RSVD3_V(e) BF_DIGCTL_CTRL_RSVD3(BV_DIGCTL_CTRL_RSVD3__##e) +#define BFM_DIGCTL_CTRL_RSVD3_V(v) BM_DIGCTL_CTRL_RSVD3 +#define BP_DIGCTL_CTRL_XTAL24M_GATE 30 +#define BM_DIGCTL_CTRL_XTAL24M_GATE 0x40000000 +#define BF_DIGCTL_CTRL_XTAL24M_GATE(v) (((v) & 0x1) << 30) +#define BFM_DIGCTL_CTRL_XTAL24M_GATE(v) BM_DIGCTL_CTRL_XTAL24M_GATE +#define BF_DIGCTL_CTRL_XTAL24M_GATE_V(e) BF_DIGCTL_CTRL_XTAL24M_GATE(BV_DIGCTL_CTRL_XTAL24M_GATE__##e) +#define BFM_DIGCTL_CTRL_XTAL24M_GATE_V(v) BM_DIGCTL_CTRL_XTAL24M_GATE +#define BP_DIGCTL_CTRL_TRAP_IRQ 29 +#define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000 +#define BF_DIGCTL_CTRL_TRAP_IRQ(v) (((v) & 0x1) << 29) +#define BFM_DIGCTL_CTRL_TRAP_IRQ(v) BM_DIGCTL_CTRL_TRAP_IRQ +#define BF_DIGCTL_CTRL_TRAP_IRQ_V(e) BF_DIGCTL_CTRL_TRAP_IRQ(BV_DIGCTL_CTRL_TRAP_IRQ__##e) +#define BFM_DIGCTL_CTRL_TRAP_IRQ_V(v) BM_DIGCTL_CTRL_TRAP_IRQ +#define BP_DIGCTL_CTRL_RSVD2 27 +#define BM_DIGCTL_CTRL_RSVD2 0x18000000 +#define BF_DIGCTL_CTRL_RSVD2(v) (((v) & 0x3) << 27) +#define BFM_DIGCTL_CTRL_RSVD2(v) BM_DIGCTL_CTRL_RSVD2 +#define BF_DIGCTL_CTRL_RSVD2_V(e) BF_DIGCTL_CTRL_RSVD2(BV_DIGCTL_CTRL_RSVD2__##e) +#define BFM_DIGCTL_CTRL_RSVD2_V(v) BM_DIGCTL_CTRL_RSVD2 +#define BP_DIGCTL_CTRL_CACHE_BIST_TMODE 26 +#define BM_DIGCTL_CTRL_CACHE_BIST_TMODE 0x4000000 +#define BF_DIGCTL_CTRL_CACHE_BIST_TMODE(v) (((v) & 0x1) << 26) +#define BFM_DIGCTL_CTRL_CACHE_BIST_TMODE(v) BM_DIGCTL_CTRL_CACHE_BIST_TMODE +#define BF_DIGCTL_CTRL_CACHE_BIST_TMODE_V(e) BF_DIGCTL_CTRL_CACHE_BIST_TMODE(BV_DIGCTL_CTRL_CACHE_BIST_TMODE__##e) +#define BFM_DIGCTL_CTRL_CACHE_BIST_TMODE_V(v) BM_DIGCTL_CTRL_CACHE_BIST_TMODE +#define BP_DIGCTL_CTRL_LCD_BIST_CLKEN 25 +#define BM_DIGCTL_CTRL_LCD_BIST_CLKEN 0x2000000 +#define BF_DIGCTL_CTRL_LCD_BIST_CLKEN(v) (((v) & 0x1) << 25) +#define BFM_DIGCTL_CTRL_LCD_BIST_CLKEN(v) BM_DIGCTL_CTRL_LCD_BIST_CLKEN +#define BF_DIGCTL_CTRL_LCD_BIST_CLKEN_V(e) BF_DIGCTL_CTRL_LCD_BIST_CLKEN(BV_DIGCTL_CTRL_LCD_BIST_CLKEN__##e) +#define BFM_DIGCTL_CTRL_LCD_BIST_CLKEN_V(v) BM_DIGCTL_CTRL_LCD_BIST_CLKEN +#define BP_DIGCTL_CTRL_LCD_BIST_START 24 +#define BM_DIGCTL_CTRL_LCD_BIST_START 0x1000000 +#define BF_DIGCTL_CTRL_LCD_BIST_START(v) (((v) & 0x1) << 24) +#define BFM_DIGCTL_CTRL_LCD_BIST_START(v) BM_DIGCTL_CTRL_LCD_BIST_START +#define BF_DIGCTL_CTRL_LCD_BIST_START_V(e) BF_DIGCTL_CTRL_LCD_BIST_START(BV_DIGCTL_CTRL_LCD_BIST_START__##e) +#define BFM_DIGCTL_CTRL_LCD_BIST_START_V(v) BM_DIGCTL_CTRL_LCD_BIST_START +#define BP_DIGCTL_CTRL_DCP_BIST_CLKEN 23 +#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x800000 +#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN(v) (((v) & 0x1) << 23) +#define BFM_DIGCTL_CTRL_DCP_BIST_CLKEN(v) BM_DIGCTL_CTRL_DCP_BIST_CLKEN +#define BF_DIGCTL_CTRL_DCP_BIST_CLKEN_V(e) BF_DIGCTL_CTRL_DCP_BIST_CLKEN(BV_DIGCTL_CTRL_DCP_BIST_CLKEN__##e) +#define BFM_DIGCTL_CTRL_DCP_BIST_CLKEN_V(v) BM_DIGCTL_CTRL_DCP_BIST_CLKEN +#define BP_DIGCTL_CTRL_DCP_BIST_START 22 +#define BM_DIGCTL_CTRL_DCP_BIST_START 0x400000 +#define BF_DIGCTL_CTRL_DCP_BIST_START(v) (((v) & 0x1) << 22) +#define BFM_DIGCTL_CTRL_DCP_BIST_START(v) BM_DIGCTL_CTRL_DCP_BIST_START +#define BF_DIGCTL_CTRL_DCP_BIST_START_V(e) BF_DIGCTL_CTRL_DCP_BIST_START(BV_DIGCTL_CTRL_DCP_BIST_START__##e) +#define BFM_DIGCTL_CTRL_DCP_BIST_START_V(v) BM_DIGCTL_CTRL_DCP_BIST_START +#define BP_DIGCTL_CTRL_ARM_BIST_CLKEN 21 +#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x200000 +#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN(v) (((v) & 0x1) << 21) +#define BFM_DIGCTL_CTRL_ARM_BIST_CLKEN(v) BM_DIGCTL_CTRL_ARM_BIST_CLKEN +#define BF_DIGCTL_CTRL_ARM_BIST_CLKEN_V(e) BF_DIGCTL_CTRL_ARM_BIST_CLKEN(BV_DIGCTL_CTRL_ARM_BIST_CLKEN__##e) +#define BFM_DIGCTL_CTRL_ARM_BIST_CLKEN_V(v) BM_DIGCTL_CTRL_ARM_BIST_CLKEN +#define BP_DIGCTL_CTRL_USB_TESTMODE 20 +#define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 +#define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) & 0x1) << 20) +#define BFM_DIGCTL_CTRL_USB_TESTMODE(v) BM_DIGCTL_CTRL_USB_TESTMODE +#define BF_DIGCTL_CTRL_USB_TESTMODE_V(e) BF_DIGCTL_CTRL_USB_TESTMODE(BV_DIGCTL_CTRL_USB_TESTMODE__##e) +#define BFM_DIGCTL_CTRL_USB_TESTMODE_V(v) BM_DIGCTL_CTRL_USB_TESTMODE +#define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 +#define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 +#define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) & 0x1) << 19) +#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE(v) BM_DIGCTL_CTRL_ANALOG_TESTMODE +#define BF_DIGCTL_CTRL_ANALOG_TESTMODE_V(e) BF_DIGCTL_CTRL_ANALOG_TESTMODE(BV_DIGCTL_CTRL_ANALOG_TESTMODE__##e) +#define BFM_DIGCTL_CTRL_ANALOG_TESTMODE_V(v) BM_DIGCTL_CTRL_ANALOG_TESTMODE +#define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 +#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 +#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) & 0x1) << 18) +#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE(v) BM_DIGCTL_CTRL_DIGITAL_TESTMODE +#define BF_DIGCTL_CTRL_DIGITAL_TESTMODE_V(e) BF_DIGCTL_CTRL_DIGITAL_TESTMODE(BV_DIGCTL_CTRL_DIGITAL_TESTMODE__##e) +#define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE_V(v) BM_DIGCTL_CTRL_DIGITAL_TESTMODE +#define BP_DIGCTL_CTRL_ARM_BIST_START 17 +#define BM_DIGCTL_CTRL_ARM_BIST_START 0x20000 +#define BF_DIGCTL_CTRL_ARM_BIST_START(v) (((v) & 0x1) << 17) +#define BFM_DIGCTL_CTRL_ARM_BIST_START(v) BM_DIGCTL_CTRL_ARM_BIST_START +#define BF_DIGCTL_CTRL_ARM_BIST_START_V(e) BF_DIGCTL_CTRL_ARM_BIST_START(BV_DIGCTL_CTRL_ARM_BIST_START__##e) +#define BFM_DIGCTL_CTRL_ARM_BIST_START_V(v) BM_DIGCTL_CTRL_ARM_BIST_START +#define BP_DIGCTL_CTRL_UART_LOOPBACK 16 +#define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 +#define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) & 0x1) << 16) +#define BFM_DIGCTL_CTRL_UART_LOOPBACK(v) BM_DIGCTL_CTRL_UART_LOOPBACK +#define BF_DIGCTL_CTRL_UART_LOOPBACK_V(e) BF_DIGCTL_CTRL_UART_LOOPBACK(BV_DIGCTL_CTRL_UART_LOOPBACK__##e) +#define BFM_DIGCTL_CTRL_UART_LOOPBACK_V(v) BM_DIGCTL_CTRL_UART_LOOPBACK +#define BP_DIGCTL_CTRL_SAIF_LOOPBACK 15 +#define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x8000 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 +#define BF_DIGCTL_CTRL_SAIF_LOOPBACK(v) (((v) & 0x1) << 15) +#define BFM_DIGCTL_CTRL_SAIF_LOOPBACK(v) BM_DIGCTL_CTRL_SAIF_LOOPBACK +#define BF_DIGCTL_CTRL_SAIF_LOOPBACK_V(e) BF_DIGCTL_CTRL_SAIF_LOOPBACK(BV_DIGCTL_CTRL_SAIF_LOOPBACK__##e) +#define BFM_DIGCTL_CTRL_SAIF_LOOPBACK_V(v) BM_DIGCTL_CTRL_SAIF_LOOPBACK +#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13 +#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x6000 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3 +#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) (((v) & 0x3) << 13) +#define BFM_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL +#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(e) BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__##e) +#define BFM_DIGCTL_CTRL_SAIF_CLKMUX_SEL_V(v) BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL +#define BP_DIGCTL_CTRL_SAIF_CLKMST_SEL 12 +#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x1000 +#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1 +#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(v) (((v) & 0x1) << 12) +#define BFM_DIGCTL_CTRL_SAIF_CLKMST_SEL(v) BM_DIGCTL_CTRL_SAIF_CLKMST_SEL +#define BF_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(e) BF_DIGCTL_CTRL_SAIF_CLKMST_SEL(BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__##e) +#define BFM_DIGCTL_CTRL_SAIF_CLKMST_SEL_V(v) BM_DIGCTL_CTRL_SAIF_CLKMST_SEL +#define BP_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 11 +#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x800 +#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v) (((v) & 0x1) << 11) +#define BFM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(v) BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL +#define BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL_V(e) BF_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL(BV_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL__##e) +#define BFM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL_V(v) BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL +#define BP_DIGCTL_CTRL_RSVD1 10 +#define BM_DIGCTL_CTRL_RSVD1 0x400 +#define BF_DIGCTL_CTRL_RSVD1(v) (((v) & 0x1) << 10) +#define BFM_DIGCTL_CTRL_RSVD1(v) BM_DIGCTL_CTRL_RSVD1 +#define BF_DIGCTL_CTRL_RSVD1_V(e) BF_DIGCTL_CTRL_RSVD1(BV_DIGCTL_CTRL_RSVD1__##e) +#define BFM_DIGCTL_CTRL_RSVD1_V(v) BM_DIGCTL_CTRL_RSVD1 +#define BP_DIGCTL_CTRL_SY_ENDIAN 9 +#define BM_DIGCTL_CTRL_SY_ENDIAN 0x200 +#define BF_DIGCTL_CTRL_SY_ENDIAN(v) (((v) & 0x1) << 9) +#define BFM_DIGCTL_CTRL_SY_ENDIAN(v) BM_DIGCTL_CTRL_SY_ENDIAN +#define BF_DIGCTL_CTRL_SY_ENDIAN_V(e) BF_DIGCTL_CTRL_SY_ENDIAN(BV_DIGCTL_CTRL_SY_ENDIAN__##e) +#define BFM_DIGCTL_CTRL_SY_ENDIAN_V(v) BM_DIGCTL_CTRL_SY_ENDIAN +#define BP_DIGCTL_CTRL_SY_SFTRST 8 +#define BM_DIGCTL_CTRL_SY_SFTRST 0x100 +#define BF_DIGCTL_CTRL_SY_SFTRST(v) (((v) & 0x1) << 8) +#define BFM_DIGCTL_CTRL_SY_SFTRST(v) BM_DIGCTL_CTRL_SY_SFTRST +#define BF_DIGCTL_CTRL_SY_SFTRST_V(e) BF_DIGCTL_CTRL_SY_SFTRST(BV_DIGCTL_CTRL_SY_SFTRST__##e) +#define BFM_DIGCTL_CTRL_SY_SFTRST_V(v) BM_DIGCTL_CTRL_SY_SFTRST +#define BP_DIGCTL_CTRL_SY_CLKGATE 7 +#define BM_DIGCTL_CTRL_SY_CLKGATE 0x80 +#define BF_DIGCTL_CTRL_SY_CLKGATE(v) (((v) & 0x1) << 7) +#define BFM_DIGCTL_CTRL_SY_CLKGATE(v) BM_DIGCTL_CTRL_SY_CLKGATE +#define BF_DIGCTL_CTRL_SY_CLKGATE_V(e) BF_DIGCTL_CTRL_SY_CLKGATE(BV_DIGCTL_CTRL_SY_CLKGATE__##e) +#define BFM_DIGCTL_CTRL_SY_CLKGATE_V(v) BM_DIGCTL_CTRL_SY_CLKGATE +#define BP_DIGCTL_CTRL_USE_SERIAL_JTAG 6 +#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x40 +#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0 +#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1 +#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG(v) (((v) & 0x1) << 6) +#define BFM_DIGCTL_CTRL_USE_SERIAL_JTAG(v) BM_DIGCTL_CTRL_USE_SERIAL_JTAG +#define BF_DIGCTL_CTRL_USE_SERIAL_JTAG_V(e) BF_DIGCTL_CTRL_USE_SERIAL_JTAG(BV_DIGCTL_CTRL_USE_SERIAL_JTAG__##e) +#define BFM_DIGCTL_CTRL_USE_SERIAL_JTAG_V(v) BM_DIGCTL_CTRL_USE_SERIAL_JTAG +#define BP_DIGCTL_CTRL_TRAP_IN_RANGE 5 +#define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x20 +#define BF_DIGCTL_CTRL_TRAP_IN_RANGE(v) (((v) & 0x1) << 5) +#define BFM_DIGCTL_CTRL_TRAP_IN_RANGE(v) BM_DIGCTL_CTRL_TRAP_IN_RANGE +#define BF_DIGCTL_CTRL_TRAP_IN_RANGE_V(e) BF_DIGCTL_CTRL_TRAP_IN_RANGE(BV_DIGCTL_CTRL_TRAP_IN_RANGE__##e) +#define BFM_DIGCTL_CTRL_TRAP_IN_RANGE_V(v) BM_DIGCTL_CTRL_TRAP_IN_RANGE +#define BP_DIGCTL_CTRL_TRAP_ENABLE 4 +#define BM_DIGCTL_CTRL_TRAP_ENABLE 0x10 +#define BF_DIGCTL_CTRL_TRAP_ENABLE(v) (((v) & 0x1) << 4) +#define BFM_DIGCTL_CTRL_TRAP_ENABLE(v) BM_DIGCTL_CTRL_TRAP_ENABLE +#define BF_DIGCTL_CTRL_TRAP_ENABLE_V(e) BF_DIGCTL_CTRL_TRAP_ENABLE(BV_DIGCTL_CTRL_TRAP_ENABLE__##e) +#define BFM_DIGCTL_CTRL_TRAP_ENABLE_V(v) BM_DIGCTL_CTRL_TRAP_ENABLE +#define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 +#define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 +#define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) & 0x1) << 3) +#define BFM_DIGCTL_CTRL_DEBUG_DISABLE(v) BM_DIGCTL_CTRL_DEBUG_DISABLE +#define BF_DIGCTL_CTRL_DEBUG_DISABLE_V(e) BF_DIGCTL_CTRL_DEBUG_DISABLE(BV_DIGCTL_CTRL_DEBUG_DISABLE__##e) +#define BFM_DIGCTL_CTRL_DEBUG_DISABLE_V(v) BM_DIGCTL_CTRL_DEBUG_DISABLE +#define BP_DIGCTL_CTRL_USB_CLKGATE 2 +#define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 +#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 +#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 +#define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) & 0x1) << 2) +#define BFM_DIGCTL_CTRL_USB_CLKGATE(v) BM_DIGCTL_CTRL_USB_CLKGATE +#define BF_DIGCTL_CTRL_USB_CLKGATE_V(e) BF_DIGCTL_CTRL_USB_CLKGATE(BV_DIGCTL_CTRL_USB_CLKGATE__##e) +#define BFM_DIGCTL_CTRL_USB_CLKGATE_V(v) BM_DIGCTL_CTRL_USB_CLKGATE +#define BP_DIGCTL_CTRL_JTAG_SHIELD 1 +#define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 +#define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) & 0x1) << 1) +#define BFM_DIGCTL_CTRL_JTAG_SHIELD(v) BM_DIGCTL_CTRL_JTAG_SHIELD +#define BF_DIGCTL_CTRL_JTAG_SHIELD_V(e) BF_DIGCTL_CTRL_JTAG_SHIELD(BV_DIGCTL_CTRL_JTAG_SHIELD__##e) +#define BFM_DIGCTL_CTRL_JTAG_SHIELD_V(v) BM_DIGCTL_CTRL_JTAG_SHIELD +#define BP_DIGCTL_CTRL_LATCH_ENTROPY 0 +#define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x1 +#define BF_DIGCTL_CTRL_LATCH_ENTROPY(v) (((v) & 0x1) << 0) +#define BFM_DIGCTL_CTRL_LATCH_ENTROPY(v) BM_DIGCTL_CTRL_LATCH_ENTROPY +#define BF_DIGCTL_CTRL_LATCH_ENTROPY_V(e) BF_DIGCTL_CTRL_LATCH_ENTROPY(BV_DIGCTL_CTRL_LATCH_ENTROPY__##e) +#define BFM_DIGCTL_CTRL_LATCH_ENTROPY_V(v) BM_DIGCTL_CTRL_LATCH_ENTROPY + +#define HW_DIGCTL_STATUS HW(DIGCTL_STATUS) +#define HWA_DIGCTL_STATUS (0x8001c000 + 0x10) +#define HWT_DIGCTL_STATUS HWIO_32_RW +#define HWN_DIGCTL_STATUS DIGCTL_STATUS +#define HWI_DIGCTL_STATUS +#define HW_DIGCTL_STATUS_SET HW(DIGCTL_STATUS_SET) +#define HWA_DIGCTL_STATUS_SET (HWA_DIGCTL_STATUS + 0x4) +#define HWT_DIGCTL_STATUS_SET HWIO_32_WO +#define HWN_DIGCTL_STATUS_SET DIGCTL_STATUS +#define HWI_DIGCTL_STATUS_SET +#define HW_DIGCTL_STATUS_CLR HW(DIGCTL_STATUS_CLR) +#define HWA_DIGCTL_STATUS_CLR (HWA_DIGCTL_STATUS + 0x8) +#define HWT_DIGCTL_STATUS_CLR HWIO_32_WO +#define HWN_DIGCTL_STATUS_CLR DIGCTL_STATUS +#define HWI_DIGCTL_STATUS_CLR +#define HW_DIGCTL_STATUS_TOG HW(DIGCTL_STATUS_TOG) +#define HWA_DIGCTL_STATUS_TOG (HWA_DIGCTL_STATUS + 0xc) +#define HWT_DIGCTL_STATUS_TOG HWIO_32_WO +#define HWN_DIGCTL_STATUS_TOG DIGCTL_STATUS +#define HWI_DIGCTL_STATUS_TOG +#define BP_DIGCTL_STATUS_USB_HS_PRESENT 31 +#define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000 +#define BF_DIGCTL_STATUS_USB_HS_PRESENT(v) (((v) & 0x1) << 31) +#define BFM_DIGCTL_STATUS_USB_HS_PRESENT(v) BM_DIGCTL_STATUS_USB_HS_PRESENT +#define BF_DIGCTL_STATUS_USB_HS_PRESENT_V(e) BF_DIGCTL_STATUS_USB_HS_PRESENT(BV_DIGCTL_STATUS_USB_HS_PRESENT__##e) +#define BFM_DIGCTL_STATUS_USB_HS_PRESENT_V(v) BM_DIGCTL_STATUS_USB_HS_PRESENT +#define BP_DIGCTL_STATUS_USB_OTG_PRESENT 30 +#define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000 +#define BF_DIGCTL_STATUS_USB_OTG_PRESENT(v) (((v) & 0x1) << 30) +#define BFM_DIGCTL_STATUS_USB_OTG_PRESENT(v) BM_DIGCTL_STATUS_USB_OTG_PRESENT +#define BF_DIGCTL_STATUS_USB_OTG_PRESENT_V(e) BF_DIGCTL_STATUS_USB_OTG_PRESENT(BV_DIGCTL_STATUS_USB_OTG_PRESENT__##e) +#define BFM_DIGCTL_STATUS_USB_OTG_PRESENT_V(v) BM_DIGCTL_STATUS_USB_OTG_PRESENT +#define BP_DIGCTL_STATUS_USB_HOST_PRESENT 29 +#define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000 +#define BF_DIGCTL_STATUS_USB_HOST_PRESENT(v) (((v) & 0x1) << 29) +#define BFM_DIGCTL_STATUS_USB_HOST_PRESENT(v) BM_DIGCTL_STATUS_USB_HOST_PRESENT +#define BF_DIGCTL_STATUS_USB_HOST_PRESENT_V(e) BF_DIGCTL_STATUS_USB_HOST_PRESENT(BV_DIGCTL_STATUS_USB_HOST_PRESENT__##e) +#define BFM_DIGCTL_STATUS_USB_HOST_PRESENT_V(v) BM_DIGCTL_STATUS_USB_HOST_PRESENT +#define BP_DIGCTL_STATUS_USB_DEVICE_PRESENT 28 +#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000 +#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(v) (((v) & 0x1) << 28) +#define BFM_DIGCTL_STATUS_USB_DEVICE_PRESENT(v) BM_DIGCTL_STATUS_USB_DEVICE_PRESENT +#define BF_DIGCTL_STATUS_USB_DEVICE_PRESENT_V(e) BF_DIGCTL_STATUS_USB_DEVICE_PRESENT(BV_DIGCTL_STATUS_USB_DEVICE_PRESENT__##e) +#define BFM_DIGCTL_STATUS_USB_DEVICE_PRESENT_V(v) BM_DIGCTL_STATUS_USB_DEVICE_PRESENT +#define BP_DIGCTL_STATUS_RSVD2 11 +#define BM_DIGCTL_STATUS_RSVD2 0xffff800 +#define BF_DIGCTL_STATUS_RSVD2(v) (((v) & 0x1ffff) << 11) +#define BFM_DIGCTL_STATUS_RSVD2(v) BM_DIGCTL_STATUS_RSVD2 +#define BF_DIGCTL_STATUS_RSVD2_V(e) BF_DIGCTL_STATUS_RSVD2(BV_DIGCTL_STATUS_RSVD2__##e) +#define BFM_DIGCTL_STATUS_RSVD2_V(v) BM_DIGCTL_STATUS_RSVD2 +#define BP_DIGCTL_STATUS_DCP_BIST_FAIL 10 +#define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x400 +#define BF_DIGCTL_STATUS_DCP_BIST_FAIL(v) (((v) & 0x1) << 10) +#define BFM_DIGCTL_STATUS_DCP_BIST_FAIL(v) BM_DIGCTL_STATUS_DCP_BIST_FAIL +#define BF_DIGCTL_STATUS_DCP_BIST_FAIL_V(e) BF_DIGCTL_STATUS_DCP_BIST_FAIL(BV_DIGCTL_STATUS_DCP_BIST_FAIL__##e) +#define BFM_DIGCTL_STATUS_DCP_BIST_FAIL_V(v) BM_DIGCTL_STATUS_DCP_BIST_FAIL +#define BP_DIGCTL_STATUS_DCP_BIST_PASS 9 +#define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x200 +#define BF_DIGCTL_STATUS_DCP_BIST_PASS(v) (((v) & 0x1) << 9) +#define BFM_DIGCTL_STATUS_DCP_BIST_PASS(v) BM_DIGCTL_STATUS_DCP_BIST_PASS +#define BF_DIGCTL_STATUS_DCP_BIST_PASS_V(e) BF_DIGCTL_STATUS_DCP_BIST_PASS(BV_DIGCTL_STATUS_DCP_BIST_PASS__##e) +#define BFM_DIGCTL_STATUS_DCP_BIST_PASS_V(v) BM_DIGCTL_STATUS_DCP_BIST_PASS +#define BP_DIGCTL_STATUS_DCP_BIST_DONE 8 +#define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x100 +#define BF_DIGCTL_STATUS_DCP_BIST_DONE(v) (((v) & 0x1) << 8) +#define BFM_DIGCTL_STATUS_DCP_BIST_DONE(v) BM_DIGCTL_STATUS_DCP_BIST_DONE +#define BF_DIGCTL_STATUS_DCP_BIST_DONE_V(e) BF_DIGCTL_STATUS_DCP_BIST_DONE(BV_DIGCTL_STATUS_DCP_BIST_DONE__##e) +#define BFM_DIGCTL_STATUS_DCP_BIST_DONE_V(v) BM_DIGCTL_STATUS_DCP_BIST_DONE +#define BP_DIGCTL_STATUS_LCD_BIST_FAIL 7 +#define BM_DIGCTL_STATUS_LCD_BIST_FAIL 0x80 +#define BF_DIGCTL_STATUS_LCD_BIST_FAIL(v) (((v) & 0x1) << 7) +#define BFM_DIGCTL_STATUS_LCD_BIST_FAIL(v) BM_DIGCTL_STATUS_LCD_BIST_FAIL +#define BF_DIGCTL_STATUS_LCD_BIST_FAIL_V(e) BF_DIGCTL_STATUS_LCD_BIST_FAIL(BV_DIGCTL_STATUS_LCD_BIST_FAIL__##e) +#define BFM_DIGCTL_STATUS_LCD_BIST_FAIL_V(v) BM_DIGCTL_STATUS_LCD_BIST_FAIL +#define BP_DIGCTL_STATUS_LCD_BIST_PASS 6 +#define BM_DIGCTL_STATUS_LCD_BIST_PASS 0x40 +#define BF_DIGCTL_STATUS_LCD_BIST_PASS(v) (((v) & 0x1) << 6) +#define BFM_DIGCTL_STATUS_LCD_BIST_PASS(v) BM_DIGCTL_STATUS_LCD_BIST_PASS +#define BF_DIGCTL_STATUS_LCD_BIST_PASS_V(e) BF_DIGCTL_STATUS_LCD_BIST_PASS(BV_DIGCTL_STATUS_LCD_BIST_PASS__##e) +#define BFM_DIGCTL_STATUS_LCD_BIST_PASS_V(v) BM_DIGCTL_STATUS_LCD_BIST_PASS +#define BP_DIGCTL_STATUS_LCD_BIST_DONE 5 +#define BM_DIGCTL_STATUS_LCD_BIST_DONE 0x20 +#define BF_DIGCTL_STATUS_LCD_BIST_DONE(v) (((v) & 0x1) << 5) +#define BFM_DIGCTL_STATUS_LCD_BIST_DONE(v) BM_DIGCTL_STATUS_LCD_BIST_DONE +#define BF_DIGCTL_STATUS_LCD_BIST_DONE_V(e) BF_DIGCTL_STATUS_LCD_BIST_DONE(BV_DIGCTL_STATUS_LCD_BIST_DONE__##e) +#define BFM_DIGCTL_STATUS_LCD_BIST_DONE_V(v) BM_DIGCTL_STATUS_LCD_BIST_DONE +#define BP_DIGCTL_STATUS_JTAG_IN_USE 4 +#define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 +#define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) & 0x1) << 4) +#define BFM_DIGCTL_STATUS_JTAG_IN_USE(v) BM_DIGCTL_STATUS_JTAG_IN_USE +#define BF_DIGCTL_STATUS_JTAG_IN_USE_V(e) BF_DIGCTL_STATUS_JTAG_IN_USE(BV_DIGCTL_STATUS_JTAG_IN_USE__##e) +#define BFM_DIGCTL_STATUS_JTAG_IN_USE_V(v) BM_DIGCTL_STATUS_JTAG_IN_USE +#define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 +#define BM_DIGCTL_STATUS_PACKAGE_TYPE 0xe +#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) & 0x7) << 1) +#define BFM_DIGCTL_STATUS_PACKAGE_TYPE(v) BM_DIGCTL_STATUS_PACKAGE_TYPE +#define BF_DIGCTL_STATUS_PACKAGE_TYPE_V(e) BF_DIGCTL_STATUS_PACKAGE_TYPE(BV_DIGCTL_STATUS_PACKAGE_TYPE__##e) +#define BFM_DIGCTL_STATUS_PACKAGE_TYPE_V(v) BM_DIGCTL_STATUS_PACKAGE_TYPE +#define BP_DIGCTL_STATUS_WRITTEN 0 +#define BM_DIGCTL_STATUS_WRITTEN 0x1 +#define BF_DIGCTL_STATUS_WRITTEN(v) (((v) & 0x1) << 0) +#define BFM_DIGCTL_STATUS_WRITTEN(v) BM_DIGCTL_STATUS_WRITTEN +#define BF_DIGCTL_STATUS_WRITTEN_V(e) BF_DIGCTL_STATUS_WRITTEN(BV_DIGCTL_STATUS_WRITTEN__##e) +#define BFM_DIGCTL_STATUS_WRITTEN_V(v) BM_DIGCTL_STATUS_WRITTEN + +#define HW_DIGCTL_HCLKCOUNT HW(DIGCTL_HCLKCOUNT) +#define HWA_DIGCTL_HCLKCOUNT (0x8001c000 + 0x20) +#define HWT_DIGCTL_HCLKCOUNT HWIO_32_RW +#define HWN_DIGCTL_HCLKCOUNT DIGCTL_HCLKCOUNT +#define HWI_DIGCTL_HCLKCOUNT +#define HW_DIGCTL_HCLKCOUNT_SET HW(DIGCTL_HCLKCOUNT_SET) +#define HWA_DIGCTL_HCLKCOUNT_SET (HWA_DIGCTL_HCLKCOUNT + 0x4) +#define HWT_DIGCTL_HCLKCOUNT_SET HWIO_32_WO +#define HWN_DIGCTL_HCLKCOUNT_SET DIGCTL_HCLKCOUNT +#define HWI_DIGCTL_HCLKCOUNT_SET +#define HW_DIGCTL_HCLKCOUNT_CLR HW(DIGCTL_HCLKCOUNT_CLR) +#define HWA_DIGCTL_HCLKCOUNT_CLR (HWA_DIGCTL_HCLKCOUNT + 0x8) +#define HWT_DIGCTL_HCLKCOUNT_CLR HWIO_32_WO +#define HWN_DIGCTL_HCLKCOUNT_CLR DIGCTL_HCLKCOUNT +#define HWI_DIGCTL_HCLKCOUNT_CLR +#define HW_DIGCTL_HCLKCOUNT_TOG HW(DIGCTL_HCLKCOUNT_TOG) +#define HWA_DIGCTL_HCLKCOUNT_TOG (HWA_DIGCTL_HCLKCOUNT + 0xc) +#define HWT_DIGCTL_HCLKCOUNT_TOG HWIO_32_WO +#define HWN_DIGCTL_HCLKCOUNT_TOG DIGCTL_HCLKCOUNT +#define HWI_DIGCTL_HCLKCOUNT_TOG +#define BP_DIGCTL_HCLKCOUNT_COUNT 0 +#define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff +#define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_HCLKCOUNT_COUNT(v) BM_DIGCTL_HCLKCOUNT_COUNT +#define BF_DIGCTL_HCLKCOUNT_COUNT_V(e) BF_DIGCTL_HCLKCOUNT_COUNT(BV_DIGCTL_HCLKCOUNT_COUNT__##e) +#define BFM_DIGCTL_HCLKCOUNT_COUNT_V(v) BM_DIGCTL_HCLKCOUNT_COUNT + +#define HW_DIGCTL_RAMCTRL HW(DIGCTL_RAMCTRL) +#define HWA_DIGCTL_RAMCTRL (0x8001c000 + 0x30) +#define HWT_DIGCTL_RAMCTRL HWIO_32_RW +#define HWN_DIGCTL_RAMCTRL DIGCTL_RAMCTRL +#define HWI_DIGCTL_RAMCTRL +#define HW_DIGCTL_RAMCTRL_SET HW(DIGCTL_RAMCTRL_SET) +#define HWA_DIGCTL_RAMCTRL_SET (HWA_DIGCTL_RAMCTRL + 0x4) +#define HWT_DIGCTL_RAMCTRL_SET HWIO_32_WO +#define HWN_DIGCTL_RAMCTRL_SET DIGCTL_RAMCTRL +#define HWI_DIGCTL_RAMCTRL_SET +#define HW_DIGCTL_RAMCTRL_CLR HW(DIGCTL_RAMCTRL_CLR) +#define HWA_DIGCTL_RAMCTRL_CLR (HWA_DIGCTL_RAMCTRL + 0x8) +#define HWT_DIGCTL_RAMCTRL_CLR HWIO_32_WO +#define HWN_DIGCTL_RAMCTRL_CLR DIGCTL_RAMCTRL +#define HWI_DIGCTL_RAMCTRL_CLR +#define HW_DIGCTL_RAMCTRL_TOG HW(DIGCTL_RAMCTRL_TOG) +#define HWA_DIGCTL_RAMCTRL_TOG (HWA_DIGCTL_RAMCTRL + 0xc) +#define HWT_DIGCTL_RAMCTRL_TOG HWIO_32_WO +#define HWN_DIGCTL_RAMCTRL_TOG DIGCTL_RAMCTRL +#define HWI_DIGCTL_RAMCTRL_TOG +#define BP_DIGCTL_RAMCTRL_RSVD1 12 +#define BM_DIGCTL_RAMCTRL_RSVD1 0xfffff000 +#define BF_DIGCTL_RAMCTRL_RSVD1(v) (((v) & 0xfffff) << 12) +#define BFM_DIGCTL_RAMCTRL_RSVD1(v) BM_DIGCTL_RAMCTRL_RSVD1 +#define BF_DIGCTL_RAMCTRL_RSVD1_V(e) BF_DIGCTL_RAMCTRL_RSVD1(BV_DIGCTL_RAMCTRL_RSVD1__##e) +#define BFM_DIGCTL_RAMCTRL_RSVD1_V(v) BM_DIGCTL_RAMCTRL_RSVD1 +#define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8 +#define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0xf00 +#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) (((v) & 0xf) << 8) +#define BFM_DIGCTL_RAMCTRL_SPEED_SELECT(v) BM_DIGCTL_RAMCTRL_SPEED_SELECT +#define BF_DIGCTL_RAMCTRL_SPEED_SELECT_V(e) BF_DIGCTL_RAMCTRL_SPEED_SELECT(BV_DIGCTL_RAMCTRL_SPEED_SELECT__##e) +#define BFM_DIGCTL_RAMCTRL_SPEED_SELECT_V(v) BM_DIGCTL_RAMCTRL_SPEED_SELECT +#define BP_DIGCTL_RAMCTRL_RSVD0 1 +#define BM_DIGCTL_RAMCTRL_RSVD0 0xfe +#define BF_DIGCTL_RAMCTRL_RSVD0(v) (((v) & 0x7f) << 1) +#define BFM_DIGCTL_RAMCTRL_RSVD0(v) BM_DIGCTL_RAMCTRL_RSVD0 +#define BF_DIGCTL_RAMCTRL_RSVD0_V(e) BF_DIGCTL_RAMCTRL_RSVD0(BV_DIGCTL_RAMCTRL_RSVD0__##e) +#define BFM_DIGCTL_RAMCTRL_RSVD0_V(v) BM_DIGCTL_RAMCTRL_RSVD0 +#define BP_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0 +#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x1 +#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v) (((v) & 0x1) << 0) +#define BFM_DIGCTL_RAMCTRL_RAM_REPAIR_EN(v) BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN +#define BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN_V(e) BF_DIGCTL_RAMCTRL_RAM_REPAIR_EN(BV_DIGCTL_RAMCTRL_RAM_REPAIR_EN__##e) +#define BFM_DIGCTL_RAMCTRL_RAM_REPAIR_EN_V(v) BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN + +#define HW_DIGCTL_RAMREPAIR HW(DIGCTL_RAMREPAIR) +#define HWA_DIGCTL_RAMREPAIR (0x8001c000 + 0x40) +#define HWT_DIGCTL_RAMREPAIR HWIO_32_RW +#define HWN_DIGCTL_RAMREPAIR DIGCTL_RAMREPAIR +#define HWI_DIGCTL_RAMREPAIR +#define HW_DIGCTL_RAMREPAIR_SET HW(DIGCTL_RAMREPAIR_SET) +#define HWA_DIGCTL_RAMREPAIR_SET (HWA_DIGCTL_RAMREPAIR + 0x4) +#define HWT_DIGCTL_RAMREPAIR_SET HWIO_32_WO +#define HWN_DIGCTL_RAMREPAIR_SET DIGCTL_RAMREPAIR +#define HWI_DIGCTL_RAMREPAIR_SET +#define HW_DIGCTL_RAMREPAIR_CLR HW(DIGCTL_RAMREPAIR_CLR) +#define HWA_DIGCTL_RAMREPAIR_CLR (HWA_DIGCTL_RAMREPAIR + 0x8) +#define HWT_DIGCTL_RAMREPAIR_CLR HWIO_32_WO +#define HWN_DIGCTL_RAMREPAIR_CLR DIGCTL_RAMREPAIR +#define HWI_DIGCTL_RAMREPAIR_CLR +#define HW_DIGCTL_RAMREPAIR_TOG HW(DIGCTL_RAMREPAIR_TOG) +#define HWA_DIGCTL_RAMREPAIR_TOG (HWA_DIGCTL_RAMREPAIR + 0xc) +#define HWT_DIGCTL_RAMREPAIR_TOG HWIO_32_WO +#define HWN_DIGCTL_RAMREPAIR_TOG DIGCTL_RAMREPAIR +#define HWI_DIGCTL_RAMREPAIR_TOG +#define BP_DIGCTL_RAMREPAIR_RSVD1 16 +#define BM_DIGCTL_RAMREPAIR_RSVD1 0xffff0000 +#define BF_DIGCTL_RAMREPAIR_RSVD1(v) (((v) & 0xffff) << 16) +#define BFM_DIGCTL_RAMREPAIR_RSVD1(v) BM_DIGCTL_RAMREPAIR_RSVD1 +#define BF_DIGCTL_RAMREPAIR_RSVD1_V(e) BF_DIGCTL_RAMREPAIR_RSVD1(BV_DIGCTL_RAMREPAIR_RSVD1__##e) +#define BFM_DIGCTL_RAMREPAIR_RSVD1_V(v) BM_DIGCTL_RAMREPAIR_RSVD1 +#define BP_DIGCTL_RAMREPAIR_ADDR 0 +#define BM_DIGCTL_RAMREPAIR_ADDR 0xffff +#define BF_DIGCTL_RAMREPAIR_ADDR(v) (((v) & 0xffff) << 0) +#define BFM_DIGCTL_RAMREPAIR_ADDR(v) BM_DIGCTL_RAMREPAIR_ADDR +#define BF_DIGCTL_RAMREPAIR_ADDR_V(e) BF_DIGCTL_RAMREPAIR_ADDR(BV_DIGCTL_RAMREPAIR_ADDR__##e) +#define BFM_DIGCTL_RAMREPAIR_ADDR_V(v) BM_DIGCTL_RAMREPAIR_ADDR + +#define HW_DIGCTL_ROMCTRL HW(DIGCTL_ROMCTRL) +#define HWA_DIGCTL_ROMCTRL (0x8001c000 + 0x50) +#define HWT_DIGCTL_ROMCTRL HWIO_32_RW +#define HWN_DIGCTL_ROMCTRL DIGCTL_ROMCTRL +#define HWI_DIGCTL_ROMCTRL +#define HW_DIGCTL_ROMCTRL_SET HW(DIGCTL_ROMCTRL_SET) +#define HWA_DIGCTL_ROMCTRL_SET (HWA_DIGCTL_ROMCTRL + 0x4) +#define HWT_DIGCTL_ROMCTRL_SET HWIO_32_WO +#define HWN_DIGCTL_ROMCTRL_SET DIGCTL_ROMCTRL +#define HWI_DIGCTL_ROMCTRL_SET +#define HW_DIGCTL_ROMCTRL_CLR HW(DIGCTL_ROMCTRL_CLR) +#define HWA_DIGCTL_ROMCTRL_CLR (HWA_DIGCTL_ROMCTRL + 0x8) +#define HWT_DIGCTL_ROMCTRL_CLR HWIO_32_WO +#define HWN_DIGCTL_ROMCTRL_CLR DIGCTL_ROMCTRL +#define HWI_DIGCTL_ROMCTRL_CLR +#define HW_DIGCTL_ROMCTRL_TOG HW(DIGCTL_ROMCTRL_TOG) +#define HWA_DIGCTL_ROMCTRL_TOG (HWA_DIGCTL_ROMCTRL + 0xc) +#define HWT_DIGCTL_ROMCTRL_TOG HWIO_32_WO +#define HWN_DIGCTL_ROMCTRL_TOG DIGCTL_ROMCTRL +#define HWI_DIGCTL_ROMCTRL_TOG +#define BP_DIGCTL_ROMCTRL_RSVD0 4 +#define BM_DIGCTL_ROMCTRL_RSVD0 0xfffffff0 +#define BF_DIGCTL_ROMCTRL_RSVD0(v) (((v) & 0xfffffff) << 4) +#define BFM_DIGCTL_ROMCTRL_RSVD0(v) BM_DIGCTL_ROMCTRL_RSVD0 +#define BF_DIGCTL_ROMCTRL_RSVD0_V(e) BF_DIGCTL_ROMCTRL_RSVD0(BV_DIGCTL_ROMCTRL_RSVD0__##e) +#define BFM_DIGCTL_ROMCTRL_RSVD0_V(v) BM_DIGCTL_ROMCTRL_RSVD0 +#define BP_DIGCTL_ROMCTRL_RD_MARGIN 0 +#define BM_DIGCTL_ROMCTRL_RD_MARGIN 0xf +#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) (((v) & 0xf) << 0) +#define BFM_DIGCTL_ROMCTRL_RD_MARGIN(v) BM_DIGCTL_ROMCTRL_RD_MARGIN +#define BF_DIGCTL_ROMCTRL_RD_MARGIN_V(e) BF_DIGCTL_ROMCTRL_RD_MARGIN(BV_DIGCTL_ROMCTRL_RD_MARGIN__##e) +#define BFM_DIGCTL_ROMCTRL_RD_MARGIN_V(v) BM_DIGCTL_ROMCTRL_RD_MARGIN + +#define HW_DIGCTL_WRITEONCE HW(DIGCTL_WRITEONCE) +#define HWA_DIGCTL_WRITEONCE (0x8001c000 + 0x60) +#define HWT_DIGCTL_WRITEONCE HWIO_32_RW +#define HWN_DIGCTL_WRITEONCE DIGCTL_WRITEONCE +#define HWI_DIGCTL_WRITEONCE +#define BP_DIGCTL_WRITEONCE_BITS 0 +#define BM_DIGCTL_WRITEONCE_BITS 0xffffffff +#define BF_DIGCTL_WRITEONCE_BITS(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_WRITEONCE_BITS(v) BM_DIGCTL_WRITEONCE_BITS +#define BF_DIGCTL_WRITEONCE_BITS_V(e) BF_DIGCTL_WRITEONCE_BITS(BV_DIGCTL_WRITEONCE_BITS__##e) +#define BFM_DIGCTL_WRITEONCE_BITS_V(v) BM_DIGCTL_WRITEONCE_BITS + +#define HW_DIGCTL_ENTROPY HW(DIGCTL_ENTROPY) +#define HWA_DIGCTL_ENTROPY (0x8001c000 + 0x90) +#define HWT_DIGCTL_ENTROPY HWIO_32_RW +#define HWN_DIGCTL_ENTROPY DIGCTL_ENTROPY +#define HWI_DIGCTL_ENTROPY +#define BP_DIGCTL_ENTROPY_VALUE 0 +#define BM_DIGCTL_ENTROPY_VALUE 0xffffffff +#define BF_DIGCTL_ENTROPY_VALUE(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_ENTROPY_VALUE(v) BM_DIGCTL_ENTROPY_VALUE +#define BF_DIGCTL_ENTROPY_VALUE_V(e) BF_DIGCTL_ENTROPY_VALUE(BV_DIGCTL_ENTROPY_VALUE__##e) +#define BFM_DIGCTL_ENTROPY_VALUE_V(v) BM_DIGCTL_ENTROPY_VALUE + +#define HW_DIGCTL_ENTROPY_LATCHED HW(DIGCTL_ENTROPY_LATCHED) +#define HWA_DIGCTL_ENTROPY_LATCHED (0x8001c000 + 0xa0) +#define HWT_DIGCTL_ENTROPY_LATCHED HWIO_32_RW +#define HWN_DIGCTL_ENTROPY_LATCHED DIGCTL_ENTROPY_LATCHED +#define HWI_DIGCTL_ENTROPY_LATCHED +#define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 +#define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xffffffff +#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_ENTROPY_LATCHED_VALUE(v) BM_DIGCTL_ENTROPY_LATCHED_VALUE +#define BF_DIGCTL_ENTROPY_LATCHED_VALUE_V(e) BF_DIGCTL_ENTROPY_LATCHED_VALUE(BV_DIGCTL_ENTROPY_LATCHED_VALUE__##e) +#define BFM_DIGCTL_ENTROPY_LATCHED_VALUE_V(v) BM_DIGCTL_ENTROPY_LATCHED_VALUE + +#define HW_DIGCTL_SJTAGDBG HW(DIGCTL_SJTAGDBG) +#define HWA_DIGCTL_SJTAGDBG (0x8001c000 + 0xb0) +#define HWT_DIGCTL_SJTAGDBG HWIO_32_RW +#define HWN_DIGCTL_SJTAGDBG DIGCTL_SJTAGDBG +#define HWI_DIGCTL_SJTAGDBG +#define HW_DIGCTL_SJTAGDBG_SET HW(DIGCTL_SJTAGDBG_SET) +#define HWA_DIGCTL_SJTAGDBG_SET (HWA_DIGCTL_SJTAGDBG + 0x4) +#define HWT_DIGCTL_SJTAGDBG_SET HWIO_32_WO +#define HWN_DIGCTL_SJTAGDBG_SET DIGCTL_SJTAGDBG +#define HWI_DIGCTL_SJTAGDBG_SET +#define HW_DIGCTL_SJTAGDBG_CLR HW(DIGCTL_SJTAGDBG_CLR) +#define HWA_DIGCTL_SJTAGDBG_CLR (HWA_DIGCTL_SJTAGDBG + 0x8) +#define HWT_DIGCTL_SJTAGDBG_CLR HWIO_32_WO +#define HWN_DIGCTL_SJTAGDBG_CLR DIGCTL_SJTAGDBG +#define HWI_DIGCTL_SJTAGDBG_CLR +#define HW_DIGCTL_SJTAGDBG_TOG HW(DIGCTL_SJTAGDBG_TOG) +#define HWA_DIGCTL_SJTAGDBG_TOG (HWA_DIGCTL_SJTAGDBG + 0xc) +#define HWT_DIGCTL_SJTAGDBG_TOG HWIO_32_WO +#define HWN_DIGCTL_SJTAGDBG_TOG DIGCTL_SJTAGDBG +#define HWI_DIGCTL_SJTAGDBG_TOG +#define BP_DIGCTL_SJTAGDBG_RSVD2 27 +#define BM_DIGCTL_SJTAGDBG_RSVD2 0xf8000000 +#define BF_DIGCTL_SJTAGDBG_RSVD2(v) (((v) & 0x1f) << 27) +#define BFM_DIGCTL_SJTAGDBG_RSVD2(v) BM_DIGCTL_SJTAGDBG_RSVD2 +#define BF_DIGCTL_SJTAGDBG_RSVD2_V(e) BF_DIGCTL_SJTAGDBG_RSVD2(BV_DIGCTL_SJTAGDBG_RSVD2__##e) +#define BFM_DIGCTL_SJTAGDBG_RSVD2_V(v) BM_DIGCTL_SJTAGDBG_RSVD2 +#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16 +#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x7ff0000 +#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) (((v) & 0x7ff) << 16) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_STATE(v) BM_DIGCTL_SJTAGDBG_SJTAG_STATE +#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_STATE(BV_DIGCTL_SJTAGDBG_SJTAG_STATE__##e) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_STATE_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_STATE +#define BP_DIGCTL_SJTAGDBG_RSVD1 11 +#define BM_DIGCTL_SJTAGDBG_RSVD1 0xf800 +#define BF_DIGCTL_SJTAGDBG_RSVD1(v) (((v) & 0x1f) << 11) +#define BFM_DIGCTL_SJTAGDBG_RSVD1(v) BM_DIGCTL_SJTAGDBG_RSVD1 +#define BF_DIGCTL_SJTAGDBG_RSVD1_V(e) BF_DIGCTL_SJTAGDBG_RSVD1(BV_DIGCTL_SJTAGDBG_RSVD1__##e) +#define BFM_DIGCTL_SJTAGDBG_RSVD1_V(v) BM_DIGCTL_SJTAGDBG_RSVD1 +#define BP_DIGCTL_SJTAGDBG_SJTAG_TDO 10 +#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x400 +#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO(v) (((v) & 0x1) << 10) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDO(v) BM_DIGCTL_SJTAGDBG_SJTAG_TDO +#define BF_DIGCTL_SJTAGDBG_SJTAG_TDO_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_TDO(BV_DIGCTL_SJTAGDBG_SJTAG_TDO__##e) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDO_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_TDO +#define BP_DIGCTL_SJTAGDBG_SJTAG_TDI 9 +#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x200 +#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI(v) (((v) & 0x1) << 9) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDI(v) BM_DIGCTL_SJTAGDBG_SJTAG_TDI +#define BF_DIGCTL_SJTAGDBG_SJTAG_TDI_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_TDI(BV_DIGCTL_SJTAGDBG_SJTAG_TDI__##e) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_TDI_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_TDI +#define BP_DIGCTL_SJTAGDBG_SJTAG_MODE 8 +#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x100 +#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE(v) (((v) & 0x1) << 8) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_MODE(v) BM_DIGCTL_SJTAGDBG_SJTAG_MODE +#define BF_DIGCTL_SJTAGDBG_SJTAG_MODE_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_MODE(BV_DIGCTL_SJTAGDBG_SJTAG_MODE__##e) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_MODE_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_MODE +#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4 +#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0xf0 +#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) (((v) & 0xf) << 4) +#define BFM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE +#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE_V(e) BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(BV_DIGCTL_SJTAGDBG_DELAYED_ACTIVE__##e) +#define BFM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE_V(v) BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE +#define BP_DIGCTL_SJTAGDBG_ACTIVE 3 +#define BM_DIGCTL_SJTAGDBG_ACTIVE 0x8 +#define BF_DIGCTL_SJTAGDBG_ACTIVE(v) (((v) & 0x1) << 3) +#define BFM_DIGCTL_SJTAGDBG_ACTIVE(v) BM_DIGCTL_SJTAGDBG_ACTIVE +#define BF_DIGCTL_SJTAGDBG_ACTIVE_V(e) BF_DIGCTL_SJTAGDBG_ACTIVE(BV_DIGCTL_SJTAGDBG_ACTIVE__##e) +#define BFM_DIGCTL_SJTAGDBG_ACTIVE_V(v) BM_DIGCTL_SJTAGDBG_ACTIVE +#define BP_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 2 +#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x4 +#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v) (((v) & 0x1) << 2) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(v) BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE +#define BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE(BV_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE__##e) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE +#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 1 +#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x2 +#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v) (((v) & 0x1) << 1) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(v) BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA +#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA(BV_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA__##e) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA +#define BP_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0 +#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x1 +#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v) (((v) & 0x1) << 0) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(v) BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE +#define BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE_V(e) BF_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE(BV_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE__##e) +#define BFM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE_V(v) BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE + +#define HW_DIGCTL_MICROSECONDS HW(DIGCTL_MICROSECONDS) +#define HWA_DIGCTL_MICROSECONDS (0x8001c000 + 0xc0) +#define HWT_DIGCTL_MICROSECONDS HWIO_32_RW +#define HWN_DIGCTL_MICROSECONDS DIGCTL_MICROSECONDS +#define HWI_DIGCTL_MICROSECONDS +#define HW_DIGCTL_MICROSECONDS_SET HW(DIGCTL_MICROSECONDS_SET) +#define HWA_DIGCTL_MICROSECONDS_SET (HWA_DIGCTL_MICROSECONDS + 0x4) +#define HWT_DIGCTL_MICROSECONDS_SET HWIO_32_WO +#define HWN_DIGCTL_MICROSECONDS_SET DIGCTL_MICROSECONDS +#define HWI_DIGCTL_MICROSECONDS_SET +#define HW_DIGCTL_MICROSECONDS_CLR HW(DIGCTL_MICROSECONDS_CLR) +#define HWA_DIGCTL_MICROSECONDS_CLR (HWA_DIGCTL_MICROSECONDS + 0x8) +#define HWT_DIGCTL_MICROSECONDS_CLR HWIO_32_WO +#define HWN_DIGCTL_MICROSECONDS_CLR DIGCTL_MICROSECONDS +#define HWI_DIGCTL_MICROSECONDS_CLR +#define HW_DIGCTL_MICROSECONDS_TOG HW(DIGCTL_MICROSECONDS_TOG) +#define HWA_DIGCTL_MICROSECONDS_TOG (HWA_DIGCTL_MICROSECONDS + 0xc) +#define HWT_DIGCTL_MICROSECONDS_TOG HWIO_32_WO +#define HWN_DIGCTL_MICROSECONDS_TOG DIGCTL_MICROSECONDS +#define HWI_DIGCTL_MICROSECONDS_TOG +#define BP_DIGCTL_MICROSECONDS_VALUE 0 +#define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff +#define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_MICROSECONDS_VALUE(v) BM_DIGCTL_MICROSECONDS_VALUE +#define BF_DIGCTL_MICROSECONDS_VALUE_V(e) BF_DIGCTL_MICROSECONDS_VALUE(BV_DIGCTL_MICROSECONDS_VALUE__##e) +#define BFM_DIGCTL_MICROSECONDS_VALUE_V(v) BM_DIGCTL_MICROSECONDS_VALUE + +#define HW_DIGCTL_DBGRD HW(DIGCTL_DBGRD) +#define HWA_DIGCTL_DBGRD (0x8001c000 + 0xd0) +#define HWT_DIGCTL_DBGRD HWIO_32_RW +#define HWN_DIGCTL_DBGRD DIGCTL_DBGRD +#define HWI_DIGCTL_DBGRD +#define BP_DIGCTL_DBGRD_COMPLEMENT 0 +#define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff +#define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_DBGRD_COMPLEMENT(v) BM_DIGCTL_DBGRD_COMPLEMENT +#define BF_DIGCTL_DBGRD_COMPLEMENT_V(e) BF_DIGCTL_DBGRD_COMPLEMENT(BV_DIGCTL_DBGRD_COMPLEMENT__##e) +#define BFM_DIGCTL_DBGRD_COMPLEMENT_V(v) BM_DIGCTL_DBGRD_COMPLEMENT + +#define HW_DIGCTL_DBG HW(DIGCTL_DBG) +#define HWA_DIGCTL_DBG (0x8001c000 + 0xe0) +#define HWT_DIGCTL_DBG HWIO_32_RW +#define HWN_DIGCTL_DBG DIGCTL_DBG +#define HWI_DIGCTL_DBG +#define BP_DIGCTL_DBG_VALUE 0 +#define BM_DIGCTL_DBG_VALUE 0xffffffff +#define BF_DIGCTL_DBG_VALUE(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_DBG_VALUE(v) BM_DIGCTL_DBG_VALUE +#define BF_DIGCTL_DBG_VALUE_V(e) BF_DIGCTL_DBG_VALUE(BV_DIGCTL_DBG_VALUE__##e) +#define BFM_DIGCTL_DBG_VALUE_V(v) BM_DIGCTL_DBG_VALUE + +#define HW_DIGCTL_OCRAM_BIST_CSR HW(DIGCTL_OCRAM_BIST_CSR) +#define HWA_DIGCTL_OCRAM_BIST_CSR (0x8001c000 + 0xf0) +#define HWT_DIGCTL_OCRAM_BIST_CSR HWIO_32_RW +#define HWN_DIGCTL_OCRAM_BIST_CSR DIGCTL_OCRAM_BIST_CSR +#define HWI_DIGCTL_OCRAM_BIST_CSR +#define HW_DIGCTL_OCRAM_BIST_CSR_SET HW(DIGCTL_OCRAM_BIST_CSR_SET) +#define HWA_DIGCTL_OCRAM_BIST_CSR_SET (HWA_DIGCTL_OCRAM_BIST_CSR + 0x4) +#define HWT_DIGCTL_OCRAM_BIST_CSR_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_BIST_CSR_SET DIGCTL_OCRAM_BIST_CSR +#define HWI_DIGCTL_OCRAM_BIST_CSR_SET +#define HW_DIGCTL_OCRAM_BIST_CSR_CLR HW(DIGCTL_OCRAM_BIST_CSR_CLR) +#define HWA_DIGCTL_OCRAM_BIST_CSR_CLR (HWA_DIGCTL_OCRAM_BIST_CSR + 0x8) +#define HWT_DIGCTL_OCRAM_BIST_CSR_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_BIST_CSR_CLR DIGCTL_OCRAM_BIST_CSR +#define HWI_DIGCTL_OCRAM_BIST_CSR_CLR +#define HW_DIGCTL_OCRAM_BIST_CSR_TOG HW(DIGCTL_OCRAM_BIST_CSR_TOG) +#define HWA_DIGCTL_OCRAM_BIST_CSR_TOG (HWA_DIGCTL_OCRAM_BIST_CSR + 0xc) +#define HWT_DIGCTL_OCRAM_BIST_CSR_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_BIST_CSR_TOG DIGCTL_OCRAM_BIST_CSR +#define HWI_DIGCTL_OCRAM_BIST_CSR_TOG +#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1 11 +#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1 0xfffff800 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v) (((v) & 0x1fffff) << 11) +#define BFM_DIGCTL_OCRAM_BIST_CSR_RSVD1(v) BM_DIGCTL_OCRAM_BIST_CSR_RSVD1 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1_V(e) BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(BV_DIGCTL_OCRAM_BIST_CSR_RSVD1__##e) +#define BFM_DIGCTL_OCRAM_BIST_CSR_RSVD1_V(v) BM_DIGCTL_OCRAM_BIST_CSR_RSVD1 +#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE 10 +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE 0x400 +#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE(v) (((v) & 0x1) << 10) +#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE +#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE_V(e) BF_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE(BV_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE__##e) +#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE_V(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE +#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 9 +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x200 +#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v) (((v) & 0x1) << 9) +#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE +#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE_V(e) BF_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE(BV_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE__##e) +#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE_V(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE +#define BP_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 8 +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x100 +#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v) (((v) & 0x1) << 8) +#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN +#define BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN_V(e) BF_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN(BV_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN__##e) +#define BFM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN_V(v) BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN +#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0 4 +#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0 0xf0 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v) (((v) & 0xf) << 4) +#define BFM_DIGCTL_OCRAM_BIST_CSR_RSVD0(v) BM_DIGCTL_OCRAM_BIST_CSR_RSVD0 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0_V(e) BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(BV_DIGCTL_OCRAM_BIST_CSR_RSVD0__##e) +#define BFM_DIGCTL_OCRAM_BIST_CSR_RSVD0_V(v) BM_DIGCTL_OCRAM_BIST_CSR_RSVD0 +#define BP_DIGCTL_OCRAM_BIST_CSR_FAIL 3 +#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x8 +#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL(v) (((v) & 0x1) << 3) +#define BFM_DIGCTL_OCRAM_BIST_CSR_FAIL(v) BM_DIGCTL_OCRAM_BIST_CSR_FAIL +#define BF_DIGCTL_OCRAM_BIST_CSR_FAIL_V(e) BF_DIGCTL_OCRAM_BIST_CSR_FAIL(BV_DIGCTL_OCRAM_BIST_CSR_FAIL__##e) +#define BFM_DIGCTL_OCRAM_BIST_CSR_FAIL_V(v) BM_DIGCTL_OCRAM_BIST_CSR_FAIL +#define BP_DIGCTL_OCRAM_BIST_CSR_PASS 2 +#define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x4 +#define BF_DIGCTL_OCRAM_BIST_CSR_PASS(v) (((v) & 0x1) << 2) +#define BFM_DIGCTL_OCRAM_BIST_CSR_PASS(v) BM_DIGCTL_OCRAM_BIST_CSR_PASS +#define BF_DIGCTL_OCRAM_BIST_CSR_PASS_V(e) BF_DIGCTL_OCRAM_BIST_CSR_PASS(BV_DIGCTL_OCRAM_BIST_CSR_PASS__##e) +#define BFM_DIGCTL_OCRAM_BIST_CSR_PASS_V(v) BM_DIGCTL_OCRAM_BIST_CSR_PASS +#define BP_DIGCTL_OCRAM_BIST_CSR_DONE 1 +#define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x2 +#define BF_DIGCTL_OCRAM_BIST_CSR_DONE(v) (((v) & 0x1) << 1) +#define BFM_DIGCTL_OCRAM_BIST_CSR_DONE(v) BM_DIGCTL_OCRAM_BIST_CSR_DONE +#define BF_DIGCTL_OCRAM_BIST_CSR_DONE_V(e) BF_DIGCTL_OCRAM_BIST_CSR_DONE(BV_DIGCTL_OCRAM_BIST_CSR_DONE__##e) +#define BFM_DIGCTL_OCRAM_BIST_CSR_DONE_V(v) BM_DIGCTL_OCRAM_BIST_CSR_DONE +#define BP_DIGCTL_OCRAM_BIST_CSR_START 0 +#define BM_DIGCTL_OCRAM_BIST_CSR_START 0x1 +#define BF_DIGCTL_OCRAM_BIST_CSR_START(v) (((v) & 0x1) << 0) +#define BFM_DIGCTL_OCRAM_BIST_CSR_START(v) BM_DIGCTL_OCRAM_BIST_CSR_START +#define BF_DIGCTL_OCRAM_BIST_CSR_START_V(e) BF_DIGCTL_OCRAM_BIST_CSR_START(BV_DIGCTL_OCRAM_BIST_CSR_START__##e) +#define BFM_DIGCTL_OCRAM_BIST_CSR_START_V(v) BM_DIGCTL_OCRAM_BIST_CSR_START + +#define HW_DIGCTL_OCRAM_STATUS0 HW(DIGCTL_OCRAM_STATUS0) +#define HWA_DIGCTL_OCRAM_STATUS0 (0x8001c000 + 0x110) +#define HWT_DIGCTL_OCRAM_STATUS0 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS0 DIGCTL_OCRAM_STATUS0 +#define HWI_DIGCTL_OCRAM_STATUS0 +#define HW_DIGCTL_OCRAM_STATUS0_SET HW(DIGCTL_OCRAM_STATUS0_SET) +#define HWA_DIGCTL_OCRAM_STATUS0_SET (HWA_DIGCTL_OCRAM_STATUS0 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS0_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS0_SET DIGCTL_OCRAM_STATUS0 +#define HWI_DIGCTL_OCRAM_STATUS0_SET +#define HW_DIGCTL_OCRAM_STATUS0_CLR HW(DIGCTL_OCRAM_STATUS0_CLR) +#define HWA_DIGCTL_OCRAM_STATUS0_CLR (HWA_DIGCTL_OCRAM_STATUS0 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS0_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS0_CLR DIGCTL_OCRAM_STATUS0 +#define HWI_DIGCTL_OCRAM_STATUS0_CLR +#define HW_DIGCTL_OCRAM_STATUS0_TOG HW(DIGCTL_OCRAM_STATUS0_TOG) +#define HWA_DIGCTL_OCRAM_STATUS0_TOG (HWA_DIGCTL_OCRAM_STATUS0 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS0_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS0_TOG DIGCTL_OCRAM_STATUS0 +#define HWI_DIGCTL_OCRAM_STATUS0_TOG +#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 +#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xffffffff +#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 +#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00_V(e) BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(BV_DIGCTL_OCRAM_STATUS0_FAILDATA00__##e) +#define BFM_DIGCTL_OCRAM_STATUS0_FAILDATA00_V(v) BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 + +#define HW_DIGCTL_OCRAM_STATUS1 HW(DIGCTL_OCRAM_STATUS1) +#define HWA_DIGCTL_OCRAM_STATUS1 (0x8001c000 + 0x120) +#define HWT_DIGCTL_OCRAM_STATUS1 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS1 DIGCTL_OCRAM_STATUS1 +#define HWI_DIGCTL_OCRAM_STATUS1 +#define HW_DIGCTL_OCRAM_STATUS1_SET HW(DIGCTL_OCRAM_STATUS1_SET) +#define HWA_DIGCTL_OCRAM_STATUS1_SET (HWA_DIGCTL_OCRAM_STATUS1 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS1_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS1_SET DIGCTL_OCRAM_STATUS1 +#define HWI_DIGCTL_OCRAM_STATUS1_SET +#define HW_DIGCTL_OCRAM_STATUS1_CLR HW(DIGCTL_OCRAM_STATUS1_CLR) +#define HWA_DIGCTL_OCRAM_STATUS1_CLR (HWA_DIGCTL_OCRAM_STATUS1 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS1_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS1_CLR DIGCTL_OCRAM_STATUS1 +#define HWI_DIGCTL_OCRAM_STATUS1_CLR +#define HW_DIGCTL_OCRAM_STATUS1_TOG HW(DIGCTL_OCRAM_STATUS1_TOG) +#define HWA_DIGCTL_OCRAM_STATUS1_TOG (HWA_DIGCTL_OCRAM_STATUS1 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS1_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS1_TOG DIGCTL_OCRAM_STATUS1 +#define HWI_DIGCTL_OCRAM_STATUS1_TOG +#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 +#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xffffffff +#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 +#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01_V(e) BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(BV_DIGCTL_OCRAM_STATUS1_FAILDATA01__##e) +#define BFM_DIGCTL_OCRAM_STATUS1_FAILDATA01_V(v) BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 + +#define HW_DIGCTL_OCRAM_STATUS2 HW(DIGCTL_OCRAM_STATUS2) +#define HWA_DIGCTL_OCRAM_STATUS2 (0x8001c000 + 0x130) +#define HWT_DIGCTL_OCRAM_STATUS2 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS2 DIGCTL_OCRAM_STATUS2 +#define HWI_DIGCTL_OCRAM_STATUS2 +#define HW_DIGCTL_OCRAM_STATUS2_SET HW(DIGCTL_OCRAM_STATUS2_SET) +#define HWA_DIGCTL_OCRAM_STATUS2_SET (HWA_DIGCTL_OCRAM_STATUS2 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS2_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS2_SET DIGCTL_OCRAM_STATUS2 +#define HWI_DIGCTL_OCRAM_STATUS2_SET +#define HW_DIGCTL_OCRAM_STATUS2_CLR HW(DIGCTL_OCRAM_STATUS2_CLR) +#define HWA_DIGCTL_OCRAM_STATUS2_CLR (HWA_DIGCTL_OCRAM_STATUS2 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS2_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS2_CLR DIGCTL_OCRAM_STATUS2 +#define HWI_DIGCTL_OCRAM_STATUS2_CLR +#define HW_DIGCTL_OCRAM_STATUS2_TOG HW(DIGCTL_OCRAM_STATUS2_TOG) +#define HWA_DIGCTL_OCRAM_STATUS2_TOG (HWA_DIGCTL_OCRAM_STATUS2 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS2_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS2_TOG DIGCTL_OCRAM_STATUS2 +#define HWI_DIGCTL_OCRAM_STATUS2_TOG +#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 +#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xffffffff +#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 +#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10_V(e) BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(BV_DIGCTL_OCRAM_STATUS2_FAILDATA10__##e) +#define BFM_DIGCTL_OCRAM_STATUS2_FAILDATA10_V(v) BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 + +#define HW_DIGCTL_OCRAM_STATUS3 HW(DIGCTL_OCRAM_STATUS3) +#define HWA_DIGCTL_OCRAM_STATUS3 (0x8001c000 + 0x140) +#define HWT_DIGCTL_OCRAM_STATUS3 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS3 DIGCTL_OCRAM_STATUS3 +#define HWI_DIGCTL_OCRAM_STATUS3 +#define HW_DIGCTL_OCRAM_STATUS3_SET HW(DIGCTL_OCRAM_STATUS3_SET) +#define HWA_DIGCTL_OCRAM_STATUS3_SET (HWA_DIGCTL_OCRAM_STATUS3 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS3_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS3_SET DIGCTL_OCRAM_STATUS3 +#define HWI_DIGCTL_OCRAM_STATUS3_SET +#define HW_DIGCTL_OCRAM_STATUS3_CLR HW(DIGCTL_OCRAM_STATUS3_CLR) +#define HWA_DIGCTL_OCRAM_STATUS3_CLR (HWA_DIGCTL_OCRAM_STATUS3 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS3_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS3_CLR DIGCTL_OCRAM_STATUS3 +#define HWI_DIGCTL_OCRAM_STATUS3_CLR +#define HW_DIGCTL_OCRAM_STATUS3_TOG HW(DIGCTL_OCRAM_STATUS3_TOG) +#define HWA_DIGCTL_OCRAM_STATUS3_TOG (HWA_DIGCTL_OCRAM_STATUS3 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS3_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS3_TOG DIGCTL_OCRAM_STATUS3 +#define HWI_DIGCTL_OCRAM_STATUS3_TOG +#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 +#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xffffffff +#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 +#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11_V(e) BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(BV_DIGCTL_OCRAM_STATUS3_FAILDATA11__##e) +#define BFM_DIGCTL_OCRAM_STATUS3_FAILDATA11_V(v) BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 + +#define HW_DIGCTL_OCRAM_STATUS4 HW(DIGCTL_OCRAM_STATUS4) +#define HWA_DIGCTL_OCRAM_STATUS4 (0x8001c000 + 0x150) +#define HWT_DIGCTL_OCRAM_STATUS4 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS4 DIGCTL_OCRAM_STATUS4 +#define HWI_DIGCTL_OCRAM_STATUS4 +#define HW_DIGCTL_OCRAM_STATUS4_SET HW(DIGCTL_OCRAM_STATUS4_SET) +#define HWA_DIGCTL_OCRAM_STATUS4_SET (HWA_DIGCTL_OCRAM_STATUS4 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS4_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS4_SET DIGCTL_OCRAM_STATUS4 +#define HWI_DIGCTL_OCRAM_STATUS4_SET +#define HW_DIGCTL_OCRAM_STATUS4_CLR HW(DIGCTL_OCRAM_STATUS4_CLR) +#define HWA_DIGCTL_OCRAM_STATUS4_CLR (HWA_DIGCTL_OCRAM_STATUS4 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS4_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS4_CLR DIGCTL_OCRAM_STATUS4 +#define HWI_DIGCTL_OCRAM_STATUS4_CLR +#define HW_DIGCTL_OCRAM_STATUS4_TOG HW(DIGCTL_OCRAM_STATUS4_TOG) +#define HWA_DIGCTL_OCRAM_STATUS4_TOG (HWA_DIGCTL_OCRAM_STATUS4 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS4_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS4_TOG DIGCTL_OCRAM_STATUS4 +#define HWI_DIGCTL_OCRAM_STATUS4_TOG +#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 +#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xffffffff +#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 +#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20_V(e) BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(BV_DIGCTL_OCRAM_STATUS4_FAILDATA20__##e) +#define BFM_DIGCTL_OCRAM_STATUS4_FAILDATA20_V(v) BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 + +#define HW_DIGCTL_OCRAM_STATUS5 HW(DIGCTL_OCRAM_STATUS5) +#define HWA_DIGCTL_OCRAM_STATUS5 (0x8001c000 + 0x160) +#define HWT_DIGCTL_OCRAM_STATUS5 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS5 DIGCTL_OCRAM_STATUS5 +#define HWI_DIGCTL_OCRAM_STATUS5 +#define HW_DIGCTL_OCRAM_STATUS5_SET HW(DIGCTL_OCRAM_STATUS5_SET) +#define HWA_DIGCTL_OCRAM_STATUS5_SET (HWA_DIGCTL_OCRAM_STATUS5 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS5_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS5_SET DIGCTL_OCRAM_STATUS5 +#define HWI_DIGCTL_OCRAM_STATUS5_SET +#define HW_DIGCTL_OCRAM_STATUS5_CLR HW(DIGCTL_OCRAM_STATUS5_CLR) +#define HWA_DIGCTL_OCRAM_STATUS5_CLR (HWA_DIGCTL_OCRAM_STATUS5 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS5_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS5_CLR DIGCTL_OCRAM_STATUS5 +#define HWI_DIGCTL_OCRAM_STATUS5_CLR +#define HW_DIGCTL_OCRAM_STATUS5_TOG HW(DIGCTL_OCRAM_STATUS5_TOG) +#define HWA_DIGCTL_OCRAM_STATUS5_TOG (HWA_DIGCTL_OCRAM_STATUS5 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS5_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS5_TOG DIGCTL_OCRAM_STATUS5 +#define HWI_DIGCTL_OCRAM_STATUS5_TOG +#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 +#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xffffffff +#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 +#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21_V(e) BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(BV_DIGCTL_OCRAM_STATUS5_FAILDATA21__##e) +#define BFM_DIGCTL_OCRAM_STATUS5_FAILDATA21_V(v) BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 + +#define HW_DIGCTL_OCRAM_STATUS6 HW(DIGCTL_OCRAM_STATUS6) +#define HWA_DIGCTL_OCRAM_STATUS6 (0x8001c000 + 0x170) +#define HWT_DIGCTL_OCRAM_STATUS6 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS6 DIGCTL_OCRAM_STATUS6 +#define HWI_DIGCTL_OCRAM_STATUS6 +#define HW_DIGCTL_OCRAM_STATUS6_SET HW(DIGCTL_OCRAM_STATUS6_SET) +#define HWA_DIGCTL_OCRAM_STATUS6_SET (HWA_DIGCTL_OCRAM_STATUS6 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS6_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS6_SET DIGCTL_OCRAM_STATUS6 +#define HWI_DIGCTL_OCRAM_STATUS6_SET +#define HW_DIGCTL_OCRAM_STATUS6_CLR HW(DIGCTL_OCRAM_STATUS6_CLR) +#define HWA_DIGCTL_OCRAM_STATUS6_CLR (HWA_DIGCTL_OCRAM_STATUS6 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS6_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS6_CLR DIGCTL_OCRAM_STATUS6 +#define HWI_DIGCTL_OCRAM_STATUS6_CLR +#define HW_DIGCTL_OCRAM_STATUS6_TOG HW(DIGCTL_OCRAM_STATUS6_TOG) +#define HWA_DIGCTL_OCRAM_STATUS6_TOG (HWA_DIGCTL_OCRAM_STATUS6 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS6_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS6_TOG DIGCTL_OCRAM_STATUS6 +#define HWI_DIGCTL_OCRAM_STATUS6_TOG +#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 +#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xffffffff +#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 +#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30_V(e) BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(BV_DIGCTL_OCRAM_STATUS6_FAILDATA30__##e) +#define BFM_DIGCTL_OCRAM_STATUS6_FAILDATA30_V(v) BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 + +#define HW_DIGCTL_OCRAM_STATUS7 HW(DIGCTL_OCRAM_STATUS7) +#define HWA_DIGCTL_OCRAM_STATUS7 (0x8001c000 + 0x180) +#define HWT_DIGCTL_OCRAM_STATUS7 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS7 DIGCTL_OCRAM_STATUS7 +#define HWI_DIGCTL_OCRAM_STATUS7 +#define HW_DIGCTL_OCRAM_STATUS7_SET HW(DIGCTL_OCRAM_STATUS7_SET) +#define HWA_DIGCTL_OCRAM_STATUS7_SET (HWA_DIGCTL_OCRAM_STATUS7 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS7_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS7_SET DIGCTL_OCRAM_STATUS7 +#define HWI_DIGCTL_OCRAM_STATUS7_SET +#define HW_DIGCTL_OCRAM_STATUS7_CLR HW(DIGCTL_OCRAM_STATUS7_CLR) +#define HWA_DIGCTL_OCRAM_STATUS7_CLR (HWA_DIGCTL_OCRAM_STATUS7 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS7_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS7_CLR DIGCTL_OCRAM_STATUS7 +#define HWI_DIGCTL_OCRAM_STATUS7_CLR +#define HW_DIGCTL_OCRAM_STATUS7_TOG HW(DIGCTL_OCRAM_STATUS7_TOG) +#define HWA_DIGCTL_OCRAM_STATUS7_TOG (HWA_DIGCTL_OCRAM_STATUS7 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS7_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS7_TOG DIGCTL_OCRAM_STATUS7 +#define HWI_DIGCTL_OCRAM_STATUS7_TOG +#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 +#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xffffffff +#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 +#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31_V(e) BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(BV_DIGCTL_OCRAM_STATUS7_FAILDATA31__##e) +#define BFM_DIGCTL_OCRAM_STATUS7_FAILDATA31_V(v) BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 + +#define HW_DIGCTL_OCRAM_STATUS8 HW(DIGCTL_OCRAM_STATUS8) +#define HWA_DIGCTL_OCRAM_STATUS8 (0x8001c000 + 0x190) +#define HWT_DIGCTL_OCRAM_STATUS8 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS8 DIGCTL_OCRAM_STATUS8 +#define HWI_DIGCTL_OCRAM_STATUS8 +#define HW_DIGCTL_OCRAM_STATUS8_SET HW(DIGCTL_OCRAM_STATUS8_SET) +#define HWA_DIGCTL_OCRAM_STATUS8_SET (HWA_DIGCTL_OCRAM_STATUS8 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS8_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS8_SET DIGCTL_OCRAM_STATUS8 +#define HWI_DIGCTL_OCRAM_STATUS8_SET +#define HW_DIGCTL_OCRAM_STATUS8_CLR HW(DIGCTL_OCRAM_STATUS8_CLR) +#define HWA_DIGCTL_OCRAM_STATUS8_CLR (HWA_DIGCTL_OCRAM_STATUS8 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS8_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS8_CLR DIGCTL_OCRAM_STATUS8 +#define HWI_DIGCTL_OCRAM_STATUS8_CLR +#define HW_DIGCTL_OCRAM_STATUS8_TOG HW(DIGCTL_OCRAM_STATUS8_TOG) +#define HWA_DIGCTL_OCRAM_STATUS8_TOG (HWA_DIGCTL_OCRAM_STATUS8 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS8_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS8_TOG DIGCTL_OCRAM_STATUS8 +#define HWI_DIGCTL_OCRAM_STATUS8_TOG +#define BP_DIGCTL_OCRAM_STATUS8_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS8_RSVD3 0xe0000000 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v) (((v) & 0x7) << 29) +#define BFM_DIGCTL_OCRAM_STATUS8_RSVD3(v) BM_DIGCTL_OCRAM_STATUS8_RSVD3 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD3_V(e) BF_DIGCTL_OCRAM_STATUS8_RSVD3(BV_DIGCTL_OCRAM_STATUS8_RSVD3__##e) +#define BFM_DIGCTL_OCRAM_STATUS8_RSVD3_V(v) BM_DIGCTL_OCRAM_STATUS8_RSVD3 +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0x1fff0000 +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) (((v) & 0x1fff) << 16) +#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01_V(e) BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(BV_DIGCTL_OCRAM_STATUS8_FAILADDR01__##e) +#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR01_V(v) BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 +#define BP_DIGCTL_OCRAM_STATUS8_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS8_RSVD2 0xe000 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v) (((v) & 0x7) << 13) +#define BFM_DIGCTL_OCRAM_STATUS8_RSVD2(v) BM_DIGCTL_OCRAM_STATUS8_RSVD2 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD2_V(e) BF_DIGCTL_OCRAM_STATUS8_RSVD2(BV_DIGCTL_OCRAM_STATUS8_RSVD2__##e) +#define BFM_DIGCTL_OCRAM_STATUS8_RSVD2_V(v) BM_DIGCTL_OCRAM_STATUS8_RSVD2 +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0x1fff +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) (((v) & 0x1fff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00_V(e) BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(BV_DIGCTL_OCRAM_STATUS8_FAILADDR00__##e) +#define BFM_DIGCTL_OCRAM_STATUS8_FAILADDR00_V(v) BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 + +#define HW_DIGCTL_OCRAM_STATUS9 HW(DIGCTL_OCRAM_STATUS9) +#define HWA_DIGCTL_OCRAM_STATUS9 (0x8001c000 + 0x1a0) +#define HWT_DIGCTL_OCRAM_STATUS9 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS9 DIGCTL_OCRAM_STATUS9 +#define HWI_DIGCTL_OCRAM_STATUS9 +#define HW_DIGCTL_OCRAM_STATUS9_SET HW(DIGCTL_OCRAM_STATUS9_SET) +#define HWA_DIGCTL_OCRAM_STATUS9_SET (HWA_DIGCTL_OCRAM_STATUS9 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS9_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS9_SET DIGCTL_OCRAM_STATUS9 +#define HWI_DIGCTL_OCRAM_STATUS9_SET +#define HW_DIGCTL_OCRAM_STATUS9_CLR HW(DIGCTL_OCRAM_STATUS9_CLR) +#define HWA_DIGCTL_OCRAM_STATUS9_CLR (HWA_DIGCTL_OCRAM_STATUS9 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS9_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS9_CLR DIGCTL_OCRAM_STATUS9 +#define HWI_DIGCTL_OCRAM_STATUS9_CLR +#define HW_DIGCTL_OCRAM_STATUS9_TOG HW(DIGCTL_OCRAM_STATUS9_TOG) +#define HWA_DIGCTL_OCRAM_STATUS9_TOG (HWA_DIGCTL_OCRAM_STATUS9 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS9_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS9_TOG DIGCTL_OCRAM_STATUS9 +#define HWI_DIGCTL_OCRAM_STATUS9_TOG +#define BP_DIGCTL_OCRAM_STATUS9_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS9_RSVD3 0xe0000000 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v) (((v) & 0x7) << 29) +#define BFM_DIGCTL_OCRAM_STATUS9_RSVD3(v) BM_DIGCTL_OCRAM_STATUS9_RSVD3 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD3_V(e) BF_DIGCTL_OCRAM_STATUS9_RSVD3(BV_DIGCTL_OCRAM_STATUS9_RSVD3__##e) +#define BFM_DIGCTL_OCRAM_STATUS9_RSVD3_V(v) BM_DIGCTL_OCRAM_STATUS9_RSVD3 +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0x1fff0000 +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) (((v) & 0x1fff) << 16) +#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11_V(e) BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(BV_DIGCTL_OCRAM_STATUS9_FAILADDR11__##e) +#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR11_V(v) BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 +#define BP_DIGCTL_OCRAM_STATUS9_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS9_RSVD2 0xe000 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v) (((v) & 0x7) << 13) +#define BFM_DIGCTL_OCRAM_STATUS9_RSVD2(v) BM_DIGCTL_OCRAM_STATUS9_RSVD2 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD2_V(e) BF_DIGCTL_OCRAM_STATUS9_RSVD2(BV_DIGCTL_OCRAM_STATUS9_RSVD2__##e) +#define BFM_DIGCTL_OCRAM_STATUS9_RSVD2_V(v) BM_DIGCTL_OCRAM_STATUS9_RSVD2 +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0x1fff +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) (((v) & 0x1fff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10_V(e) BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(BV_DIGCTL_OCRAM_STATUS9_FAILADDR10__##e) +#define BFM_DIGCTL_OCRAM_STATUS9_FAILADDR10_V(v) BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 + +#define HW_DIGCTL_OCRAM_STATUS10 HW(DIGCTL_OCRAM_STATUS10) +#define HWA_DIGCTL_OCRAM_STATUS10 (0x8001c000 + 0x1b0) +#define HWT_DIGCTL_OCRAM_STATUS10 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS10 DIGCTL_OCRAM_STATUS10 +#define HWI_DIGCTL_OCRAM_STATUS10 +#define HW_DIGCTL_OCRAM_STATUS10_SET HW(DIGCTL_OCRAM_STATUS10_SET) +#define HWA_DIGCTL_OCRAM_STATUS10_SET (HWA_DIGCTL_OCRAM_STATUS10 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS10_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS10_SET DIGCTL_OCRAM_STATUS10 +#define HWI_DIGCTL_OCRAM_STATUS10_SET +#define HW_DIGCTL_OCRAM_STATUS10_CLR HW(DIGCTL_OCRAM_STATUS10_CLR) +#define HWA_DIGCTL_OCRAM_STATUS10_CLR (HWA_DIGCTL_OCRAM_STATUS10 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS10_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS10_CLR DIGCTL_OCRAM_STATUS10 +#define HWI_DIGCTL_OCRAM_STATUS10_CLR +#define HW_DIGCTL_OCRAM_STATUS10_TOG HW(DIGCTL_OCRAM_STATUS10_TOG) +#define HWA_DIGCTL_OCRAM_STATUS10_TOG (HWA_DIGCTL_OCRAM_STATUS10 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS10_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS10_TOG DIGCTL_OCRAM_STATUS10 +#define HWI_DIGCTL_OCRAM_STATUS10_TOG +#define BP_DIGCTL_OCRAM_STATUS10_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS10_RSVD3 0xe0000000 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v) (((v) & 0x7) << 29) +#define BFM_DIGCTL_OCRAM_STATUS10_RSVD3(v) BM_DIGCTL_OCRAM_STATUS10_RSVD3 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD3_V(e) BF_DIGCTL_OCRAM_STATUS10_RSVD3(BV_DIGCTL_OCRAM_STATUS10_RSVD3__##e) +#define BFM_DIGCTL_OCRAM_STATUS10_RSVD3_V(v) BM_DIGCTL_OCRAM_STATUS10_RSVD3 +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0x1fff0000 +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) (((v) & 0x1fff) << 16) +#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21_V(e) BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(BV_DIGCTL_OCRAM_STATUS10_FAILADDR21__##e) +#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR21_V(v) BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 +#define BP_DIGCTL_OCRAM_STATUS10_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS10_RSVD2 0xe000 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v) (((v) & 0x7) << 13) +#define BFM_DIGCTL_OCRAM_STATUS10_RSVD2(v) BM_DIGCTL_OCRAM_STATUS10_RSVD2 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD2_V(e) BF_DIGCTL_OCRAM_STATUS10_RSVD2(BV_DIGCTL_OCRAM_STATUS10_RSVD2__##e) +#define BFM_DIGCTL_OCRAM_STATUS10_RSVD2_V(v) BM_DIGCTL_OCRAM_STATUS10_RSVD2 +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0x1fff +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) (((v) & 0x1fff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20_V(e) BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(BV_DIGCTL_OCRAM_STATUS10_FAILADDR20__##e) +#define BFM_DIGCTL_OCRAM_STATUS10_FAILADDR20_V(v) BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 + +#define HW_DIGCTL_OCRAM_STATUS11 HW(DIGCTL_OCRAM_STATUS11) +#define HWA_DIGCTL_OCRAM_STATUS11 (0x8001c000 + 0x1c0) +#define HWT_DIGCTL_OCRAM_STATUS11 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS11 DIGCTL_OCRAM_STATUS11 +#define HWI_DIGCTL_OCRAM_STATUS11 +#define HW_DIGCTL_OCRAM_STATUS11_SET HW(DIGCTL_OCRAM_STATUS11_SET) +#define HWA_DIGCTL_OCRAM_STATUS11_SET (HWA_DIGCTL_OCRAM_STATUS11 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS11_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS11_SET DIGCTL_OCRAM_STATUS11 +#define HWI_DIGCTL_OCRAM_STATUS11_SET +#define HW_DIGCTL_OCRAM_STATUS11_CLR HW(DIGCTL_OCRAM_STATUS11_CLR) +#define HWA_DIGCTL_OCRAM_STATUS11_CLR (HWA_DIGCTL_OCRAM_STATUS11 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS11_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS11_CLR DIGCTL_OCRAM_STATUS11 +#define HWI_DIGCTL_OCRAM_STATUS11_CLR +#define HW_DIGCTL_OCRAM_STATUS11_TOG HW(DIGCTL_OCRAM_STATUS11_TOG) +#define HWA_DIGCTL_OCRAM_STATUS11_TOG (HWA_DIGCTL_OCRAM_STATUS11 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS11_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS11_TOG DIGCTL_OCRAM_STATUS11 +#define HWI_DIGCTL_OCRAM_STATUS11_TOG +#define BP_DIGCTL_OCRAM_STATUS11_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS11_RSVD3 0xe0000000 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v) (((v) & 0x7) << 29) +#define BFM_DIGCTL_OCRAM_STATUS11_RSVD3(v) BM_DIGCTL_OCRAM_STATUS11_RSVD3 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD3_V(e) BF_DIGCTL_OCRAM_STATUS11_RSVD3(BV_DIGCTL_OCRAM_STATUS11_RSVD3__##e) +#define BFM_DIGCTL_OCRAM_STATUS11_RSVD3_V(v) BM_DIGCTL_OCRAM_STATUS11_RSVD3 +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0x1fff0000 +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) (((v) & 0x1fff) << 16) +#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31_V(e) BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(BV_DIGCTL_OCRAM_STATUS11_FAILADDR31__##e) +#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR31_V(v) BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 +#define BP_DIGCTL_OCRAM_STATUS11_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS11_RSVD2 0xe000 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v) (((v) & 0x7) << 13) +#define BFM_DIGCTL_OCRAM_STATUS11_RSVD2(v) BM_DIGCTL_OCRAM_STATUS11_RSVD2 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD2_V(e) BF_DIGCTL_OCRAM_STATUS11_RSVD2(BV_DIGCTL_OCRAM_STATUS11_RSVD2__##e) +#define BFM_DIGCTL_OCRAM_STATUS11_RSVD2_V(v) BM_DIGCTL_OCRAM_STATUS11_RSVD2 +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0x1fff +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) (((v) & 0x1fff) << 0) +#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30_V(e) BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(BV_DIGCTL_OCRAM_STATUS11_FAILADDR30__##e) +#define BFM_DIGCTL_OCRAM_STATUS11_FAILADDR30_V(v) BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 + +#define HW_DIGCTL_OCRAM_STATUS12 HW(DIGCTL_OCRAM_STATUS12) +#define HWA_DIGCTL_OCRAM_STATUS12 (0x8001c000 + 0x1d0) +#define HWT_DIGCTL_OCRAM_STATUS12 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS12 DIGCTL_OCRAM_STATUS12 +#define HWI_DIGCTL_OCRAM_STATUS12 +#define HW_DIGCTL_OCRAM_STATUS12_SET HW(DIGCTL_OCRAM_STATUS12_SET) +#define HWA_DIGCTL_OCRAM_STATUS12_SET (HWA_DIGCTL_OCRAM_STATUS12 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS12_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS12_SET DIGCTL_OCRAM_STATUS12 +#define HWI_DIGCTL_OCRAM_STATUS12_SET +#define HW_DIGCTL_OCRAM_STATUS12_CLR HW(DIGCTL_OCRAM_STATUS12_CLR) +#define HWA_DIGCTL_OCRAM_STATUS12_CLR (HWA_DIGCTL_OCRAM_STATUS12 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS12_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS12_CLR DIGCTL_OCRAM_STATUS12 +#define HWI_DIGCTL_OCRAM_STATUS12_CLR +#define HW_DIGCTL_OCRAM_STATUS12_TOG HW(DIGCTL_OCRAM_STATUS12_TOG) +#define HWA_DIGCTL_OCRAM_STATUS12_TOG (HWA_DIGCTL_OCRAM_STATUS12 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS12_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS12_TOG DIGCTL_OCRAM_STATUS12 +#define HWI_DIGCTL_OCRAM_STATUS12_TOG +#define BP_DIGCTL_OCRAM_STATUS12_RSVD3 28 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD3 0xf0000000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v) (((v) & 0xf) << 28) +#define BFM_DIGCTL_OCRAM_STATUS12_RSVD3(v) BM_DIGCTL_OCRAM_STATUS12_RSVD3 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD3_V(e) BF_DIGCTL_OCRAM_STATUS12_RSVD3(BV_DIGCTL_OCRAM_STATUS12_RSVD3__##e) +#define BFM_DIGCTL_OCRAM_STATUS12_RSVD3_V(v) BM_DIGCTL_OCRAM_STATUS12_RSVD3 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0xf000000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) (((v) & 0xf) << 24) +#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11_V(e) BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE11__##e) +#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE11_V(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 +#define BP_DIGCTL_OCRAM_STATUS12_RSVD2 20 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD2 0xf00000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v) (((v) & 0xf) << 20) +#define BFM_DIGCTL_OCRAM_STATUS12_RSVD2(v) BM_DIGCTL_OCRAM_STATUS12_RSVD2 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD2_V(e) BF_DIGCTL_OCRAM_STATUS12_RSVD2(BV_DIGCTL_OCRAM_STATUS12_RSVD2__##e) +#define BFM_DIGCTL_OCRAM_STATUS12_RSVD2_V(v) BM_DIGCTL_OCRAM_STATUS12_RSVD2 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0xf0000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) (((v) & 0xf) << 16) +#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10_V(e) BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE10__##e) +#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE10_V(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 +#define BP_DIGCTL_OCRAM_STATUS12_RSVD1 12 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD1 0xf000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v) (((v) & 0xf) << 12) +#define BFM_DIGCTL_OCRAM_STATUS12_RSVD1(v) BM_DIGCTL_OCRAM_STATUS12_RSVD1 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD1_V(e) BF_DIGCTL_OCRAM_STATUS12_RSVD1(BV_DIGCTL_OCRAM_STATUS12_RSVD1__##e) +#define BFM_DIGCTL_OCRAM_STATUS12_RSVD1_V(v) BM_DIGCTL_OCRAM_STATUS12_RSVD1 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0xf00 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) (((v) & 0xf) << 8) +#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01_V(e) BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE01__##e) +#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE01_V(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 +#define BP_DIGCTL_OCRAM_STATUS12_RSVD0 4 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD0 0xf0 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v) (((v) & 0xf) << 4) +#define BFM_DIGCTL_OCRAM_STATUS12_RSVD0(v) BM_DIGCTL_OCRAM_STATUS12_RSVD0 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD0_V(e) BF_DIGCTL_OCRAM_STATUS12_RSVD0(BV_DIGCTL_OCRAM_STATUS12_RSVD0__##e) +#define BFM_DIGCTL_OCRAM_STATUS12_RSVD0_V(v) BM_DIGCTL_OCRAM_STATUS12_RSVD0 +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0xf +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) (((v) & 0xf) << 0) +#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00_V(e) BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(BV_DIGCTL_OCRAM_STATUS12_FAILSTATE00__##e) +#define BFM_DIGCTL_OCRAM_STATUS12_FAILSTATE00_V(v) BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 + +#define HW_DIGCTL_OCRAM_STATUS13 HW(DIGCTL_OCRAM_STATUS13) +#define HWA_DIGCTL_OCRAM_STATUS13 (0x8001c000 + 0x1e0) +#define HWT_DIGCTL_OCRAM_STATUS13 HWIO_32_RW +#define HWN_DIGCTL_OCRAM_STATUS13 DIGCTL_OCRAM_STATUS13 +#define HWI_DIGCTL_OCRAM_STATUS13 +#define HW_DIGCTL_OCRAM_STATUS13_SET HW(DIGCTL_OCRAM_STATUS13_SET) +#define HWA_DIGCTL_OCRAM_STATUS13_SET (HWA_DIGCTL_OCRAM_STATUS13 + 0x4) +#define HWT_DIGCTL_OCRAM_STATUS13_SET HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS13_SET DIGCTL_OCRAM_STATUS13 +#define HWI_DIGCTL_OCRAM_STATUS13_SET +#define HW_DIGCTL_OCRAM_STATUS13_CLR HW(DIGCTL_OCRAM_STATUS13_CLR) +#define HWA_DIGCTL_OCRAM_STATUS13_CLR (HWA_DIGCTL_OCRAM_STATUS13 + 0x8) +#define HWT_DIGCTL_OCRAM_STATUS13_CLR HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS13_CLR DIGCTL_OCRAM_STATUS13 +#define HWI_DIGCTL_OCRAM_STATUS13_CLR +#define HW_DIGCTL_OCRAM_STATUS13_TOG HW(DIGCTL_OCRAM_STATUS13_TOG) +#define HWA_DIGCTL_OCRAM_STATUS13_TOG (HWA_DIGCTL_OCRAM_STATUS13 + 0xc) +#define HWT_DIGCTL_OCRAM_STATUS13_TOG HWIO_32_WO +#define HWN_DIGCTL_OCRAM_STATUS13_TOG DIGCTL_OCRAM_STATUS13 +#define HWI_DIGCTL_OCRAM_STATUS13_TOG +#define BP_DIGCTL_OCRAM_STATUS13_RSVD3 28 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD3 0xf0000000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v) (((v) & 0xf) << 28) +#define BFM_DIGCTL_OCRAM_STATUS13_RSVD3(v) BM_DIGCTL_OCRAM_STATUS13_RSVD3 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD3_V(e) BF_DIGCTL_OCRAM_STATUS13_RSVD3(BV_DIGCTL_OCRAM_STATUS13_RSVD3__##e) +#define BFM_DIGCTL_OCRAM_STATUS13_RSVD3_V(v) BM_DIGCTL_OCRAM_STATUS13_RSVD3 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0xf000000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) (((v) & 0xf) << 24) +#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31_V(e) BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE31__##e) +#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE31_V(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 +#define BP_DIGCTL_OCRAM_STATUS13_RSVD2 20 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD2 0xf00000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v) (((v) & 0xf) << 20) +#define BFM_DIGCTL_OCRAM_STATUS13_RSVD2(v) BM_DIGCTL_OCRAM_STATUS13_RSVD2 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD2_V(e) BF_DIGCTL_OCRAM_STATUS13_RSVD2(BV_DIGCTL_OCRAM_STATUS13_RSVD2__##e) +#define BFM_DIGCTL_OCRAM_STATUS13_RSVD2_V(v) BM_DIGCTL_OCRAM_STATUS13_RSVD2 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0xf0000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) (((v) & 0xf) << 16) +#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30_V(e) BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE30__##e) +#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE30_V(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 +#define BP_DIGCTL_OCRAM_STATUS13_RSVD1 12 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD1 0xf000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v) (((v) & 0xf) << 12) +#define BFM_DIGCTL_OCRAM_STATUS13_RSVD1(v) BM_DIGCTL_OCRAM_STATUS13_RSVD1 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD1_V(e) BF_DIGCTL_OCRAM_STATUS13_RSVD1(BV_DIGCTL_OCRAM_STATUS13_RSVD1__##e) +#define BFM_DIGCTL_OCRAM_STATUS13_RSVD1_V(v) BM_DIGCTL_OCRAM_STATUS13_RSVD1 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0xf00 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) (((v) & 0xf) << 8) +#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21_V(e) BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE21__##e) +#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE21_V(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 +#define BP_DIGCTL_OCRAM_STATUS13_RSVD0 4 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD0 0xf0 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v) (((v) & 0xf) << 4) +#define BFM_DIGCTL_OCRAM_STATUS13_RSVD0(v) BM_DIGCTL_OCRAM_STATUS13_RSVD0 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD0_V(e) BF_DIGCTL_OCRAM_STATUS13_RSVD0(BV_DIGCTL_OCRAM_STATUS13_RSVD0__##e) +#define BFM_DIGCTL_OCRAM_STATUS13_RSVD0_V(v) BM_DIGCTL_OCRAM_STATUS13_RSVD0 +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0xf +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) (((v) & 0xf) << 0) +#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20_V(e) BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(BV_DIGCTL_OCRAM_STATUS13_FAILSTATE20__##e) +#define BFM_DIGCTL_OCRAM_STATUS13_FAILSTATE20_V(v) BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 + +#define HW_DIGCTL_SCRATCH0 HW(DIGCTL_SCRATCH0) +#define HWA_DIGCTL_SCRATCH0 (0x8001c000 + 0x290) +#define HWT_DIGCTL_SCRATCH0 HWIO_32_RW +#define HWN_DIGCTL_SCRATCH0 DIGCTL_SCRATCH0 +#define HWI_DIGCTL_SCRATCH0 +#define BP_DIGCTL_SCRATCH0_PTR 0 +#define BM_DIGCTL_SCRATCH0_PTR 0xffffffff +#define BF_DIGCTL_SCRATCH0_PTR(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_SCRATCH0_PTR(v) BM_DIGCTL_SCRATCH0_PTR +#define BF_DIGCTL_SCRATCH0_PTR_V(e) BF_DIGCTL_SCRATCH0_PTR(BV_DIGCTL_SCRATCH0_PTR__##e) +#define BFM_DIGCTL_SCRATCH0_PTR_V(v) BM_DIGCTL_SCRATCH0_PTR + +#define HW_DIGCTL_SCRATCH1 HW(DIGCTL_SCRATCH1) +#define HWA_DIGCTL_SCRATCH1 (0x8001c000 + 0x2a0) +#define HWT_DIGCTL_SCRATCH1 HWIO_32_RW +#define HWN_DIGCTL_SCRATCH1 DIGCTL_SCRATCH1 +#define HWI_DIGCTL_SCRATCH1 +#define BP_DIGCTL_SCRATCH1_PTR 0 +#define BM_DIGCTL_SCRATCH1_PTR 0xffffffff +#define BF_DIGCTL_SCRATCH1_PTR(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_SCRATCH1_PTR(v) BM_DIGCTL_SCRATCH1_PTR +#define BF_DIGCTL_SCRATCH1_PTR_V(e) BF_DIGCTL_SCRATCH1_PTR(BV_DIGCTL_SCRATCH1_PTR__##e) +#define BFM_DIGCTL_SCRATCH1_PTR_V(v) BM_DIGCTL_SCRATCH1_PTR + +#define HW_DIGCTL_ARMCACHE HW(DIGCTL_ARMCACHE) +#define HWA_DIGCTL_ARMCACHE (0x8001c000 + 0x2b0) +#define HWT_DIGCTL_ARMCACHE HWIO_32_RW +#define HWN_DIGCTL_ARMCACHE DIGCTL_ARMCACHE +#define HWI_DIGCTL_ARMCACHE +#define BP_DIGCTL_ARMCACHE_RSVD4 18 +#define BM_DIGCTL_ARMCACHE_RSVD4 0xfffc0000 +#define BF_DIGCTL_ARMCACHE_RSVD4(v) (((v) & 0x3fff) << 18) +#define BFM_DIGCTL_ARMCACHE_RSVD4(v) BM_DIGCTL_ARMCACHE_RSVD4 +#define BF_DIGCTL_ARMCACHE_RSVD4_V(e) BF_DIGCTL_ARMCACHE_RSVD4(BV_DIGCTL_ARMCACHE_RSVD4__##e) +#define BFM_DIGCTL_ARMCACHE_RSVD4_V(v) BM_DIGCTL_ARMCACHE_RSVD4 +#define BP_DIGCTL_ARMCACHE_VALID_SS 16 +#define BM_DIGCTL_ARMCACHE_VALID_SS 0x30000 +#define BF_DIGCTL_ARMCACHE_VALID_SS(v) (((v) & 0x3) << 16) +#define BFM_DIGCTL_ARMCACHE_VALID_SS(v) BM_DIGCTL_ARMCACHE_VALID_SS +#define BF_DIGCTL_ARMCACHE_VALID_SS_V(e) BF_DIGCTL_ARMCACHE_VALID_SS(BV_DIGCTL_ARMCACHE_VALID_SS__##e) +#define BFM_DIGCTL_ARMCACHE_VALID_SS_V(v) BM_DIGCTL_ARMCACHE_VALID_SS +#define BP_DIGCTL_ARMCACHE_RSVD3 14 +#define BM_DIGCTL_ARMCACHE_RSVD3 0xc000 +#define BF_DIGCTL_ARMCACHE_RSVD3(v) (((v) & 0x3) << 14) +#define BFM_DIGCTL_ARMCACHE_RSVD3(v) BM_DIGCTL_ARMCACHE_RSVD3 +#define BF_DIGCTL_ARMCACHE_RSVD3_V(e) BF_DIGCTL_ARMCACHE_RSVD3(BV_DIGCTL_ARMCACHE_RSVD3__##e) +#define BFM_DIGCTL_ARMCACHE_RSVD3_V(v) BM_DIGCTL_ARMCACHE_RSVD3 +#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 +#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x3000 +#define BF_DIGCTL_ARMCACHE_DRTY_SS(v) (((v) & 0x3) << 12) +#define BFM_DIGCTL_ARMCACHE_DRTY_SS(v) BM_DIGCTL_ARMCACHE_DRTY_SS +#define BF_DIGCTL_ARMCACHE_DRTY_SS_V(e) BF_DIGCTL_ARMCACHE_DRTY_SS(BV_DIGCTL_ARMCACHE_DRTY_SS__##e) +#define BFM_DIGCTL_ARMCACHE_DRTY_SS_V(v) BM_DIGCTL_ARMCACHE_DRTY_SS +#define BP_DIGCTL_ARMCACHE_RSVD2 10 +#define BM_DIGCTL_ARMCACHE_RSVD2 0xc00 +#define BF_DIGCTL_ARMCACHE_RSVD2(v) (((v) & 0x3) << 10) +#define BFM_DIGCTL_ARMCACHE_RSVD2(v) BM_DIGCTL_ARMCACHE_RSVD2 +#define BF_DIGCTL_ARMCACHE_RSVD2_V(e) BF_DIGCTL_ARMCACHE_RSVD2(BV_DIGCTL_ARMCACHE_RSVD2__##e) +#define BFM_DIGCTL_ARMCACHE_RSVD2_V(v) BM_DIGCTL_ARMCACHE_RSVD2 +#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 +#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 +#define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) & 0x3) << 8) +#define BFM_DIGCTL_ARMCACHE_CACHE_SS(v) BM_DIGCTL_ARMCACHE_CACHE_SS +#define BF_DIGCTL_ARMCACHE_CACHE_SS_V(e) BF_DIGCTL_ARMCACHE_CACHE_SS(BV_DIGCTL_ARMCACHE_CACHE_SS__##e) +#define BFM_DIGCTL_ARMCACHE_CACHE_SS_V(v) BM_DIGCTL_ARMCACHE_CACHE_SS +#define BP_DIGCTL_ARMCACHE_RSVD1 6 +#define BM_DIGCTL_ARMCACHE_RSVD1 0xc0 +#define BF_DIGCTL_ARMCACHE_RSVD1(v) (((v) & 0x3) << 6) +#define BFM_DIGCTL_ARMCACHE_RSVD1(v) BM_DIGCTL_ARMCACHE_RSVD1 +#define BF_DIGCTL_ARMCACHE_RSVD1_V(e) BF_DIGCTL_ARMCACHE_RSVD1(BV_DIGCTL_ARMCACHE_RSVD1__##e) +#define BFM_DIGCTL_ARMCACHE_RSVD1_V(v) BM_DIGCTL_ARMCACHE_RSVD1 +#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 +#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 +#define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) & 0x3) << 4) +#define BFM_DIGCTL_ARMCACHE_DTAG_SS(v) BM_DIGCTL_ARMCACHE_DTAG_SS +#define BF_DIGCTL_ARMCACHE_DTAG_SS_V(e) BF_DIGCTL_ARMCACHE_DTAG_SS(BV_DIGCTL_ARMCACHE_DTAG_SS__##e) +#define BFM_DIGCTL_ARMCACHE_DTAG_SS_V(v) BM_DIGCTL_ARMCACHE_DTAG_SS +#define BP_DIGCTL_ARMCACHE_RSVD0 2 +#define BM_DIGCTL_ARMCACHE_RSVD0 0xc +#define BF_DIGCTL_ARMCACHE_RSVD0(v) (((v) & 0x3) << 2) +#define BFM_DIGCTL_ARMCACHE_RSVD0(v) BM_DIGCTL_ARMCACHE_RSVD0 +#define BF_DIGCTL_ARMCACHE_RSVD0_V(e) BF_DIGCTL_ARMCACHE_RSVD0(BV_DIGCTL_ARMCACHE_RSVD0__##e) +#define BFM_DIGCTL_ARMCACHE_RSVD0_V(v) BM_DIGCTL_ARMCACHE_RSVD0 +#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 +#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 +#define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) & 0x3) << 0) +#define BFM_DIGCTL_ARMCACHE_ITAG_SS(v) BM_DIGCTL_ARMCACHE_ITAG_SS +#define BF_DIGCTL_ARMCACHE_ITAG_SS_V(e) BF_DIGCTL_ARMCACHE_ITAG_SS(BV_DIGCTL_ARMCACHE_ITAG_SS__##e) +#define BFM_DIGCTL_ARMCACHE_ITAG_SS_V(v) BM_DIGCTL_ARMCACHE_ITAG_SS + +#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW HW(DIGCTL_DEBUG_TRAP_ADDR_LOW) +#define HWA_DIGCTL_DEBUG_TRAP_ADDR_LOW (0x8001c000 + 0x2c0) +#define HWT_DIGCTL_DEBUG_TRAP_ADDR_LOW HWIO_32_RW +#define HWN_DIGCTL_DEBUG_TRAP_ADDR_LOW DIGCTL_DEBUG_TRAP_ADDR_LOW +#define HWI_DIGCTL_DEBUG_TRAP_ADDR_LOW +#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xffffffff +#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR +#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR_V(e) BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(BV_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR__##e) +#define BFM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR_V(v) BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR + +#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH HW(DIGCTL_DEBUG_TRAP_ADDR_HIGH) +#define HWA_DIGCTL_DEBUG_TRAP_ADDR_HIGH (0x8001c000 + 0x2d0) +#define HWT_DIGCTL_DEBUG_TRAP_ADDR_HIGH HWIO_32_RW +#define HWN_DIGCTL_DEBUG_TRAP_ADDR_HIGH DIGCTL_DEBUG_TRAP_ADDR_HIGH +#define HWI_DIGCTL_DEBUG_TRAP_ADDR_HIGH +#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xffffffff +#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR +#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR_V(e) BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(BV_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR__##e) +#define BFM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR_V(v) BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR + +#define HW_DIGCTL_SGTL HW(DIGCTL_SGTL) +#define HWA_DIGCTL_SGTL (0x8001c000 + 0x300) +#define HWT_DIGCTL_SGTL HWIO_32_RW +#define HWN_DIGCTL_SGTL DIGCTL_SGTL +#define HWI_DIGCTL_SGTL +#define BP_DIGCTL_SGTL_COPYRIGHT 0 +#define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff +#define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_SGTL_COPYRIGHT(v) BM_DIGCTL_SGTL_COPYRIGHT +#define BF_DIGCTL_SGTL_COPYRIGHT_V(e) BF_DIGCTL_SGTL_COPYRIGHT(BV_DIGCTL_SGTL_COPYRIGHT__##e) +#define BFM_DIGCTL_SGTL_COPYRIGHT_V(v) BM_DIGCTL_SGTL_COPYRIGHT + +#define HW_DIGCTL_CHIPID HW(DIGCTL_CHIPID) +#define HWA_DIGCTL_CHIPID (0x8001c000 + 0x310) +#define HWT_DIGCTL_CHIPID HWIO_32_RW +#define HWN_DIGCTL_CHIPID DIGCTL_CHIPID +#define HWI_DIGCTL_CHIPID +#define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 +#define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 +#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) & 0xffff) << 16) +#define BFM_DIGCTL_CHIPID_PRODUCT_CODE(v) BM_DIGCTL_CHIPID_PRODUCT_CODE +#define BF_DIGCTL_CHIPID_PRODUCT_CODE_V(e) BF_DIGCTL_CHIPID_PRODUCT_CODE(BV_DIGCTL_CHIPID_PRODUCT_CODE__##e) +#define BFM_DIGCTL_CHIPID_PRODUCT_CODE_V(v) BM_DIGCTL_CHIPID_PRODUCT_CODE +#define BP_DIGCTL_CHIPID_RSVD0 8 +#define BM_DIGCTL_CHIPID_RSVD0 0xff00 +#define BF_DIGCTL_CHIPID_RSVD0(v) (((v) & 0xff) << 8) +#define BFM_DIGCTL_CHIPID_RSVD0(v) BM_DIGCTL_CHIPID_RSVD0 +#define BF_DIGCTL_CHIPID_RSVD0_V(e) BF_DIGCTL_CHIPID_RSVD0(BV_DIGCTL_CHIPID_RSVD0__##e) +#define BFM_DIGCTL_CHIPID_RSVD0_V(v) BM_DIGCTL_CHIPID_RSVD0 +#define BP_DIGCTL_CHIPID_REVISION 0 +#define BM_DIGCTL_CHIPID_REVISION 0xff +#define BF_DIGCTL_CHIPID_REVISION(v) (((v) & 0xff) << 0) +#define BFM_DIGCTL_CHIPID_REVISION(v) BM_DIGCTL_CHIPID_REVISION +#define BF_DIGCTL_CHIPID_REVISION_V(e) BF_DIGCTL_CHIPID_REVISION(BV_DIGCTL_CHIPID_REVISION__##e) +#define BFM_DIGCTL_CHIPID_REVISION_V(v) BM_DIGCTL_CHIPID_REVISION + +#define HW_DIGCTL_AHB_STATS_SELECT HW(DIGCTL_AHB_STATS_SELECT) +#define HWA_DIGCTL_AHB_STATS_SELECT (0x8001c000 + 0x330) +#define HWT_DIGCTL_AHB_STATS_SELECT HWIO_32_RW +#define HWN_DIGCTL_AHB_STATS_SELECT DIGCTL_AHB_STATS_SELECT +#define HWI_DIGCTL_AHB_STATS_SELECT +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD3 28 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD3 0xf0000000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v) (((v) & 0xf) << 28) +#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD3(v) BM_DIGCTL_AHB_STATS_SELECT_RSVD3 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3_V(e) BF_DIGCTL_AHB_STATS_SELECT_RSVD3(BV_DIGCTL_AHB_STATS_SELECT_RSVD3__##e) +#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD3_V(v) BM_DIGCTL_AHB_STATS_SELECT_RSVD3 +#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24 +#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0xf000000 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4 +#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) (((v) & 0xf) << 24) +#define BFM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT +#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(e) BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__##e) +#define BFM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT_V(v) BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD2 20 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD2 0xf00000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v) (((v) & 0xf) << 20) +#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD2(v) BM_DIGCTL_AHB_STATS_SELECT_RSVD2 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2_V(e) BF_DIGCTL_AHB_STATS_SELECT_RSVD2(BV_DIGCTL_AHB_STATS_SELECT_RSVD2__##e) +#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD2_V(v) BM_DIGCTL_AHB_STATS_SELECT_RSVD2 +#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16 +#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0xf0000 +#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1 +#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) (((v) & 0xf) << 16) +#define BFM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT +#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(e) BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__##e) +#define BFM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT_V(v) BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD1 12 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD1 0xf000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v) (((v) & 0xf) << 12) +#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD1(v) BM_DIGCTL_AHB_STATS_SELECT_RSVD1 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1_V(e) BF_DIGCTL_AHB_STATS_SELECT_RSVD1(BV_DIGCTL_AHB_STATS_SELECT_RSVD1__##e) +#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD1_V(v) BM_DIGCTL_AHB_STATS_SELECT_RSVD1 +#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8 +#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0xf00 +#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1 +#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) (((v) & 0xf) << 8) +#define BFM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT +#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(e) BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__##e) +#define BFM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT_V(v) BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0 4 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0 0xf0 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v) (((v) & 0xf) << 4) +#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD0(v) BM_DIGCTL_AHB_STATS_SELECT_RSVD0 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0_V(e) BF_DIGCTL_AHB_STATS_SELECT_RSVD0(BV_DIGCTL_AHB_STATS_SELECT_RSVD0__##e) +#define BFM_DIGCTL_AHB_STATS_SELECT_RSVD0_V(v) BM_DIGCTL_AHB_STATS_SELECT_RSVD0 +#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0 +#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0xf +#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2 +#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) (((v) & 0xf) << 0) +#define BFM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT +#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(e) BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__##e) +#define BFM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT_V(v) BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT + +#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES HW(DIGCTL_L0_AHB_ACTIVE_CYCLES) +#define HWA_DIGCTL_L0_AHB_ACTIVE_CYCLES (0x8001c000 + 0x340) +#define HWT_DIGCTL_L0_AHB_ACTIVE_CYCLES HWIO_32_RW +#define HWN_DIGCTL_L0_AHB_ACTIVE_CYCLES DIGCTL_L0_AHB_ACTIVE_CYCLES +#define HWI_DIGCTL_L0_AHB_ACTIVE_CYCLES +#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xffffffff +#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT +#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT_V(e) BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT__##e) +#define BFM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT_V(v) BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT + +#define HW_DIGCTL_L0_AHB_DATA_STALLED HW(DIGCTL_L0_AHB_DATA_STALLED) +#define HWA_DIGCTL_L0_AHB_DATA_STALLED (0x8001c000 + 0x350) +#define HWT_DIGCTL_L0_AHB_DATA_STALLED HWIO_32_RW +#define HWN_DIGCTL_L0_AHB_DATA_STALLED DIGCTL_L0_AHB_DATA_STALLED +#define HWI_DIGCTL_L0_AHB_DATA_STALLED +#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xffffffff +#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT +#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT_V(e) BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L0_AHB_DATA_STALLED_COUNT__##e) +#define BFM_DIGCTL_L0_AHB_DATA_STALLED_COUNT_V(v) BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT + +#define HW_DIGCTL_L0_AHB_DATA_CYCLES HW(DIGCTL_L0_AHB_DATA_CYCLES) +#define HWA_DIGCTL_L0_AHB_DATA_CYCLES (0x8001c000 + 0x360) +#define HWT_DIGCTL_L0_AHB_DATA_CYCLES HWIO_32_RW +#define HWN_DIGCTL_L0_AHB_DATA_CYCLES DIGCTL_L0_AHB_DATA_CYCLES +#define HWI_DIGCTL_L0_AHB_DATA_CYCLES +#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xffffffff +#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT +#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT_V(e) BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L0_AHB_DATA_CYCLES_COUNT__##e) +#define BFM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT_V(v) BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT + +#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES HW(DIGCTL_L1_AHB_ACTIVE_CYCLES) +#define HWA_DIGCTL_L1_AHB_ACTIVE_CYCLES (0x8001c000 + 0x370) +#define HWT_DIGCTL_L1_AHB_ACTIVE_CYCLES HWIO_32_RW +#define HWN_DIGCTL_L1_AHB_ACTIVE_CYCLES DIGCTL_L1_AHB_ACTIVE_CYCLES +#define HWI_DIGCTL_L1_AHB_ACTIVE_CYCLES +#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xffffffff +#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT +#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_V(e) BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT__##e) +#define BFM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_V(v) BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT + +#define HW_DIGCTL_L1_AHB_DATA_STALLED HW(DIGCTL_L1_AHB_DATA_STALLED) +#define HWA_DIGCTL_L1_AHB_DATA_STALLED (0x8001c000 + 0x380) +#define HWT_DIGCTL_L1_AHB_DATA_STALLED HWIO_32_RW +#define HWN_DIGCTL_L1_AHB_DATA_STALLED DIGCTL_L1_AHB_DATA_STALLED +#define HWI_DIGCTL_L1_AHB_DATA_STALLED +#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xffffffff +#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT +#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT_V(e) BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L1_AHB_DATA_STALLED_COUNT__##e) +#define BFM_DIGCTL_L1_AHB_DATA_STALLED_COUNT_V(v) BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT + +#define HW_DIGCTL_L1_AHB_DATA_CYCLES HW(DIGCTL_L1_AHB_DATA_CYCLES) +#define HWA_DIGCTL_L1_AHB_DATA_CYCLES (0x8001c000 + 0x390) +#define HWT_DIGCTL_L1_AHB_DATA_CYCLES HWIO_32_RW +#define HWN_DIGCTL_L1_AHB_DATA_CYCLES DIGCTL_L1_AHB_DATA_CYCLES +#define HWI_DIGCTL_L1_AHB_DATA_CYCLES +#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xffffffff +#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT +#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT_V(e) BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L1_AHB_DATA_CYCLES_COUNT__##e) +#define BFM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT_V(v) BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT + +#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES HW(DIGCTL_L2_AHB_ACTIVE_CYCLES) +#define HWA_DIGCTL_L2_AHB_ACTIVE_CYCLES (0x8001c000 + 0x3a0) +#define HWT_DIGCTL_L2_AHB_ACTIVE_CYCLES HWIO_32_RW +#define HWN_DIGCTL_L2_AHB_ACTIVE_CYCLES DIGCTL_L2_AHB_ACTIVE_CYCLES +#define HWI_DIGCTL_L2_AHB_ACTIVE_CYCLES +#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xffffffff +#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT +#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_V(e) BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT__##e) +#define BFM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_V(v) BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT + +#define HW_DIGCTL_L2_AHB_DATA_STALLED HW(DIGCTL_L2_AHB_DATA_STALLED) +#define HWA_DIGCTL_L2_AHB_DATA_STALLED (0x8001c000 + 0x3b0) +#define HWT_DIGCTL_L2_AHB_DATA_STALLED HWIO_32_RW +#define HWN_DIGCTL_L2_AHB_DATA_STALLED DIGCTL_L2_AHB_DATA_STALLED +#define HWI_DIGCTL_L2_AHB_DATA_STALLED +#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xffffffff +#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT +#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT_V(e) BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L2_AHB_DATA_STALLED_COUNT__##e) +#define BFM_DIGCTL_L2_AHB_DATA_STALLED_COUNT_V(v) BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT + +#define HW_DIGCTL_L2_AHB_DATA_CYCLES HW(DIGCTL_L2_AHB_DATA_CYCLES) +#define HWA_DIGCTL_L2_AHB_DATA_CYCLES (0x8001c000 + 0x3c0) +#define HWT_DIGCTL_L2_AHB_DATA_CYCLES HWIO_32_RW +#define HWN_DIGCTL_L2_AHB_DATA_CYCLES DIGCTL_L2_AHB_DATA_CYCLES +#define HWI_DIGCTL_L2_AHB_DATA_CYCLES +#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xffffffff +#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT +#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT_V(e) BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L2_AHB_DATA_CYCLES_COUNT__##e) +#define BFM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT_V(v) BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT + +#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES HW(DIGCTL_L3_AHB_ACTIVE_CYCLES) +#define HWA_DIGCTL_L3_AHB_ACTIVE_CYCLES (0x8001c000 + 0x3d0) +#define HWT_DIGCTL_L3_AHB_ACTIVE_CYCLES HWIO_32_RW +#define HWN_DIGCTL_L3_AHB_ACTIVE_CYCLES DIGCTL_L3_AHB_ACTIVE_CYCLES +#define HWI_DIGCTL_L3_AHB_ACTIVE_CYCLES +#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xffffffff +#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT +#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_V(e) BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(BV_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT__##e) +#define BFM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_V(v) BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT + +#define HW_DIGCTL_L3_AHB_DATA_STALLED HW(DIGCTL_L3_AHB_DATA_STALLED) +#define HWA_DIGCTL_L3_AHB_DATA_STALLED (0x8001c000 + 0x3e0) +#define HWT_DIGCTL_L3_AHB_DATA_STALLED HWIO_32_RW +#define HWN_DIGCTL_L3_AHB_DATA_STALLED DIGCTL_L3_AHB_DATA_STALLED +#define HWI_DIGCTL_L3_AHB_DATA_STALLED +#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xffffffff +#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT +#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT_V(e) BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(BV_DIGCTL_L3_AHB_DATA_STALLED_COUNT__##e) +#define BFM_DIGCTL_L3_AHB_DATA_STALLED_COUNT_V(v) BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT + +#define HW_DIGCTL_L3_AHB_DATA_CYCLES HW(DIGCTL_L3_AHB_DATA_CYCLES) +#define HWA_DIGCTL_L3_AHB_DATA_CYCLES (0x8001c000 + 0x3f0) +#define HWT_DIGCTL_L3_AHB_DATA_CYCLES HWIO_32_RW +#define HWN_DIGCTL_L3_AHB_DATA_CYCLES DIGCTL_L3_AHB_DATA_CYCLES +#define HWI_DIGCTL_L3_AHB_DATA_CYCLES +#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xffffffff +#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (((v) & 0xffffffff) << 0) +#define BFM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT +#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT_V(e) BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(BV_DIGCTL_L3_AHB_DATA_CYCLES_COUNT__##e) +#define BFM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT_V(v) BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT + +#define HW_DIGCTL_MPTEn_LOC(_n1) HW(DIGCTL_MPTEn_LOC(_n1)) +#define HWA_DIGCTL_MPTEn_LOC(_n1) (0x8001c000 + 0x400 + (_n1) * 0x10) +#define HWT_DIGCTL_MPTEn_LOC(_n1) HWIO_32_RW +#define HWN_DIGCTL_MPTEn_LOC(_n1) DIGCTL_MPTEn_LOC +#define HWI_DIGCTL_MPTEn_LOC(_n1) (_n1) +#define BP_DIGCTL_MPTEn_LOC_RSVD0 12 +#define BM_DIGCTL_MPTEn_LOC_RSVD0 0xfffff000 +#define BF_DIGCTL_MPTEn_LOC_RSVD0(v) (((v) & 0xfffff) << 12) +#define BFM_DIGCTL_MPTEn_LOC_RSVD0(v) BM_DIGCTL_MPTEn_LOC_RSVD0 +#define BF_DIGCTL_MPTEn_LOC_RSVD0_V(e) BF_DIGCTL_MPTEn_LOC_RSVD0(BV_DIGCTL_MPTEn_LOC_RSVD0__##e) +#define BFM_DIGCTL_MPTEn_LOC_RSVD0_V(v) BM_DIGCTL_MPTEn_LOC_RSVD0 +#define BP_DIGCTL_MPTEn_LOC_LOC 0 +#define BM_DIGCTL_MPTEn_LOC_LOC 0xfff +#define BF_DIGCTL_MPTEn_LOC_LOC(v) (((v) & 0xfff) << 0) +#define BFM_DIGCTL_MPTEn_LOC_LOC(v) BM_DIGCTL_MPTEn_LOC_LOC +#define BF_DIGCTL_MPTEn_LOC_LOC_V(e) BF_DIGCTL_MPTEn_LOC_LOC(BV_DIGCTL_MPTEn_LOC_LOC__##e) +#define BFM_DIGCTL_MPTEn_LOC_LOC_V(v) BM_DIGCTL_MPTEn_LOC_LOC + +#define HW_DIGCTL_EMICLK_DELAY HW(DIGCTL_EMICLK_DELAY) +#define HWA_DIGCTL_EMICLK_DELAY (0x8001c000 + 0x500) +#define HWT_DIGCTL_EMICLK_DELAY HWIO_32_RW +#define HWN_DIGCTL_EMICLK_DELAY DIGCTL_EMICLK_DELAY +#define HWI_DIGCTL_EMICLK_DELAY +#define BP_DIGCTL_EMICLK_DELAY_RSVD0 5 +#define BM_DIGCTL_EMICLK_DELAY_RSVD0 0xffffffe0 +#define BF_DIGCTL_EMICLK_DELAY_RSVD0(v) (((v) & 0x7ffffff) << 5) +#define BFM_DIGCTL_EMICLK_DELAY_RSVD0(v) BM_DIGCTL_EMICLK_DELAY_RSVD0 +#define BF_DIGCTL_EMICLK_DELAY_RSVD0_V(e) BF_DIGCTL_EMICLK_DELAY_RSVD0(BV_DIGCTL_EMICLK_DELAY_RSVD0__##e) +#define BFM_DIGCTL_EMICLK_DELAY_RSVD0_V(v) BM_DIGCTL_EMICLK_DELAY_RSVD0 +#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0 +#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x1f +#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) (((v) & 0x1f) << 0) +#define BFM_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) BM_DIGCTL_EMICLK_DELAY_NUM_TAPS +#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS_V(e) BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(BV_DIGCTL_EMICLK_DELAY_NUM_TAPS__##e) +#define BFM_DIGCTL_EMICLK_DELAY_NUM_TAPS_V(v) BM_DIGCTL_EMICLK_DELAY_NUM_TAPS + +#endif /* __HEADERGEN_IMX233_DIGCTL_H__*/ diff --git a/firmware/target/arm/imx233/regs/imx233/dram.h b/firmware/target/arm/imx233/regs/imx233/dram.h new file mode 100644 index 0000000000..c8bafc2881 --- /dev/null +++ b/firmware/target/arm/imx233/regs/imx233/dram.h @@ -0,0 +1,1599 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * imx233 version: 2.4.0 + * imx233 authors: Amaury Pouly + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_IMX233_DRAM_H__ +#define __HEADERGEN_IMX233_DRAM_H__ + +#define HW_DRAM_CTL00 HW(DRAM_CTL00) +#define HWA_DRAM_CTL00 (0x800e0000 + 0x0) +#define HWT_DRAM_CTL00 HWIO_32_RW +#define HWN_DRAM_CTL00 DRAM_CTL00 +#define HWI_DRAM_CTL00 +#define BP_DRAM_CTL00_RSVD4 25 +#define BM_DRAM_CTL00_RSVD4 0xfe000000 +#define BF_DRAM_CTL00_RSVD4(v) (((v) & 0x7f) << 25) +#define BFM_DRAM_CTL00_RSVD4(v) BM_DRAM_CTL00_RSVD4 +#define BF_DRAM_CTL00_RSVD4_V(e) BF_DRAM_CTL00_RSVD4(BV_DRAM_CTL00_RSVD4__##e) +#define BFM_DRAM_CTL00_RSVD4_V(v) BM_DRAM_CTL00_RSVD4 +#define BP_DRAM_CTL00_AHB0_W_PRIORITY 24 +#define BM_DRAM_CTL00_AHB0_W_PRIORITY 0x1000000 +#define BF_DRAM_CTL00_AHB0_W_PRIORITY(v) (((v) & 0x1) << 24) +#define BFM_DRAM_CTL00_AHB0_W_PRIORITY(v) BM_DRAM_CTL00_AHB0_W_PRIORITY +#define BF_DRAM_CTL00_AHB0_W_PRIORITY_V(e) BF_DRAM_CTL00_AHB0_W_PRIORITY(BV_DRAM_CTL00_AHB0_W_PRIORITY__##e) +#define BFM_DRAM_CTL00_AHB0_W_PRIORITY_V(v) BM_DRAM_CTL00_AHB0_W_PRIORITY +#define BP_DRAM_CTL00_RSVD3 17 +#define BM_DRAM_CTL00_RSVD3 0xfe0000 +#define BF_DRAM_CTL00_RSVD3(v) (((v) & 0x7f) << 17) +#define BFM_DRAM_CTL00_RSVD3(v) BM_DRAM_CTL00_RSVD3 +#define BF_DRAM_CTL00_RSVD3_V(e) BF_DRAM_CTL00_RSVD3(BV_DRAM_CTL00_RSVD3__##e) +#define BFM_DRAM_CTL00_RSVD3_V(v) BM_DRAM_CTL00_RSVD3 +#define BP_DRAM_CTL00_AHB0_R_PRIORITY 16 +#define BM_DRAM_CTL00_AHB0_R_PRIORITY 0x10000 +#define BF_DRAM_CTL00_AHB0_R_PRIORITY(v) (((v) & 0x1) << 16) +#define BFM_DRAM_CTL00_AHB0_R_PRIORITY(v) BM_DRAM_CTL00_AHB0_R_PRIORITY +#define BF_DRAM_CTL00_AHB0_R_PRIORITY_V(e) BF_DRAM_CTL00_AHB0_R_PRIORITY(BV_DRAM_CTL00_AHB0_R_PRIORITY__##e) +#define BFM_DRAM_CTL00_AHB0_R_PRIORITY_V(v) BM_DRAM_CTL00_AHB0_R_PRIORITY +#define BP_DRAM_CTL00_RSVD2 9 +#define BM_DRAM_CTL00_RSVD2 0xfe00 +#define BF_DRAM_CTL00_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL00_RSVD2(v) BM_DRAM_CTL00_RSVD2 +#define BF_DRAM_CTL00_RSVD2_V(e) BF_DRAM_CTL00_RSVD2(BV_DRAM_CTL00_RSVD2__##e) +#define BFM_DRAM_CTL00_RSVD2_V(v) BM_DRAM_CTL00_RSVD2 +#define BP_DRAM_CTL00_AHB0_FIFO_TYPE_REG 8 +#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG 0x100 +#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL00_AHB0_FIFO_TYPE_REG(v) BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG +#define BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG_V(e) BF_DRAM_CTL00_AHB0_FIFO_TYPE_REG(BV_DRAM_CTL00_AHB0_FIFO_TYPE_REG__##e) +#define BFM_DRAM_CTL00_AHB0_FIFO_TYPE_REG_V(v) BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG +#define BP_DRAM_CTL00_RSVD1 1 +#define BM_DRAM_CTL00_RSVD1 0xfe +#define BF_DRAM_CTL00_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL00_RSVD1(v) BM_DRAM_CTL00_RSVD1 +#define BF_DRAM_CTL00_RSVD1_V(e) BF_DRAM_CTL00_RSVD1(BV_DRAM_CTL00_RSVD1__##e) +#define BFM_DRAM_CTL00_RSVD1_V(v) BM_DRAM_CTL00_RSVD1 +#define BP_DRAM_CTL00_ADDR_CMP_EN 0 +#define BM_DRAM_CTL00_ADDR_CMP_EN 0x1 +#define BF_DRAM_CTL00_ADDR_CMP_EN(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL00_ADDR_CMP_EN(v) BM_DRAM_CTL00_ADDR_CMP_EN +#define BF_DRAM_CTL00_ADDR_CMP_EN_V(e) BF_DRAM_CTL00_ADDR_CMP_EN(BV_DRAM_CTL00_ADDR_CMP_EN__##e) +#define BFM_DRAM_CTL00_ADDR_CMP_EN_V(v) BM_DRAM_CTL00_ADDR_CMP_EN + +#define HW_DRAM_CTL01 HW(DRAM_CTL01) +#define HWA_DRAM_CTL01 (0x800e0000 + 0x4) +#define HWT_DRAM_CTL01 HWIO_32_RW +#define HWN_DRAM_CTL01 DRAM_CTL01 +#define HWI_DRAM_CTL01 +#define BP_DRAM_CTL01_RSVD4 25 +#define BM_DRAM_CTL01_RSVD4 0xfe000000 +#define BF_DRAM_CTL01_RSVD4(v) (((v) & 0x7f) << 25) +#define BFM_DRAM_CTL01_RSVD4(v) BM_DRAM_CTL01_RSVD4 +#define BF_DRAM_CTL01_RSVD4_V(e) BF_DRAM_CTL01_RSVD4(BV_DRAM_CTL01_RSVD4__##e) +#define BFM_DRAM_CTL01_RSVD4_V(v) BM_DRAM_CTL01_RSVD4 +#define BP_DRAM_CTL01_AHB2_FIFO_TYPE_REG 24 +#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG 0x1000000 +#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) (((v) & 0x1) << 24) +#define BFM_DRAM_CTL01_AHB2_FIFO_TYPE_REG(v) BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG +#define BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG_V(e) BF_DRAM_CTL01_AHB2_FIFO_TYPE_REG(BV_DRAM_CTL01_AHB2_FIFO_TYPE_REG__##e) +#define BFM_DRAM_CTL01_AHB2_FIFO_TYPE_REG_V(v) BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG +#define BP_DRAM_CTL01_RSVD3 17 +#define BM_DRAM_CTL01_RSVD3 0xfe0000 +#define BF_DRAM_CTL01_RSVD3(v) (((v) & 0x7f) << 17) +#define BFM_DRAM_CTL01_RSVD3(v) BM_DRAM_CTL01_RSVD3 +#define BF_DRAM_CTL01_RSVD3_V(e) BF_DRAM_CTL01_RSVD3(BV_DRAM_CTL01_RSVD3__##e) +#define BFM_DRAM_CTL01_RSVD3_V(v) BM_DRAM_CTL01_RSVD3 +#define BP_DRAM_CTL01_AHB1_W_PRIORITY 16 +#define BM_DRAM_CTL01_AHB1_W_PRIORITY 0x10000 +#define BF_DRAM_CTL01_AHB1_W_PRIORITY(v) (((v) & 0x1) << 16) +#define BFM_DRAM_CTL01_AHB1_W_PRIORITY(v) BM_DRAM_CTL01_AHB1_W_PRIORITY +#define BF_DRAM_CTL01_AHB1_W_PRIORITY_V(e) BF_DRAM_CTL01_AHB1_W_PRIORITY(BV_DRAM_CTL01_AHB1_W_PRIORITY__##e) +#define BFM_DRAM_CTL01_AHB1_W_PRIORITY_V(v) BM_DRAM_CTL01_AHB1_W_PRIORITY +#define BP_DRAM_CTL01_RSVD2 9 +#define BM_DRAM_CTL01_RSVD2 0xfe00 +#define BF_DRAM_CTL01_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL01_RSVD2(v) BM_DRAM_CTL01_RSVD2 +#define BF_DRAM_CTL01_RSVD2_V(e) BF_DRAM_CTL01_RSVD2(BV_DRAM_CTL01_RSVD2__##e) +#define BFM_DRAM_CTL01_RSVD2_V(v) BM_DRAM_CTL01_RSVD2 +#define BP_DRAM_CTL01_AHB1_R_PRIORITY 8 +#define BM_DRAM_CTL01_AHB1_R_PRIORITY 0x100 +#define BF_DRAM_CTL01_AHB1_R_PRIORITY(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL01_AHB1_R_PRIORITY(v) BM_DRAM_CTL01_AHB1_R_PRIORITY +#define BF_DRAM_CTL01_AHB1_R_PRIORITY_V(e) BF_DRAM_CTL01_AHB1_R_PRIORITY(BV_DRAM_CTL01_AHB1_R_PRIORITY__##e) +#define BFM_DRAM_CTL01_AHB1_R_PRIORITY_V(v) BM_DRAM_CTL01_AHB1_R_PRIORITY +#define BP_DRAM_CTL01_RSVD1 1 +#define BM_DRAM_CTL01_RSVD1 0xfe +#define BF_DRAM_CTL01_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL01_RSVD1(v) BM_DRAM_CTL01_RSVD1 +#define BF_DRAM_CTL01_RSVD1_V(e) BF_DRAM_CTL01_RSVD1(BV_DRAM_CTL01_RSVD1__##e) +#define BFM_DRAM_CTL01_RSVD1_V(v) BM_DRAM_CTL01_RSVD1 +#define BP_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0 +#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0x1 +#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL01_AHB1_FIFO_TYPE_REG(v) BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG +#define BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG_V(e) BF_DRAM_CTL01_AHB1_FIFO_TYPE_REG(BV_DRAM_CTL01_AHB1_FIFO_TYPE_REG__##e) +#define BFM_DRAM_CTL01_AHB1_FIFO_TYPE_REG_V(v) BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG + +#define HW_DRAM_CTL02 HW(DRAM_CTL02) +#define HWA_DRAM_CTL02 (0x800e0000 + 0x8) +#define HWT_DRAM_CTL02 HWIO_32_RW +#define HWN_DRAM_CTL02 DRAM_CTL02 +#define HWI_DRAM_CTL02 +#define BP_DRAM_CTL02_RSVD4 25 +#define BM_DRAM_CTL02_RSVD4 0xfe000000 +#define BF_DRAM_CTL02_RSVD4(v) (((v) & 0x7f) << 25) +#define BFM_DRAM_CTL02_RSVD4(v) BM_DRAM_CTL02_RSVD4 +#define BF_DRAM_CTL02_RSVD4_V(e) BF_DRAM_CTL02_RSVD4(BV_DRAM_CTL02_RSVD4__##e) +#define BFM_DRAM_CTL02_RSVD4_V(v) BM_DRAM_CTL02_RSVD4 +#define BP_DRAM_CTL02_AHB3_R_PRIORITY 24 +#define BM_DRAM_CTL02_AHB3_R_PRIORITY 0x1000000 +#define BF_DRAM_CTL02_AHB3_R_PRIORITY(v) (((v) & 0x1) << 24) +#define BFM_DRAM_CTL02_AHB3_R_PRIORITY(v) BM_DRAM_CTL02_AHB3_R_PRIORITY +#define BF_DRAM_CTL02_AHB3_R_PRIORITY_V(e) BF_DRAM_CTL02_AHB3_R_PRIORITY(BV_DRAM_CTL02_AHB3_R_PRIORITY__##e) +#define BFM_DRAM_CTL02_AHB3_R_PRIORITY_V(v) BM_DRAM_CTL02_AHB3_R_PRIORITY +#define BP_DRAM_CTL02_RSVD3 17 +#define BM_DRAM_CTL02_RSVD3 0xfe0000 +#define BF_DRAM_CTL02_RSVD3(v) (((v) & 0x7f) << 17) +#define BFM_DRAM_CTL02_RSVD3(v) BM_DRAM_CTL02_RSVD3 +#define BF_DRAM_CTL02_RSVD3_V(e) BF_DRAM_CTL02_RSVD3(BV_DRAM_CTL02_RSVD3__##e) +#define BFM_DRAM_CTL02_RSVD3_V(v) BM_DRAM_CTL02_RSVD3 +#define BP_DRAM_CTL02_AHB3_FIFO_TYPE_REG 16 +#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG 0x10000 +#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) (((v) & 0x1) << 16) +#define BFM_DRAM_CTL02_AHB3_FIFO_TYPE_REG(v) BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG +#define BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG_V(e) BF_DRAM_CTL02_AHB3_FIFO_TYPE_REG(BV_DRAM_CTL02_AHB3_FIFO_TYPE_REG__##e) +#define BFM_DRAM_CTL02_AHB3_FIFO_TYPE_REG_V(v) BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG +#define BP_DRAM_CTL02_RSVD2 9 +#define BM_DRAM_CTL02_RSVD2 0xfe00 +#define BF_DRAM_CTL02_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL02_RSVD2(v) BM_DRAM_CTL02_RSVD2 +#define BF_DRAM_CTL02_RSVD2_V(e) BF_DRAM_CTL02_RSVD2(BV_DRAM_CTL02_RSVD2__##e) +#define BFM_DRAM_CTL02_RSVD2_V(v) BM_DRAM_CTL02_RSVD2 +#define BP_DRAM_CTL02_AHB2_W_PRIORITY 8 +#define BM_DRAM_CTL02_AHB2_W_PRIORITY 0x100 +#define BF_DRAM_CTL02_AHB2_W_PRIORITY(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL02_AHB2_W_PRIORITY(v) BM_DRAM_CTL02_AHB2_W_PRIORITY +#define BF_DRAM_CTL02_AHB2_W_PRIORITY_V(e) BF_DRAM_CTL02_AHB2_W_PRIORITY(BV_DRAM_CTL02_AHB2_W_PRIORITY__##e) +#define BFM_DRAM_CTL02_AHB2_W_PRIORITY_V(v) BM_DRAM_CTL02_AHB2_W_PRIORITY +#define BP_DRAM_CTL02_RSVD1 1 +#define BM_DRAM_CTL02_RSVD1 0xfe +#define BF_DRAM_CTL02_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL02_RSVD1(v) BM_DRAM_CTL02_RSVD1 +#define BF_DRAM_CTL02_RSVD1_V(e) BF_DRAM_CTL02_RSVD1(BV_DRAM_CTL02_RSVD1__##e) +#define BFM_DRAM_CTL02_RSVD1_V(v) BM_DRAM_CTL02_RSVD1 +#define BP_DRAM_CTL02_AHB2_R_PRIORITY 0 +#define BM_DRAM_CTL02_AHB2_R_PRIORITY 0x1 +#define BF_DRAM_CTL02_AHB2_R_PRIORITY(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL02_AHB2_R_PRIORITY(v) BM_DRAM_CTL02_AHB2_R_PRIORITY +#define BF_DRAM_CTL02_AHB2_R_PRIORITY_V(e) BF_DRAM_CTL02_AHB2_R_PRIORITY(BV_DRAM_CTL02_AHB2_R_PRIORITY__##e) +#define BFM_DRAM_CTL02_AHB2_R_PRIORITY_V(v) BM_DRAM_CTL02_AHB2_R_PRIORITY + +#define HW_DRAM_CTL03 HW(DRAM_CTL03) +#define HWA_DRAM_CTL03 (0x800e0000 + 0xc) +#define HWT_DRAM_CTL03 HWIO_32_RW +#define HWN_DRAM_CTL03 DRAM_CTL03 +#define HWI_DRAM_CTL03 +#define BP_DRAM_CTL03_RSVD4 25 +#define BM_DRAM_CTL03_RSVD4 0xfe000000 +#define BF_DRAM_CTL03_RSVD4(v) (((v) & 0x7f) << 25) +#define BFM_DRAM_CTL03_RSVD4(v) BM_DRAM_CTL03_RSVD4 +#define BF_DRAM_CTL03_RSVD4_V(e) BF_DRAM_CTL03_RSVD4(BV_DRAM_CTL03_RSVD4__##e) +#define BFM_DRAM_CTL03_RSVD4_V(v) BM_DRAM_CTL03_RSVD4 +#define BP_DRAM_CTL03_AUTO_REFRESH_MODE 24 +#define BM_DRAM_CTL03_AUTO_REFRESH_MODE 0x1000000 +#define BF_DRAM_CTL03_AUTO_REFRESH_MODE(v) (((v) & 0x1) << 24) +#define BFM_DRAM_CTL03_AUTO_REFRESH_MODE(v) BM_DRAM_CTL03_AUTO_REFRESH_MODE +#define BF_DRAM_CTL03_AUTO_REFRESH_MODE_V(e) BF_DRAM_CTL03_AUTO_REFRESH_MODE(BV_DRAM_CTL03_AUTO_REFRESH_MODE__##e) +#define BFM_DRAM_CTL03_AUTO_REFRESH_MODE_V(v) BM_DRAM_CTL03_AUTO_REFRESH_MODE +#define BP_DRAM_CTL03_RSVD3 17 +#define BM_DRAM_CTL03_RSVD3 0xfe0000 +#define BF_DRAM_CTL03_RSVD3(v) (((v) & 0x7f) << 17) +#define BFM_DRAM_CTL03_RSVD3(v) BM_DRAM_CTL03_RSVD3 +#define BF_DRAM_CTL03_RSVD3_V(e) BF_DRAM_CTL03_RSVD3(BV_DRAM_CTL03_RSVD3__##e) +#define BFM_DRAM_CTL03_RSVD3_V(v) BM_DRAM_CTL03_RSVD3 +#define BP_DRAM_CTL03_AREFRESH 16 +#define BM_DRAM_CTL03_AREFRESH 0x10000 +#define BF_DRAM_CTL03_AREFRESH(v) (((v) & 0x1) << 16) +#define BFM_DRAM_CTL03_AREFRESH(v) BM_DRAM_CTL03_AREFRESH +#define BF_DRAM_CTL03_AREFRESH_V(e) BF_DRAM_CTL03_AREFRESH(BV_DRAM_CTL03_AREFRESH__##e) +#define BFM_DRAM_CTL03_AREFRESH_V(v) BM_DRAM_CTL03_AREFRESH +#define BP_DRAM_CTL03_RSVD2 9 +#define BM_DRAM_CTL03_RSVD2 0xfe00 +#define BF_DRAM_CTL03_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL03_RSVD2(v) BM_DRAM_CTL03_RSVD2 +#define BF_DRAM_CTL03_RSVD2_V(e) BF_DRAM_CTL03_RSVD2(BV_DRAM_CTL03_RSVD2__##e) +#define BFM_DRAM_CTL03_RSVD2_V(v) BM_DRAM_CTL03_RSVD2 +#define BP_DRAM_CTL03_AP 8 +#define BM_DRAM_CTL03_AP 0x100 +#define BF_DRAM_CTL03_AP(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL03_AP(v) BM_DRAM_CTL03_AP +#define BF_DRAM_CTL03_AP_V(e) BF_DRAM_CTL03_AP(BV_DRAM_CTL03_AP__##e) +#define BFM_DRAM_CTL03_AP_V(v) BM_DRAM_CTL03_AP +#define BP_DRAM_CTL03_RSVD1 1 +#define BM_DRAM_CTL03_RSVD1 0xfe +#define BF_DRAM_CTL03_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL03_RSVD1(v) BM_DRAM_CTL03_RSVD1 +#define BF_DRAM_CTL03_RSVD1_V(e) BF_DRAM_CTL03_RSVD1(BV_DRAM_CTL03_RSVD1__##e) +#define BFM_DRAM_CTL03_RSVD1_V(v) BM_DRAM_CTL03_RSVD1 +#define BP_DRAM_CTL03_AHB3_W_PRIORITY 0 +#define BM_DRAM_CTL03_AHB3_W_PRIORITY 0x1 +#define BF_DRAM_CTL03_AHB3_W_PRIORITY(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL03_AHB3_W_PRIORITY(v) BM_DRAM_CTL03_AHB3_W_PRIORITY +#define BF_DRAM_CTL03_AHB3_W_PRIORITY_V(e) BF_DRAM_CTL03_AHB3_W_PRIORITY(BV_DRAM_CTL03_AHB3_W_PRIORITY__##e) +#define BFM_DRAM_CTL03_AHB3_W_PRIORITY_V(v) BM_DRAM_CTL03_AHB3_W_PRIORITY + +#define HW_DRAM_CTL04 HW(DRAM_CTL04) +#define HWA_DRAM_CTL04 (0x800e0000 + 0x10) +#define HWT_DRAM_CTL04 HWIO_32_RW +#define HWN_DRAM_CTL04 DRAM_CTL04 +#define HWI_DRAM_CTL04 +#define BP_DRAM_CTL04_RSVD4 25 +#define BM_DRAM_CTL04_RSVD4 0xfe000000 +#define BF_DRAM_CTL04_RSVD4(v) (((v) & 0x7f) << 25) +#define BFM_DRAM_CTL04_RSVD4(v) BM_DRAM_CTL04_RSVD4 +#define BF_DRAM_CTL04_RSVD4_V(e) BF_DRAM_CTL04_RSVD4(BV_DRAM_CTL04_RSVD4__##e) +#define BFM_DRAM_CTL04_RSVD4_V(v) BM_DRAM_CTL04_RSVD4 +#define BP_DRAM_CTL04_DLL_BYPASS_MODE 24 +#define BM_DRAM_CTL04_DLL_BYPASS_MODE 0x1000000 +#define BF_DRAM_CTL04_DLL_BYPASS_MODE(v) (((v) & 0x1) << 24) +#define BFM_DRAM_CTL04_DLL_BYPASS_MODE(v) BM_DRAM_CTL04_DLL_BYPASS_MODE +#define BF_DRAM_CTL04_DLL_BYPASS_MODE_V(e) BF_DRAM_CTL04_DLL_BYPASS_MODE(BV_DRAM_CTL04_DLL_BYPASS_MODE__##e) +#define BFM_DRAM_CTL04_DLL_BYPASS_MODE_V(v) BM_DRAM_CTL04_DLL_BYPASS_MODE +#define BP_DRAM_CTL04_RSVD3 17 +#define BM_DRAM_CTL04_RSVD3 0xfe0000 +#define BF_DRAM_CTL04_RSVD3(v) (((v) & 0x7f) << 17) +#define BFM_DRAM_CTL04_RSVD3(v) BM_DRAM_CTL04_RSVD3 +#define BF_DRAM_CTL04_RSVD3_V(e) BF_DRAM_CTL04_RSVD3(BV_DRAM_CTL04_RSVD3__##e) +#define BFM_DRAM_CTL04_RSVD3_V(v) BM_DRAM_CTL04_RSVD3 +#define BP_DRAM_CTL04_DLLLOCKREG 16 +#define BM_DRAM_CTL04_DLLLOCKREG 0x10000 +#define BF_DRAM_CTL04_DLLLOCKREG(v) (((v) & 0x1) << 16) +#define BFM_DRAM_CTL04_DLLLOCKREG(v) BM_DRAM_CTL04_DLLLOCKREG +#define BF_DRAM_CTL04_DLLLOCKREG_V(e) BF_DRAM_CTL04_DLLLOCKREG(BV_DRAM_CTL04_DLLLOCKREG__##e) +#define BFM_DRAM_CTL04_DLLLOCKREG_V(v) BM_DRAM_CTL04_DLLLOCKREG +#define BP_DRAM_CTL04_RSVD2 9 +#define BM_DRAM_CTL04_RSVD2 0xfe00 +#define BF_DRAM_CTL04_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL04_RSVD2(v) BM_DRAM_CTL04_RSVD2 +#define BF_DRAM_CTL04_RSVD2_V(e) BF_DRAM_CTL04_RSVD2(BV_DRAM_CTL04_RSVD2__##e) +#define BFM_DRAM_CTL04_RSVD2_V(v) BM_DRAM_CTL04_RSVD2 +#define BP_DRAM_CTL04_CONCURRENTAP 8 +#define BM_DRAM_CTL04_CONCURRENTAP 0x100 +#define BF_DRAM_CTL04_CONCURRENTAP(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL04_CONCURRENTAP(v) BM_DRAM_CTL04_CONCURRENTAP +#define BF_DRAM_CTL04_CONCURRENTAP_V(e) BF_DRAM_CTL04_CONCURRENTAP(BV_DRAM_CTL04_CONCURRENTAP__##e) +#define BFM_DRAM_CTL04_CONCURRENTAP_V(v) BM_DRAM_CTL04_CONCURRENTAP +#define BP_DRAM_CTL04_RSVD1 1 +#define BM_DRAM_CTL04_RSVD1 0xfe +#define BF_DRAM_CTL04_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL04_RSVD1(v) BM_DRAM_CTL04_RSVD1 +#define BF_DRAM_CTL04_RSVD1_V(e) BF_DRAM_CTL04_RSVD1(BV_DRAM_CTL04_RSVD1__##e) +#define BFM_DRAM_CTL04_RSVD1_V(v) BM_DRAM_CTL04_RSVD1 +#define BP_DRAM_CTL04_BANK_SPLIT_EN 0 +#define BM_DRAM_CTL04_BANK_SPLIT_EN 0x1 +#define BF_DRAM_CTL04_BANK_SPLIT_EN(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL04_BANK_SPLIT_EN(v) BM_DRAM_CTL04_BANK_SPLIT_EN +#define BF_DRAM_CTL04_BANK_SPLIT_EN_V(e) BF_DRAM_CTL04_BANK_SPLIT_EN(BV_DRAM_CTL04_BANK_SPLIT_EN__##e) +#define BFM_DRAM_CTL04_BANK_SPLIT_EN_V(v) BM_DRAM_CTL04_BANK_SPLIT_EN + +#define HW_DRAM_CTL05 HW(DRAM_CTL05) +#define HWA_DRAM_CTL05 (0x800e0000 + 0x14) +#define HWT_DRAM_CTL05 HWIO_32_RW +#define HWN_DRAM_CTL05 DRAM_CTL05 +#define HWI_DRAM_CTL05 +#define BP_DRAM_CTL05_RSVD4 25 +#define BM_DRAM_CTL05_RSVD4 0xfe000000 +#define BF_DRAM_CTL05_RSVD4(v) (((v) & 0x7f) << 25) +#define BFM_DRAM_CTL05_RSVD4(v) BM_DRAM_CTL05_RSVD4 +#define BF_DRAM_CTL05_RSVD4_V(e) BF_DRAM_CTL05_RSVD4(BV_DRAM_CTL05_RSVD4__##e) +#define BFM_DRAM_CTL05_RSVD4_V(v) BM_DRAM_CTL05_RSVD4 +#define BP_DRAM_CTL05_INTRPTREADA 24 +#define BM_DRAM_CTL05_INTRPTREADA 0x1000000 +#define BF_DRAM_CTL05_INTRPTREADA(v) (((v) & 0x1) << 24) +#define BFM_DRAM_CTL05_INTRPTREADA(v) BM_DRAM_CTL05_INTRPTREADA +#define BF_DRAM_CTL05_INTRPTREADA_V(e) BF_DRAM_CTL05_INTRPTREADA(BV_DRAM_CTL05_INTRPTREADA__##e) +#define BFM_DRAM_CTL05_INTRPTREADA_V(v) BM_DRAM_CTL05_INTRPTREADA +#define BP_DRAM_CTL05_RSVD3 17 +#define BM_DRAM_CTL05_RSVD3 0xfe0000 +#define BF_DRAM_CTL05_RSVD3(v) (((v) & 0x7f) << 17) +#define BFM_DRAM_CTL05_RSVD3(v) BM_DRAM_CTL05_RSVD3 +#define BF_DRAM_CTL05_RSVD3_V(e) BF_DRAM_CTL05_RSVD3(BV_DRAM_CTL05_RSVD3__##e) +#define BFM_DRAM_CTL05_RSVD3_V(v) BM_DRAM_CTL05_RSVD3 +#define BP_DRAM_CTL05_INTRPTAPBURST 16 +#define BM_DRAM_CTL05_INTRPTAPBURST 0x10000 +#define BF_DRAM_CTL05_INTRPTAPBURST(v) (((v) & 0x1) << 16) +#define BFM_DRAM_CTL05_INTRPTAPBURST(v) BM_DRAM_CTL05_INTRPTAPBURST +#define BF_DRAM_CTL05_INTRPTAPBURST_V(e) BF_DRAM_CTL05_INTRPTAPBURST(BV_DRAM_CTL05_INTRPTAPBURST__##e) +#define BFM_DRAM_CTL05_INTRPTAPBURST_V(v) BM_DRAM_CTL05_INTRPTAPBURST +#define BP_DRAM_CTL05_RSVD2 9 +#define BM_DRAM_CTL05_RSVD2 0xfe00 +#define BF_DRAM_CTL05_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL05_RSVD2(v) BM_DRAM_CTL05_RSVD2 +#define BF_DRAM_CTL05_RSVD2_V(e) BF_DRAM_CTL05_RSVD2(BV_DRAM_CTL05_RSVD2__##e) +#define BFM_DRAM_CTL05_RSVD2_V(v) BM_DRAM_CTL05_RSVD2 +#define BP_DRAM_CTL05_FAST_WRITE 8 +#define BM_DRAM_CTL05_FAST_WRITE 0x100 +#define BF_DRAM_CTL05_FAST_WRITE(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL05_FAST_WRITE(v) BM_DRAM_CTL05_FAST_WRITE +#define BF_DRAM_CTL05_FAST_WRITE_V(e) BF_DRAM_CTL05_FAST_WRITE(BV_DRAM_CTL05_FAST_WRITE__##e) +#define BFM_DRAM_CTL05_FAST_WRITE_V(v) BM_DRAM_CTL05_FAST_WRITE +#define BP_DRAM_CTL05_RSVD1 1 +#define BM_DRAM_CTL05_RSVD1 0xfe +#define BF_DRAM_CTL05_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL05_RSVD1(v) BM_DRAM_CTL05_RSVD1 +#define BF_DRAM_CTL05_RSVD1_V(e) BF_DRAM_CTL05_RSVD1(BV_DRAM_CTL05_RSVD1__##e) +#define BFM_DRAM_CTL05_RSVD1_V(v) BM_DRAM_CTL05_RSVD1 +#define BP_DRAM_CTL05_EN_LOWPOWER_MODE 0 +#define BM_DRAM_CTL05_EN_LOWPOWER_MODE 0x1 +#define BF_DRAM_CTL05_EN_LOWPOWER_MODE(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL05_EN_LOWPOWER_MODE(v) BM_DRAM_CTL05_EN_LOWPOWER_MODE +#define BF_DRAM_CTL05_EN_LOWPOWER_MODE_V(e) BF_DRAM_CTL05_EN_LOWPOWER_MODE(BV_DRAM_CTL05_EN_LOWPOWER_MODE__##e) +#define BFM_DRAM_CTL05_EN_LOWPOWER_MODE_V(v) BM_DRAM_CTL05_EN_LOWPOWER_MODE + +#define HW_DRAM_CTL06 HW(DRAM_CTL06) +#define HWA_DRAM_CTL06 (0x800e0000 + 0x18) +#define HWT_DRAM_CTL06 HWIO_32_RW +#define HWN_DRAM_CTL06 DRAM_CTL06 +#define HWI_DRAM_CTL06 +#define BP_DRAM_CTL06_RSVD4 25 +#define BM_DRAM_CTL06_RSVD4 0xfe000000 +#define BF_DRAM_CTL06_RSVD4(v) (((v) & 0x7f) << 25) +#define BFM_DRAM_CTL06_RSVD4(v) BM_DRAM_CTL06_RSVD4 +#define BF_DRAM_CTL06_RSVD4_V(e) BF_DRAM_CTL06_RSVD4(BV_DRAM_CTL06_RSVD4__##e) +#define BFM_DRAM_CTL06_RSVD4_V(v) BM_DRAM_CTL06_RSVD4 +#define BP_DRAM_CTL06_POWER_DOWN 24 +#define BM_DRAM_CTL06_POWER_DOWN 0x1000000 +#define BF_DRAM_CTL06_POWER_DOWN(v) (((v) & 0x1) << 24) +#define BFM_DRAM_CTL06_POWER_DOWN(v) BM_DRAM_CTL06_POWER_DOWN +#define BF_DRAM_CTL06_POWER_DOWN_V(e) BF_DRAM_CTL06_POWER_DOWN(BV_DRAM_CTL06_POWER_DOWN__##e) +#define BFM_DRAM_CTL06_POWER_DOWN_V(v) BM_DRAM_CTL06_POWER_DOWN +#define BP_DRAM_CTL06_RSVD3 17 +#define BM_DRAM_CTL06_RSVD3 0xfe0000 +#define BF_DRAM_CTL06_RSVD3(v) (((v) & 0x7f) << 17) +#define BFM_DRAM_CTL06_RSVD3(v) BM_DRAM_CTL06_RSVD3 +#define BF_DRAM_CTL06_RSVD3_V(e) BF_DRAM_CTL06_RSVD3(BV_DRAM_CTL06_RSVD3__##e) +#define BFM_DRAM_CTL06_RSVD3_V(v) BM_DRAM_CTL06_RSVD3 +#define BP_DRAM_CTL06_PLACEMENT_EN 16 +#define BM_DRAM_CTL06_PLACEMENT_EN 0x10000 +#define BF_DRAM_CTL06_PLACEMENT_EN(v) (((v) & 0x1) << 16) +#define BFM_DRAM_CTL06_PLACEMENT_EN(v) BM_DRAM_CTL06_PLACEMENT_EN +#define BF_DRAM_CTL06_PLACEMENT_EN_V(e) BF_DRAM_CTL06_PLACEMENT_EN(BV_DRAM_CTL06_PLACEMENT_EN__##e) +#define BFM_DRAM_CTL06_PLACEMENT_EN_V(v) BM_DRAM_CTL06_PLACEMENT_EN +#define BP_DRAM_CTL06_RSVD2 9 +#define BM_DRAM_CTL06_RSVD2 0xfe00 +#define BF_DRAM_CTL06_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL06_RSVD2(v) BM_DRAM_CTL06_RSVD2 +#define BF_DRAM_CTL06_RSVD2_V(e) BF_DRAM_CTL06_RSVD2(BV_DRAM_CTL06_RSVD2__##e) +#define BFM_DRAM_CTL06_RSVD2_V(v) BM_DRAM_CTL06_RSVD2 +#define BP_DRAM_CTL06_NO_CMD_INIT 8 +#define BM_DRAM_CTL06_NO_CMD_INIT 0x100 +#define BF_DRAM_CTL06_NO_CMD_INIT(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL06_NO_CMD_INIT(v) BM_DRAM_CTL06_NO_CMD_INIT +#define BF_DRAM_CTL06_NO_CMD_INIT_V(e) BF_DRAM_CTL06_NO_CMD_INIT(BV_DRAM_CTL06_NO_CMD_INIT__##e) +#define BFM_DRAM_CTL06_NO_CMD_INIT_V(v) BM_DRAM_CTL06_NO_CMD_INIT +#define BP_DRAM_CTL06_RSVD1 1 +#define BM_DRAM_CTL06_RSVD1 0xfe +#define BF_DRAM_CTL06_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL06_RSVD1(v) BM_DRAM_CTL06_RSVD1 +#define BF_DRAM_CTL06_RSVD1_V(e) BF_DRAM_CTL06_RSVD1(BV_DRAM_CTL06_RSVD1__##e) +#define BFM_DRAM_CTL06_RSVD1_V(v) BM_DRAM_CTL06_RSVD1 +#define BP_DRAM_CTL06_INTRPTWRITEA 0 +#define BM_DRAM_CTL06_INTRPTWRITEA 0x1 +#define BF_DRAM_CTL06_INTRPTWRITEA(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL06_INTRPTWRITEA(v) BM_DRAM_CTL06_INTRPTWRITEA +#define BF_DRAM_CTL06_INTRPTWRITEA_V(e) BF_DRAM_CTL06_INTRPTWRITEA(BV_DRAM_CTL06_INTRPTWRITEA__##e) +#define BFM_DRAM_CTL06_INTRPTWRITEA_V(v) BM_DRAM_CTL06_INTRPTWRITEA + +#define HW_DRAM_CTL07 HW(DRAM_CTL07) +#define HWA_DRAM_CTL07 (0x800e0000 + 0x1c) +#define HWT_DRAM_CTL07 HWIO_32_RW +#define HWN_DRAM_CTL07 DRAM_CTL07 +#define HWI_DRAM_CTL07 +#define BP_DRAM_CTL07_RSVD4 25 +#define BM_DRAM_CTL07_RSVD4 0xfe000000 +#define BF_DRAM_CTL07_RSVD4(v) (((v) & 0x7f) << 25) +#define BFM_DRAM_CTL07_RSVD4(v) BM_DRAM_CTL07_RSVD4 +#define BF_DRAM_CTL07_RSVD4_V(e) BF_DRAM_CTL07_RSVD4(BV_DRAM_CTL07_RSVD4__##e) +#define BFM_DRAM_CTL07_RSVD4_V(v) BM_DRAM_CTL07_RSVD4 +#define BP_DRAM_CTL07_RW_SAME_EN 24 +#define BM_DRAM_CTL07_RW_SAME_EN 0x1000000 +#define BF_DRAM_CTL07_RW_SAME_EN(v) (((v) & 0x1) << 24) +#define BFM_DRAM_CTL07_RW_SAME_EN(v) BM_DRAM_CTL07_RW_SAME_EN +#define BF_DRAM_CTL07_RW_SAME_EN_V(e) BF_DRAM_CTL07_RW_SAME_EN(BV_DRAM_CTL07_RW_SAME_EN__##e) +#define BFM_DRAM_CTL07_RW_SAME_EN_V(v) BM_DRAM_CTL07_RW_SAME_EN +#define BP_DRAM_CTL07_RSVD3 17 +#define BM_DRAM_CTL07_RSVD3 0xfe0000 +#define BF_DRAM_CTL07_RSVD3(v) (((v) & 0x7f) << 17) +#define BFM_DRAM_CTL07_RSVD3(v) BM_DRAM_CTL07_RSVD3 +#define BF_DRAM_CTL07_RSVD3_V(e) BF_DRAM_CTL07_RSVD3(BV_DRAM_CTL07_RSVD3__##e) +#define BFM_DRAM_CTL07_RSVD3_V(v) BM_DRAM_CTL07_RSVD3 +#define BP_DRAM_CTL07_REG_DIMM_ENABLE 16 +#define BM_DRAM_CTL07_REG_DIMM_ENABLE 0x10000 +#define BF_DRAM_CTL07_REG_DIMM_ENABLE(v) (((v) & 0x1) << 16) +#define BFM_DRAM_CTL07_REG_DIMM_ENABLE(v) BM_DRAM_CTL07_REG_DIMM_ENABLE +#define BF_DRAM_CTL07_REG_DIMM_ENABLE_V(e) BF_DRAM_CTL07_REG_DIMM_ENABLE(BV_DRAM_CTL07_REG_DIMM_ENABLE__##e) +#define BFM_DRAM_CTL07_REG_DIMM_ENABLE_V(v) BM_DRAM_CTL07_REG_DIMM_ENABLE +#define BP_DRAM_CTL07_RSVD2 9 +#define BM_DRAM_CTL07_RSVD2 0xfe00 +#define BF_DRAM_CTL07_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL07_RSVD2(v) BM_DRAM_CTL07_RSVD2 +#define BF_DRAM_CTL07_RSVD2_V(e) BF_DRAM_CTL07_RSVD2(BV_DRAM_CTL07_RSVD2__##e) +#define BFM_DRAM_CTL07_RSVD2_V(v) BM_DRAM_CTL07_RSVD2 +#define BP_DRAM_CTL07_RD2RD_TURN 8 +#define BM_DRAM_CTL07_RD2RD_TURN 0x100 +#define BF_DRAM_CTL07_RD2RD_TURN(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL07_RD2RD_TURN(v) BM_DRAM_CTL07_RD2RD_TURN +#define BF_DRAM_CTL07_RD2RD_TURN_V(e) BF_DRAM_CTL07_RD2RD_TURN(BV_DRAM_CTL07_RD2RD_TURN__##e) +#define BFM_DRAM_CTL07_RD2RD_TURN_V(v) BM_DRAM_CTL07_RD2RD_TURN +#define BP_DRAM_CTL07_RSVD1 1 +#define BM_DRAM_CTL07_RSVD1 0xfe +#define BF_DRAM_CTL07_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL07_RSVD1(v) BM_DRAM_CTL07_RSVD1 +#define BF_DRAM_CTL07_RSVD1_V(e) BF_DRAM_CTL07_RSVD1(BV_DRAM_CTL07_RSVD1__##e) +#define BFM_DRAM_CTL07_RSVD1_V(v) BM_DRAM_CTL07_RSVD1 +#define BP_DRAM_CTL07_PRIORITY_EN 0 +#define BM_DRAM_CTL07_PRIORITY_EN 0x1 +#define BF_DRAM_CTL07_PRIORITY_EN(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL07_PRIORITY_EN(v) BM_DRAM_CTL07_PRIORITY_EN +#define BF_DRAM_CTL07_PRIORITY_EN_V(e) BF_DRAM_CTL07_PRIORITY_EN(BV_DRAM_CTL07_PRIORITY_EN__##e) +#define BFM_DRAM_CTL07_PRIORITY_EN_V(v) BM_DRAM_CTL07_PRIORITY_EN + +#define HW_DRAM_CTL08 HW(DRAM_CTL08) +#define HWA_DRAM_CTL08 (0x800e0000 + 0x20) +#define HWT_DRAM_CTL08 HWIO_32_RW +#define HWN_DRAM_CTL08 DRAM_CTL08 +#define HWI_DRAM_CTL08 +#define BP_DRAM_CTL08_RSVD4 25 +#define BM_DRAM_CTL08_RSVD4 0xfe000000 +#define BF_DRAM_CTL08_RSVD4(v) (((v) & 0x7f) << 25) +#define BFM_DRAM_CTL08_RSVD4(v) BM_DRAM_CTL08_RSVD4 +#define BF_DRAM_CTL08_RSVD4_V(e) BF_DRAM_CTL08_RSVD4(BV_DRAM_CTL08_RSVD4__##e) +#define BFM_DRAM_CTL08_RSVD4_V(v) BM_DRAM_CTL08_RSVD4 +#define BP_DRAM_CTL08_TRAS_LOCKOUT 24 +#define BM_DRAM_CTL08_TRAS_LOCKOUT 0x1000000 +#define BF_DRAM_CTL08_TRAS_LOCKOUT(v) (((v) & 0x1) << 24) +#define BFM_DRAM_CTL08_TRAS_LOCKOUT(v) BM_DRAM_CTL08_TRAS_LOCKOUT +#define BF_DRAM_CTL08_TRAS_LOCKOUT_V(e) BF_DRAM_CTL08_TRAS_LOCKOUT(BV_DRAM_CTL08_TRAS_LOCKOUT__##e) +#define BFM_DRAM_CTL08_TRAS_LOCKOUT_V(v) BM_DRAM_CTL08_TRAS_LOCKOUT +#define BP_DRAM_CTL08_RSVD3 17 +#define BM_DRAM_CTL08_RSVD3 0xfe0000 +#define BF_DRAM_CTL08_RSVD3(v) (((v) & 0x7f) << 17) +#define BFM_DRAM_CTL08_RSVD3(v) BM_DRAM_CTL08_RSVD3 +#define BF_DRAM_CTL08_RSVD3_V(e) BF_DRAM_CTL08_RSVD3(BV_DRAM_CTL08_RSVD3__##e) +#define BFM_DRAM_CTL08_RSVD3_V(v) BM_DRAM_CTL08_RSVD3 +#define BP_DRAM_CTL08_START 16 +#define BM_DRAM_CTL08_START 0x10000 +#define BF_DRAM_CTL08_START(v) (((v) & 0x1) << 16) +#define BFM_DRAM_CTL08_START(v) BM_DRAM_CTL08_START +#define BF_DRAM_CTL08_START_V(e) BF_DRAM_CTL08_START(BV_DRAM_CTL08_START__##e) +#define BFM_DRAM_CTL08_START_V(v) BM_DRAM_CTL08_START +#define BP_DRAM_CTL08_RSVD2 9 +#define BM_DRAM_CTL08_RSVD2 0xfe00 +#define BF_DRAM_CTL08_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL08_RSVD2(v) BM_DRAM_CTL08_RSVD2 +#define BF_DRAM_CTL08_RSVD2_V(e) BF_DRAM_CTL08_RSVD2(BV_DRAM_CTL08_RSVD2__##e) +#define BFM_DRAM_CTL08_RSVD2_V(v) BM_DRAM_CTL08_RSVD2 +#define BP_DRAM_CTL08_SREFRESH 8 +#define BM_DRAM_CTL08_SREFRESH 0x100 +#define BF_DRAM_CTL08_SREFRESH(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL08_SREFRESH(v) BM_DRAM_CTL08_SREFRESH +#define BF_DRAM_CTL08_SREFRESH_V(e) BF_DRAM_CTL08_SREFRESH(BV_DRAM_CTL08_SREFRESH__##e) +#define BFM_DRAM_CTL08_SREFRESH_V(v) BM_DRAM_CTL08_SREFRESH +#define BP_DRAM_CTL08_RSVD1 1 +#define BM_DRAM_CTL08_RSVD1 0xfe +#define BF_DRAM_CTL08_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL08_RSVD1(v) BM_DRAM_CTL08_RSVD1 +#define BF_DRAM_CTL08_RSVD1_V(e) BF_DRAM_CTL08_RSVD1(BV_DRAM_CTL08_RSVD1__##e) +#define BFM_DRAM_CTL08_RSVD1_V(v) BM_DRAM_CTL08_RSVD1 +#define BP_DRAM_CTL08_SDR_MODE 0 +#define BM_DRAM_CTL08_SDR_MODE 0x1 +#define BF_DRAM_CTL08_SDR_MODE(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL08_SDR_MODE(v) BM_DRAM_CTL08_SDR_MODE +#define BF_DRAM_CTL08_SDR_MODE_V(e) BF_DRAM_CTL08_SDR_MODE(BV_DRAM_CTL08_SDR_MODE__##e) +#define BFM_DRAM_CTL08_SDR_MODE_V(v) BM_DRAM_CTL08_SDR_MODE + +#define HW_DRAM_CTL09 HW(DRAM_CTL09) +#define HWA_DRAM_CTL09 (0x800e0000 + 0x24) +#define HWT_DRAM_CTL09 HWIO_32_RW +#define HWN_DRAM_CTL09 DRAM_CTL09 +#define HWI_DRAM_CTL09 +#define BP_DRAM_CTL09_RSVD4 26 +#define BM_DRAM_CTL09_RSVD4 0xfc000000 +#define BF_DRAM_CTL09_RSVD4(v) (((v) & 0x3f) << 26) +#define BFM_DRAM_CTL09_RSVD4(v) BM_DRAM_CTL09_RSVD4 +#define BF_DRAM_CTL09_RSVD4_V(e) BF_DRAM_CTL09_RSVD4(BV_DRAM_CTL09_RSVD4__##e) +#define BFM_DRAM_CTL09_RSVD4_V(v) BM_DRAM_CTL09_RSVD4 +#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE 24 +#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE 0x3000000 +#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v) (((v) & 0x3) << 24) +#define BFM_DRAM_CTL09_OUT_OF_RANGE_TYPE(v) BM_DRAM_CTL09_OUT_OF_RANGE_TYPE +#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE_V(e) BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(BV_DRAM_CTL09_OUT_OF_RANGE_TYPE__##e) +#define BFM_DRAM_CTL09_OUT_OF_RANGE_TYPE_V(v) BM_DRAM_CTL09_OUT_OF_RANGE_TYPE +#define BP_DRAM_CTL09_RSVD3 18 +#define BM_DRAM_CTL09_RSVD3 0xfc0000 +#define BF_DRAM_CTL09_RSVD3(v) (((v) & 0x3f) << 18) +#define BFM_DRAM_CTL09_RSVD3(v) BM_DRAM_CTL09_RSVD3 +#define BF_DRAM_CTL09_RSVD3_V(e) BF_DRAM_CTL09_RSVD3(BV_DRAM_CTL09_RSVD3__##e) +#define BFM_DRAM_CTL09_RSVD3_V(v) BM_DRAM_CTL09_RSVD3 +#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 16 +#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 0x30000 +#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) (((v) & 0x3) << 16) +#define BFM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID +#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID_V(e) BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(BV_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID__##e) +#define BFM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID_V(v) BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID +#define BP_DRAM_CTL09_RSVD2 9 +#define BM_DRAM_CTL09_RSVD2 0xfe00 +#define BF_DRAM_CTL09_RSVD2(v) (((v) & 0x7f) << 9) +#define BFM_DRAM_CTL09_RSVD2(v) BM_DRAM_CTL09_RSVD2 +#define BF_DRAM_CTL09_RSVD2_V(e) BF_DRAM_CTL09_RSVD2(BV_DRAM_CTL09_RSVD2__##e) +#define BFM_DRAM_CTL09_RSVD2_V(v) BM_DRAM_CTL09_RSVD2 +#define BP_DRAM_CTL09_WRITE_MODEREG 8 +#define BM_DRAM_CTL09_WRITE_MODEREG 0x100 +#define BF_DRAM_CTL09_WRITE_MODEREG(v) (((v) & 0x1) << 8) +#define BFM_DRAM_CTL09_WRITE_MODEREG(v) BM_DRAM_CTL09_WRITE_MODEREG +#define BF_DRAM_CTL09_WRITE_MODEREG_V(e) BF_DRAM_CTL09_WRITE_MODEREG(BV_DRAM_CTL09_WRITE_MODEREG__##e) +#define BFM_DRAM_CTL09_WRITE_MODEREG_V(v) BM_DRAM_CTL09_WRITE_MODEREG +#define BP_DRAM_CTL09_RSVD1 1 +#define BM_DRAM_CTL09_RSVD1 0xfe +#define BF_DRAM_CTL09_RSVD1(v) (((v) & 0x7f) << 1) +#define BFM_DRAM_CTL09_RSVD1(v) BM_DRAM_CTL09_RSVD1 +#define BF_DRAM_CTL09_RSVD1_V(e) BF_DRAM_CTL09_RSVD1(BV_DRAM_CTL09_RSVD1__##e) +#define BFM_DRAM_CTL09_RSVD1_V(v) BM_DRAM_CTL09_RSVD1 +#define BP_DRAM_CTL09_WRITEINTERP 0 +#define BM_DRAM_CTL09_WRITEINTERP 0x1 +#define BF_DRAM_CTL09_WRITEINTERP(v) (((v) & 0x1) << 0) +#define BFM_DRAM_CTL09_WRITEINTERP(v) BM_DRAM_CTL09_WRITEINTERP +#define BF_DRAM_CTL09_WRITEINTERP_V(e) BF_DRAM_CTL09_WRITEINTERP(BV_DRAM_CTL09_WRITEINTERP__##e) +#define BFM_DRAM_CTL09_WRITEINTERP_V(v) BM_DRAM_CTL09_WRITEINTERP + +#define HW_DRAM_CTL10 HW(DRAM_CTL10) +#define HWA_DRAM_CTL10 (0x800e0000 + 0x28) +#define HWT_DRAM_CTL10 HWIO_32_RW +#define HWN_DRAM_CTL10 DRAM_CTL10 +#define HWI_DRAM_CTL10 +#define BP_DRAM_CTL10_RSVD4 27 +#define BM_DRAM_CTL10_RSVD4 0xf8000000 +#define BF_DRAM_CTL10_RSVD4(v) (((v) & 0x1f) << 27) +#define BFM_DRAM_CTL10_RSVD4(v) BM_DRAM_CTL10_RSVD4 +#define BF_DRAM_CTL10_RSVD4_V(e) BF_DRAM_CTL10_RSVD4(BV_DRAM_CTL10_RSVD4__##e) +#define BFM_DRAM_CTL10_RSVD4_V(v) BM_DRAM_CTL10_RSVD4 +#define BP_DRAM_CTL10_AGE_COUNT 24 +#define BM_DRAM_CTL10_AGE_COUNT 0x7000000 +#define BF_DRAM_CTL10_AGE_COUNT(v) (((v) & 0x7) << 24) +#define BFM_DRAM_CTL10_AGE_COUNT(v) BM_DRAM_CTL10_AGE_COUNT +#define BF_DRAM_CTL10_AGE_COUNT_V(e) BF_DRAM_CTL10_AGE_COUNT(BV_DRAM_CTL10_AGE_COUNT__##e) +#define BFM_DRAM_CTL10_AGE_COUNT_V(v) BM_DRAM_CTL10_AGE_COUNT +#define BP_DRAM_CTL10_RSVD3 19 +#define BM_DRAM_CTL10_RSVD3 0xf80000 +#define BF_DRAM_CTL10_RSVD3(v) (((v) & 0x1f) << 19) +#define BFM_DRAM_CTL10_RSVD3(v) BM_DRAM_CTL10_RSVD3 +#define BF_DRAM_CTL10_RSVD3_V(e) BF_DRAM_CTL10_RSVD3(BV_DRAM_CTL10_RSVD3__##e) +#define BFM_DRAM_CTL10_RSVD3_V(v) BM_DRAM_CTL10_RSVD3 +#define BP_DRAM_CTL10_ADDR_PINS 16 +#define BM_DRAM_CTL10_ADDR_PINS 0x70000 +#define BF_DRAM_CTL10_ADDR_PINS(v) (((v) & 0x7) << 16) +#define BFM_DRAM_CTL10_ADDR_PINS(v) BM_DRAM_CTL10_ADDR_PINS +#define BF_DRAM_CTL10_ADDR_PINS_V(e) BF_DRAM_CTL10_ADDR_PINS(BV_DRAM_CTL10_ADDR_PINS__##e) +#define BFM_DRAM_CTL10_ADDR_PINS_V(v) BM_DRAM_CTL10_ADDR_PINS +#define BP_DRAM_CTL10_RSVD2 10 +#define BM_DRAM_CTL10_RSVD2 0xfc00 +#define BF_DRAM_CTL10_RSVD2(v) (((v) & 0x3f) << 10) +#define BFM_DRAM_CTL10_RSVD2(v) BM_DRAM_CTL10_RSVD2 +#define BF_DRAM_CTL10_RSVD2_V(e) BF_DRAM_CTL10_RSVD2(BV_DRAM_CTL10_RSVD2__##e) +#define BFM_DRAM_CTL10_RSVD2_V(v) BM_DRAM_CTL10_RSVD2 +#define BP_DRAM_CTL10_TEMRS 8 +#define BM_DRAM_CTL10_TEMRS 0x300 +#define BF_DRAM_CTL10_TEMRS(v) (((v) & 0x3) << 8) +#define BFM_DRAM_CTL10_TEMRS(v) BM_DRAM_CTL10_TEMRS +#define BF_DRAM_CTL10_TEMRS_V(e) BF_DRAM_CTL10_TEMRS(BV_DRAM_CTL10_TEMRS__##e) +#define BFM_DRAM_CTL10_TEMRS_V(v) BM_DRAM_CTL10_TEMRS +#define BP_DRAM_CTL10_RSVD1 2 +#define BM_DRAM_CTL10_RSVD1 0xfc +#define BF_DRAM_CTL10_RSVD1(v) (((v) & 0x3f) << 2) +#define BFM_DRAM_CTL10_RSVD1(v) BM_DRAM_CTL10_RSVD1 +#define BF_DRAM_CTL10_RSVD1_V(e) BF_DRAM_CTL10_RSVD1(BV_DRAM_CTL10_RSVD1__##e) +#define BFM_DRAM_CTL10_RSVD1_V(v) BM_DRAM_CTL10_RSVD1 +#define BP_DRAM_CTL10_Q_FULLNESS 0 +#define BM_DRAM_CTL10_Q_FULLNESS 0x3 +#define BF_DRAM_CTL10_Q_FULLNESS(v) (((v) & 0x3) << 0) +#define BFM_DRAM_CTL10_Q_FULLNESS(v) BM_DRAM_CTL10_Q_FULLNESS +#define BF_DRAM_CTL10_Q_FULLNESS_V(e) BF_DRAM_CTL10_Q_FULLNESS(BV_DRAM_CTL10_Q_FULLNESS__##e) +#define BFM_DRAM_CTL10_Q_FULLNESS_V(v) BM_DRAM_CTL10_Q_FULLNESS + +#define HW_DRAM_CTL11 HW(DRAM_CTL11) +#define HWA_DRAM_CTL11 (0x800e0000 + 0x2c) +#define HWT_DRAM_CTL11 HWIO_32_RW +#define HWN_DRAM_CTL11 DRAM_CTL11 +#define HWI_DRAM_CTL11 +#define BP_DRAM_CTL11_RSVD4 27 +#define BM_DRAM_CTL11_RSVD4 0xf8000000 +#define BF_DRAM_CTL11_RSVD4(v) (((v) & 0x1f) << 27) +#define BFM_DRAM_CTL11_RSVD4(v) BM_DRAM_CTL11_RSVD4 +#define BF_DRAM_CTL11_RSVD4_V(e) BF_DRAM_CTL11_RSVD4(BV_DRAM_CTL11_RSVD4__##e) +#define BFM_DRAM_CTL11_RSVD4_V(v) BM_DRAM_CTL11_RSVD4 +#define BP_DRAM_CTL11_MAX_CS_REG 24 +#define BM_DRAM_CTL11_MAX_CS_REG 0x7000000 +#define BF_DRAM_CTL11_MAX_CS_REG(v) (((v) & 0x7) << 24) +#define BFM_DRAM_CTL11_MAX_CS_REG(v) BM_DRAM_CTL11_MAX_CS_REG +#define BF_DRAM_CTL11_MAX_CS_REG_V(e) BF_DRAM_CTL11_MAX_CS_REG(BV_DRAM_CTL11_MAX_CS_REG__##e) +#define BFM_DRAM_CTL11_MAX_CS_REG_V(v) BM_DRAM_CTL11_MAX_CS_REG +#define BP_DRAM_CTL11_RSVD3 19 +#define BM_DRAM_CTL11_RSVD3 0xf80000 +#define BF_DRAM_CTL11_RSVD3(v) (((v) & 0x1f) << 19) +#define BFM_DRAM_CTL11_RSVD3(v) BM_DRAM_CTL11_RSVD3 +#define BF_DRAM_CTL11_RSVD3_V(e) BF_DRAM_CTL11_RSVD3(BV_DRAM_CTL11_RSVD3__##e) +#define BFM_DRAM_CTL11_RSVD3_V(v) BM_DRAM_CTL11_RSVD3 +#define BP_DRAM_CTL11_COMMAND_AGE_COUNT 16 +#define BM_DRAM_CTL11_COMMAND_AGE_COUNT 0x70000 +#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v) (((v) & 0x7) << 16) +#define BFM_DRAM_CTL11_COMMAND_AGE_COUNT(v) BM_DRAM_CTL11_COMMAND_AGE_COUNT +#define BF_DRAM_CTL11_COMMAND_AGE_COUNT_V(e) BF_DRAM_CTL11_COMMAND_AGE_COUNT(BV_DRAM_CTL11_COMMAND_AGE_COUNT__##e) +#define BFM_DRAM_CTL11_COMMAND_AGE_COUNT_V(v) BM_DRAM_CTL11_COMMAND_AGE_COUNT +#define BP_DRAM_CTL11_RSVD2 11 +#define BM_DRAM_CTL11_RSVD2 0xf800 +#define BF_DRAM_CTL11_RSVD2(v) (((v) & 0x1f) << 11) +#define BFM_DRAM_CTL11_RSVD2(v) BM_DRAM_CTL11_RSVD2 +#define BF_DRAM_CTL11_RSVD2_V(e) BF_DRAM_CTL11_RSVD2(BV_DRAM_CTL11_RSVD2__##e) +#define BFM_DRAM_CTL11_RSVD2_V(v) BM_DRAM_CTL11_RSVD2 +#define BP_DRAM_CTL11_COLUMN_SIZE 8 +#define BM_DRAM_CTL11_COLUMN_SIZE 0x700 +#define BF_DRAM_CTL11_COLUMN_SIZE(v) (((v) & 0x7) << 8) +#define BFM_DRAM_CTL11_COLUMN_SIZE(v) BM_DRAM_CTL11_COLUMN_SIZE +#define BF_DRAM_CTL11_COLUMN_SIZE_V(e) BF_DRAM_CTL11_COLUMN_SIZE(BV_DRAM_CTL11_COLUMN_SIZE__##e) +#define BFM_DRAM_CTL11_COLUMN_SIZE_V(v) BM_DRAM_CTL11_COLUMN_SIZE +#define BP_DRAM_CTL11_RSVD1 3 +#define BM_DRAM_CTL11_RSVD1 0xf8 +#define BF_DRAM_CTL11_RSVD1(v) (((v) & 0x1f) << 3) +#define BFM_DRAM_CTL11_RSVD1(v) BM_DRAM_CTL11_RSVD1 +#define BF_DRAM_CTL11_RSVD1_V(e) BF_DRAM_CTL11_RSVD1(BV_DRAM_CTL11_RSVD1__##e) +#define BFM_DRAM_CTL11_RSVD1_V(v) BM_DRAM_CTL11_RSVD1 +#define BP_DRAM_CTL11_CASLAT 0 +#define BM_DRAM_CTL11_CASLAT 0x7 +#define BF_DRAM_CTL11_CASLAT(v) (((v) & 0x7) << 0) +#define BFM_DRAM_CTL11_CASLAT(v) BM_DRAM_CTL11_CASLAT +#define BF_DRAM_CTL11_CASLAT_V(e) BF_DRAM_CTL11_CASLAT(BV_DRAM_CTL11_CASLAT__##e) +#define BFM_DRAM_CTL11_CASLAT_V(v) BM_DRAM_CTL11_CASLAT + +#define HW_DRAM_CTL12 HW(DRAM_CTL12) +#define HWA_DRAM_CTL12 (0x800e0000 + 0x30) +#define HWT_DRAM_CTL12 HWIO_32_RW +#define HWN_DRAM_CTL12 DRAM_CTL12 +#define HWI_DRAM_CTL12 +#define BP_DRAM_CTL12_RSVD3 27 +#define BM_DRAM_CTL12_RSVD3 0xf8000000 +#define BF_DRAM_CTL12_RSVD3(v) (((v) & 0x1f) << 27) +#define BFM_DRAM_CTL12_RSVD3(v) BM_DRAM_CTL12_RSVD3 +#define BF_DRAM_CTL12_RSVD3_V(e) BF_DRAM_CTL12_RSVD3(BV_DRAM_CTL12_RSVD3__##e) +#define BFM_DRAM_CTL12_RSVD3_V(v) BM_DRAM_CTL12_RSVD3 +#define BP_DRAM_CTL12_TWR_INT 24 +#define BM_DRAM_CTL12_TWR_INT 0x7000000 +#define BF_DRAM_CTL12_TWR_INT(v) (((v) & 0x7) << 24) +#define BFM_DRAM_CTL12_TWR_INT(v) BM_DRAM_CTL12_TWR_INT +#define BF_DRAM_CTL12_TWR_INT_V(e) BF_DRAM_CTL12_TWR_INT(BV_DRAM_CTL12_TWR_INT__##e) +#define BFM_DRAM_CTL12_TWR_INT_V(v) BM_DRAM_CTL12_TWR_INT +#define BP_DRAM_CTL12_RSVD2 19 +#define BM_DRAM_CTL12_RSVD2 0xf80000 +#define BF_DRAM_CTL12_RSVD2(v) (((v) & 0x1f) << 19) +#define BFM_DRAM_CTL12_RSVD2(v) BM_DRAM_CTL12_RSVD2 +#define BF_DRAM_CTL12_RSVD2_V(e) BF_DRAM_CTL12_RSVD2(BV_DRAM_CTL12_RSVD2__##e) +#define BFM_DRAM_CTL12_RSVD2_V(v) BM_DRAM_CTL12_RSVD2 +#define BP_DRAM_CTL12_TRRD 16 +#define BM_DRAM_CTL12_TRRD 0x70000 +#define BF_DRAM_CTL12_TRRD(v) (((v) & 0x7) << 16) +#define BFM_DRAM_CTL12_TRRD(v) BM_DRAM_CTL12_TRRD +#define BF_DRAM_CTL12_TRRD_V(e) BF_DRAM_CTL12_TRRD(BV_DRAM_CTL12_TRRD__##e) +#define BFM_DRAM_CTL12_TRRD_V(v) BM_DRAM_CTL12_TRRD +#define BP_DRAM_CTL12_OBSOLETE 8 +#define BM_DRAM_CTL12_OBSOLETE 0xff00 +#define BF_DRAM_CTL12_OBSOLETE(v) (((v) & 0xff) << 8) +#define BFM_DRAM_CTL12_OBSOLETE(v) BM_DRAM_CTL12_OBSOLETE +#define BF_DRAM_CTL12_OBSOLETE_V(e) BF_DRAM_CTL12_OBSOLETE(BV_DRAM_CTL12_OBSOLETE__##e) +#define BFM_DRAM_CTL12_OBSOLETE_V(v) BM_DRAM_CTL12_OBSOLETE +#define BP_DRAM_CTL12_RSVD1 3 +#define BM_DRAM_CTL12_RSVD1 0xf8 +#define BF_DRAM_CTL12_RSVD1(v) (((v) & 0x1f) << 3) +#define BFM_DRAM_CTL12_RSVD1(v) BM_DRAM_CTL12_RSVD1 +#define BF_DRAM_CTL12_RSVD1_V(e) BF_DRAM_CTL12_RSVD1(BV_DRAM_CTL12_RSVD1__##e) +#define BFM_DRAM_CTL12_RSVD1_V(v) BM_DRAM_CTL12_RSVD1 +#define BP_DRAM_CTL12_TCKE 0 +#define BM_DRAM_CTL12_TCKE 0x7 +#define BF_DRAM_CTL12_TCKE(v) (((v) & 0x7) << 0) +#define BFM_DRAM_CTL12_TCKE(v) BM_DRAM_CTL12_TCKE +#define BF_DRAM_CTL12_TCKE_V(e) BF_DRAM_CTL12_TCKE(BV_DRAM_CTL12_TCKE__##e) +#define BFM_DRAM_CTL12_TCKE_V(v) BM_DRAM_CTL12_TCKE + +#define HW_DRAM_CTL13 HW(DRAM_CTL13) +#define HWA_DRAM_CTL13 (0x800e0000 + 0x34) +#define HWT_DRAM_CTL13 HWIO_32_RW +#define HWN_DRAM_CTL13 DRAM_CTL13 +#define HWI_DRAM_CTL13 +#define BP_DRAM_CTL13_RSVD4 28 +#define BM_DRAM_CTL13_RSVD4 0xf0000000 +#define BF_DRAM_CTL13_RSVD4(v) (((v) & 0xf) << 28) +#define BFM_DRAM_CTL13_RSVD4(v) BM_DRAM_CTL13_RSVD4 +#define BF_DRAM_CTL13_RSVD4_V(e) BF_DRAM_CTL13_RSVD4(BV_DRAM_CTL13_RSVD4__##e) +#define BFM_DRAM_CTL13_RSVD4_V(v) BM_DRAM_CTL13_RSVD4 +#define BP_DRAM_CTL13_CASLAT_LIN_GATE 24 +#define BM_DRAM_CTL13_CASLAT_LIN_GATE 0xf000000 +#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v) (((v) & 0xf) << 24) +#define BFM_DRAM_CTL13_CASLAT_LIN_GATE(v) BM_DRAM_CTL13_CASLAT_LIN_GATE +#define BF_DRAM_CTL13_CASLAT_LIN_GATE_V(e) BF_DRAM_CTL13_CASLAT_LIN_GATE(BV_DRAM_CTL13_CASLAT_LIN_GATE__##e) +#define BFM_DRAM_CTL13_CASLAT_LIN_GATE_V(v) BM_DRAM_CTL13_CASLAT_LIN_GATE +#define BP_DRAM_CTL13_RSVD3 20 +#define BM_DRAM_CTL13_RSVD3 0xf00000 +#define BF_DRAM_CTL13_RSVD3(v) (((v) & 0xf) << 20) +#define BFM_DRAM_CTL13_RSVD3(v) BM_DRAM_CTL13_RSVD3 +#define BF_DRAM_CTL13_RSVD3_V(e) BF_DRAM_CTL13_RSVD3(BV_DRAM_CTL13_RSVD3__##e) +#define BFM_DRAM_CTL13_RSVD3_V(v) BM_DRAM_CTL13_RSVD3 +#define BP_DRAM_CTL13_CASLAT_LIN 16 +#define BM_DRAM_CTL13_CASLAT_LIN 0xf0000 +#define BF_DRAM_CTL13_CASLAT_LIN(v) (((v) & 0xf) << 16) +#define BFM_DRAM_CTL13_CASLAT_LIN(v) BM_DRAM_CTL13_CASLAT_LIN +#define BF_DRAM_CTL13_CASLAT_LIN_V(e) BF_DRAM_CTL13_CASLAT_LIN(BV_DRAM_CTL13_CASLAT_LIN__##e) +#define BFM_DRAM_CTL13_CASLAT_LIN_V(v) BM_DRAM_CTL13_CASLAT_LIN +#define BP_DRAM_CTL13_RSVD2 12 +#define BM_DRAM_CTL13_RSVD2 0xf000 +#define BF_DRAM_CTL13_RSVD2(v) (((v) & 0xf) << 12) +#define BFM_DRAM_CTL13_RSVD2(v) BM_DRAM_CTL13_RSVD2 +#define BF_DRAM_CTL13_RSVD2_V(e) BF_DRAM_CTL13_RSVD2(BV_DRAM_CTL13_RSVD2__##e) +#define BFM_DRAM_CTL13_RSVD2_V(v) BM_DRAM_CTL13_RSVD2 +#define BP_DRAM_CTL13_APREBIT 8 +#define BM_DRAM_CTL13_APREBIT 0xf00 +#define BF_DRAM_CTL13_APREBIT(v) (((v) & 0xf) << 8) +#define BFM_DRAM_CTL13_APREBIT(v) BM_DRAM_CTL13_APREBIT +#define BF_DRAM_CTL13_APREBIT_V(e) BF_DRAM_CTL13_APREBIT(BV_DRAM_CTL13_APREBIT__##e) +#define BFM_DRAM_CTL13_APREBIT_V(v) BM_DRAM_CTL13_APREBIT +#define BP_DRAM_CTL13_RSVD1 3 +#define BM_DRAM_CTL13_RSVD1 0xf8 +#define BF_DRAM_CTL13_RSVD1(v) (((v) & 0x1f) << 3) +#define BFM_DRAM_CTL13_RSVD1(v) BM_DRAM_CTL13_RSVD1 +#define BF_DRAM_CTL13_RSVD1_V(e) BF_DRAM_CTL13_RSVD1(BV_DRAM_CTL13_RSVD1__##e) +#define BFM_DRAM_CTL13_RSVD1_V(v) BM_DRAM_CTL13_RSVD1 +#define BP_DRAM_CTL13_TWTR 0 +#define BM_DRAM_CTL13_TWTR 0x7 +#define BF_DRAM_CTL13_TWTR(v) (((v) & 0x7) << 0) +#define BFM_DRAM_CTL13_TWTR(v) BM_DRAM_CTL13_TWTR +#define BF_DRAM_CTL13_TWTR_V(e) BF_DRAM_CTL13_TWTR(BV_DRAM_CTL13_TWTR__##e) +#define BFM_DRAM_CTL13_TWTR_V(v) BM_DRAM_CTL13_TWTR + +#define HW_DRAM_CTL14 HW(DRAM_CTL14) +#define HWA_DRAM_CTL14 (0x800e0000 + 0x38) +#define HWT_DRAM_CTL14 HWIO_32_RW +#define HWN_DRAM_CTL14 DRAM_CTL14 +#define HWI_DRAM_CTL14 +#define BP_DRAM_CTL14_RSVD4 28 +#define BM_DRAM_CTL14_RSVD4 0xf0000000 +#define BF_DRAM_CTL14_RSVD4(v) (((v) & 0xf) << 28) +#define BFM_DRAM_CTL14_RSVD4(v) BM_DRAM_CTL14_RSVD4 +#define BF_DRAM_CTL14_RSVD4_V(e) BF_DRAM_CTL14_RSVD4(BV_DRAM_CTL14_RSVD4__##e) +#define BFM_DRAM_CTL14_RSVD4_V(v) BM_DRAM_CTL14_RSVD4 +#define BP_DRAM_CTL14_MAX_COL_REG 24 +#define BM_DRAM_CTL14_MAX_COL_REG 0xf000000 +#define BF_DRAM_CTL14_MAX_COL_REG(v) (((v) & 0xf) << 24) +#define BFM_DRAM_CTL14_MAX_COL_REG(v) BM_DRAM_CTL14_MAX_COL_REG +#define BF_DRAM_CTL14_MAX_COL_REG_V(e) BF_DRAM_CTL14_MAX_COL_REG(BV_DRAM_CTL14_MAX_COL_REG__##e) +#define BFM_DRAM_CTL14_MAX_COL_REG_V(v) BM_DRAM_CTL14_MAX_COL_REG +#define BP_DRAM_CTL14_RSVD3 20 +#define BM_DRAM_CTL14_RSVD3 0xf00000 +#define BF_DRAM_CTL14_RSVD3(v) (((v) & 0xf) << 20) +#define BFM_DRAM_CTL14_RSVD3(v) BM_DRAM_CTL14_RSVD3 +#define BF_DRAM_CTL14_RSVD3_V(e) BF_DRAM_CTL14_RSVD3(BV_DRAM_CTL14_RSVD3__##e) +#define BFM_DRAM_CTL14_RSVD3_V(v) BM_DRAM_CTL14_RSVD3 +#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 16 +#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 0xf0000 +#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v) (((v) & 0xf) << 16) +#define BFM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v) BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE +#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE_V(e) BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(BV_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE__##e) +#define BFM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE_V(v) BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE +#define BP_DRAM_CTL14_RSVD2 12 +#define BM_DRAM_CTL14_RSVD2 0xf000 +#define BF_DRAM_CTL14_RSVD2(v) (((v) & 0xf) << 12) +#define BFM_DRAM_CTL14_RSVD2(v) BM_DRAM_CTL14_RSVD2 +#define BF_DRAM_CTL14_RSVD2_V(e) BF_DRAM_CTL14_RSVD2(BV_DRAM_CTL14_RSVD2__##e) +#define BFM_DRAM_CTL14_RSVD2_V(v) BM_DRAM_CTL14_RSVD2 +#define BP_DRAM_CTL14_INITAREF 8 +#define BM_DRAM_CTL14_INITAREF 0xf00 +#define BF_DRAM_CTL14_INITAREF(v) (((v) & 0xf) << 8) +#define BFM_DRAM_CTL14_INITAREF(v) BM_DRAM_CTL14_INITAREF +#define BF_DRAM_CTL14_INITAREF_V(e) BF_DRAM_CTL14_INITAREF(BV_DRAM_CTL14_INITAREF__##e) +#define BFM_DRAM_CTL14_INITAREF_V(v) BM_DRAM_CTL14_INITAREF +#define BP_DRAM_CTL14_RSVD1 4 +#define BM_DRAM_CTL14_RSVD1 0xf0 +#define BF_DRAM_CTL14_RSVD1(v) (((v) & 0xf) << 4) +#define BFM_DRAM_CTL14_RSVD1(v) BM_DRAM_CTL14_RSVD1 +#define BF_DRAM_CTL14_RSVD1_V(e) BF_DRAM_CTL14_RSVD1(BV_DRAM_CTL14_RSVD1__##e) +#define BFM_DRAM_CTL14_RSVD1_V(v) BM_DRAM_CTL14_RSVD1 +#define BP_DRAM_CTL14_CS_MAP 0 +#define BM_DRAM_CTL14_CS_MAP 0xf +#define BF_DRAM_CTL14_CS_MAP(v) (((v) & 0xf) << 0) +#define BFM_DRAM_CTL14_CS_MAP(v) BM_DRAM_CTL14_CS_MAP +#define BF_DRAM_CTL14_CS_MAP_V(e) BF_DRAM_CTL14_CS_MAP(BV_DRAM_CTL14_CS_MAP__##e) +#define BFM_DRAM_CTL14_CS_MAP_V(v) BM_DRAM_CTL14_CS_MAP + +#define HW_DRAM_CTL15 HW(DRAM_CTL15) +#define HWA_DRAM_CTL15 (0x800e0000 + 0x3c) +#define HWT_DRAM_CTL15 HWIO_32_RW +#define HWN_DRAM_CTL15 DRAM_CTL15 +#define HWI_DRAM_CTL15 +#define BP_DRAM_CTL15_RSVD4 28 +#define BM_DRAM_CTL15_RSVD4 0xf0000000 +#define BF_DRAM_CTL15_RSVD4(v) (((v) & 0xf) << 28) +#define BFM_DRAM_CTL15_RSVD4(v) BM_DRAM_CTL15_RSVD4 +#define BF_DRAM_CTL15_RSVD4_V(e) BF_DRAM_CTL15_RSVD4(BV_DRAM_CTL15_RSVD4__##e) +#define BFM_DRAM_CTL15_RSVD4_V(v) BM_DRAM_CTL15_RSVD4 +#define BP_DRAM_CTL15_TRP 24 +#define BM_DRAM_CTL15_TRP 0xf000000 +#define BF_DRAM_CTL15_TRP(v) (((v) & 0xf) << 24) +#define BFM_DRAM_CTL15_TRP(v) BM_DRAM_CTL15_TRP +#define BF_DRAM_CTL15_TRP_V(e) BF_DRAM_CTL15_TRP(BV_DRAM_CTL15_TRP__##e) +#define BFM_DRAM_CTL15_TRP_V(v) BM_DRAM_CTL15_TRP +#define BP_DRAM_CTL15_RSVD3 20 +#define BM_DRAM_CTL15_RSVD3 0xf00000 +#define BF_DRAM_CTL15_RSVD3(v) (((v) & 0xf) << 20) +#define BFM_DRAM_CTL15_RSVD3(v) BM_DRAM_CTL15_RSVD3 +#define BF_DRAM_CTL15_RSVD3_V(e) BF_DRAM_CTL15_RSVD3(BV_DRAM_CTL15_RSVD3__##e) +#define BFM_DRAM_CTL15_RSVD3_V(v) BM_DRAM_CTL15_RSVD3 +#define BP_DRAM_CTL15_TDAL 16 +#define BM_DRAM_CTL15_TDAL 0xf0000 +#define BF_DRAM_CTL15_TDAL(v) (((v) & 0xf) << 16) +#define BFM_DRAM_CTL15_TDAL(v) BM_DRAM_CTL15_TDAL +#define BF_DRAM_CTL15_TDAL_V(e) BF_DRAM_CTL15_TDAL(BV_DRAM_CTL15_TDAL__##e) +#define BFM_DRAM_CTL15_TDAL_V(v) BM_DRAM_CTL15_TDAL +#define BP_DRAM_CTL15_RSVD2 12 +#define BM_DRAM_CTL15_RSVD2 0xf000 +#define BF_DRAM_CTL15_RSVD2(v) (((v) & 0xf) << 12) +#define BFM_DRAM_CTL15_RSVD2(v) BM_DRAM_CTL15_RSVD2 +#define BF_DRAM_CTL15_RSVD2_V(e) BF_DRAM_CTL15_RSVD2(BV_DRAM_CTL15_RSVD2__##e) +#define BFM_DRAM_CTL15_RSVD2_V(v) BM_DRAM_CTL15_RSVD2 +#define BP_DRAM_CTL15_PORT_BUSY 8 +#define BM_DRAM_CTL15_PORT_BUSY 0xf00 +#define BF_DRAM_CTL15_PORT_BUSY(v) (((v) & 0xf) << 8) +#define BFM_DRAM_CTL15_PORT_BUSY(v) BM_DRAM_CTL15_PORT_BUSY +#define BF_DRAM_CTL15_PORT_BUSY_V(e) BF_DRAM_CTL15_PORT_BUSY(BV_DRAM_CTL15_PORT_BUSY__##e) +#define BFM_DRAM_CTL15_PORT_BUSY_V(v) BM_DRAM_CTL15_PORT_BUSY +#define BP_DRAM_CTL15_RSVD1 4 +#define BM_DRAM_CTL15_RSVD1 0xf0 +#define BF_DRAM_CTL15_RSVD1(v) (((v) & 0xf) << 4) +#define BFM_DRAM_CTL15_RSVD1(v) BM_DRAM_CTL15_RSVD1 +#define BF_DRAM_CTL15_RSVD1_V(e) BF_DRAM_CTL15_RSVD1(BV_DRAM_CTL15_RSVD1__##e) +#define BFM_DRAM_CTL15_RSVD1_V(v) BM_DRAM_CTL15_RSVD1 +#define BP_DRAM_CTL15_MAX_ROW_REG 0 +#define BM_DRAM_CTL15_MAX_ROW_REG 0xf +#define BF_DRAM_CTL15_MAX_ROW_REG(v) (((v) & 0xf) << 0) +#define BFM_DRAM_CTL15_MAX_ROW_REG(v) BM_DRAM_CTL15_MAX_ROW_REG +#define BF_DRAM_CTL15_MAX_ROW_REG_V(e) BF_DRAM_CTL15_MAX_ROW_REG(BV_DRAM_CTL15_MAX_ROW_REG__##e) +#define BFM_DRAM_CTL15_MAX_ROW_REG_V(v) BM_DRAM_CTL15_MAX_ROW_REG + +#define HW_DRAM_CTL16 HW(DRAM_CTL16) +#define HWA_DRAM_CTL16 (0x800e0000 + 0x40) +#define HWT_DRAM_CTL16 HWIO_32_RW +#define HWN_DRAM_CTL16 DRAM_CTL16 +#define HWI_DRAM_CTL16 +#define BP_DRAM_CTL16_RSVD4 29 +#define BM_DRAM_CTL16_RSVD4 0xe0000000 +#define BF_DRAM_CTL16_RSVD4(v) (((v) & 0x7) << 29) +#define BFM_DRAM_CTL16_RSVD4(v) BM_DRAM_CTL16_RSVD4 +#define BF_DRAM_CTL16_RSVD4_V(e) BF_DRAM_CTL16_RSVD4(BV_DRAM_CTL16_RSVD4__##e) +#define BFM_DRAM_CTL16_RSVD4_V(v) BM_DRAM_CTL16_RSVD4 +#define BP_DRAM_CTL16_TMRD 24 +#define BM_DRAM_CTL16_TMRD 0x1f000000 +#define BF_DRAM_CTL16_TMRD(v) (((v) & 0x1f) << 24) +#define BFM_DRAM_CTL16_TMRD(v) BM_DRAM_CTL16_TMRD +#define BF_DRAM_CTL16_TMRD_V(e) BF_DRAM_CTL16_TMRD(BV_DRAM_CTL16_TMRD__##e) +#define BFM_DRAM_CTL16_TMRD_V(v) BM_DRAM_CTL16_TMRD +#define BP_DRAM_CTL16_RSVD3 21 +#define BM_DRAM_CTL16_RSVD3 0xe00000 +#define BF_DRAM_CTL16_RSVD3(v) (((v) & 0x7) << 21) +#define BFM_DRAM_CTL16_RSVD3(v) BM_DRAM_CTL16_RSVD3 +#define BF_DRAM_CTL16_RSVD3_V(e) BF_DRAM_CTL16_RSVD3(BV_DRAM_CTL16_RSVD3__##e) +#define BFM_DRAM_CTL16_RSVD3_V(v) BM_DRAM_CTL16_RSVD3 +#define BP_DRAM_CTL16_LOWPOWER_CONTROL 16 +#define BM_DRAM_CTL16_LOWPOWER_CONTROL 0x1f0000 +#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v) (((v) & 0x1f) << 16) +#define BFM_DRAM_CTL16_LOWPOWER_CONTROL(v) BM_DRAM_CTL16_LOWPOWER_CONTROL +#define BF_DRAM_CTL16_LOWPOWER_CONTROL_V(e) BF_DRAM_CTL16_LOWPOWER_CONTROL(BV_DRAM_CTL16_LOWPOWER_CONTROL__##e) +#define BFM_DRAM_CTL16_LOWPOWER_CONTROL_V(v) BM_DRAM_CTL16_LOWPOWER_CONTROL +#define BP_DRAM_CTL16_RSVD2 13 +#define BM_DRAM_CTL16_RSVD2 0xe000 +#define BF_DRAM_CTL16_RSVD2(v) (((v) & 0x7) << 13) +#define BFM_DRAM_CTL16_RSVD2(v) BM_DRAM_CTL16_RSVD2 +#define BF_DRAM_CTL16_RSVD2_V(e) BF_DRAM_CTL16_RSVD2(BV_DRAM_CTL16_RSVD2__##e) +#define BFM_DRAM_CTL16_RSVD2_V(v) BM_DRAM_CTL16_RSVD2 +#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 8 +#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 0x1f00 +#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v) (((v) & 0x1f) << 8) +#define BFM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v) BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE +#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE_V(e) BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(BV_DRAM_CTL16_LOWPOWER_AUTO_ENABLE__##e) +#define BFM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE_V(v) BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE +#define BP_DRAM_CTL16_RSVD1 4 +#define BM_DRAM_CTL16_RSVD1 0xf0 +#define BF_DRAM_CTL16_RSVD1(v) (((v) & 0xf) << 4) +#define BFM_DRAM_CTL16_RSVD1(v) BM_DRAM_CTL16_RSVD1 +#define BF_DRAM_CTL16_RSVD1_V(e) BF_DRAM_CTL16_RSVD1(BV_DRAM_CTL16_RSVD1__##e) +#define BFM_DRAM_CTL16_RSVD1_V(v) BM_DRAM_CTL16_RSVD1 +#define BP_DRAM_CTL16_INT_ACK 0 +#define BM_DRAM_CTL16_INT_ACK 0xf +#define BF_DRAM_CTL16_INT_ACK(v) (((v) & 0xf) << 0) +#define BFM_DRAM_CTL16_INT_ACK(v) BM_DRAM_CTL16_INT_ACK +#define BF_DRAM_CTL16_INT_ACK_V(e) BF_DRAM_CTL16_INT_ACK(BV_DRAM_CTL16_INT_ACK__##e) +#define BFM_DRAM_CTL16_INT_ACK_V(v) BM_DRAM_CTL16_INT_ACK + +#define HW_DRAM_CTL17 HW(DRAM_CTL17) +#define HWA_DRAM_CTL17 (0x800e0000 + 0x44) +#define HWT_DRAM_CTL17 HWIO_32_RW +#define HWN_DRAM_CTL17 DRAM_CTL17 +#define HWI_DRAM_CTL17 +#define BP_DRAM_CTL17_DLL_START_POINT 24 +#define BM_DRAM_CTL17_DLL_START_POINT 0xff000000 +#define BF_DRAM_CTL17_DLL_START_POINT(v) (((v) & 0xff) << 24) +#define BFM_DRAM_CTL17_DLL_START_POINT(v) BM_DRAM_CTL17_DLL_START_POINT +#define BF_DRAM_CTL17_DLL_START_POINT_V(e) BF_DRAM_CTL17_DLL_START_POINT(BV_DRAM_CTL17_DLL_START_POINT__##e) +#define BFM_DRAM_CTL17_DLL_START_POINT_V(v) BM_DRAM_CTL17_DLL_START_POINT +#define BP_DRAM_CTL17_DLL_LOCK 16 +#define BM_DRAM_CTL17_DLL_LOCK 0xff0000 +#define BF_DRAM_CTL17_DLL_LOCK(v) (((v) & 0xff) << 16) +#define BFM_DRAM_CTL17_DLL_LOCK(v) BM_DRAM_CTL17_DLL_LOCK +#define BF_DRAM_CTL17_DLL_LOCK_V(e) BF_DRAM_CTL17_DLL_LOCK(BV_DRAM_CTL17_DLL_LOCK__##e) +#define BFM_DRAM_CTL17_DLL_LOCK_V(v) BM_DRAM_CTL17_DLL_LOCK +#define BP_DRAM_CTL17_DLL_INCREMENT 8 +#define BM_DRAM_CTL17_DLL_INCREMENT 0xff00 +#define BF_DRAM_CTL17_DLL_INCREMENT(v) (((v) & 0xff) << 8) +#define BFM_DRAM_CTL17_DLL_INCREMENT(v) BM_DRAM_CTL17_DLL_INCREMENT +#define BF_DRAM_CTL17_DLL_INCREMENT_V(e) BF_DRAM_CTL17_DLL_INCREMENT(BV_DRAM_CTL17_DLL_INCREMENT__##e) +#define BFM_DRAM_CTL17_DLL_INCREMENT_V(v) BM_DRAM_CTL17_DLL_INCREMENT +#define BP_DRAM_CTL17_RSVD1 5 +#define BM_DRAM_CTL17_RSVD1 0xe0 +#define BF_DRAM_CTL17_RSVD1(v) (((v) & 0x7) << 5) +#define BFM_DRAM_CTL17_RSVD1(v) BM_DRAM_CTL17_RSVD1 +#define BF_DRAM_CTL17_RSVD1_V(e) BF_DRAM_CTL17_RSVD1(BV_DRAM_CTL17_RSVD1__##e) +#define BFM_DRAM_CTL17_RSVD1_V(v) BM_DRAM_CTL17_RSVD1 +#define BP_DRAM_CTL17_TRC 0 +#define BM_DRAM_CTL17_TRC 0x1f +#define BF_DRAM_CTL17_TRC(v) (((v) & 0x1f) << 0) +#define BFM_DRAM_CTL17_TRC(v) BM_DRAM_CTL17_TRC +#define BF_DRAM_CTL17_TRC_V(e) BF_DRAM_CTL17_TRC(BV_DRAM_CTL17_TRC__##e) +#define BFM_DRAM_CTL17_TRC_V(v) BM_DRAM_CTL17_TRC + +#define HW_DRAM_CTL18 HW(DRAM_CTL18) +#define HWA_DRAM_CTL18 (0x800e0000 + 0x48) +#define HWT_DRAM_CTL18 HWIO_32_RW +#define HWN_DRAM_CTL18 DRAM_CTL18 +#define HWI_DRAM_CTL18 +#define BP_DRAM_CTL18_RSVD4 31 +#define BM_DRAM_CTL18_RSVD4 0x80000000 +#define BF_DRAM_CTL18_RSVD4(v) (((v) & 0x1) << 31) +#define BFM_DRAM_CTL18_RSVD4(v) BM_DRAM_CTL18_RSVD4 +#define BF_DRAM_CTL18_RSVD4_V(e) BF_DRAM_CTL18_RSVD4(BV_DRAM_CTL18_RSVD4__##e) +#define BFM_DRAM_CTL18_RSVD4_V(v) BM_DRAM_CTL18_RSVD4 +#define BP_DRAM_CTL18_DLL_DQS_DELAY_1 24 +#define BM_DRAM_CTL18_DLL_DQS_DELAY_1 0x7f000000 +#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v) (((v) & 0x7f) << 24) +#define BFM_DRAM_CTL18_DLL_DQS_DELAY_1(v) BM_DRAM_CTL18_DLL_DQS_DELAY_1 +#define BF_DRAM_CTL18_DLL_DQS_DELAY_1_V(e) BF_DRAM_CTL18_DLL_DQS_DELAY_1(BV_DRAM_CTL18_DLL_DQS_DELAY_1__##e) +#define BFM_DRAM_CTL18_DLL_DQS_DELAY_1_V(v) BM_DRAM_CTL18_DLL_DQS_DELAY_1 +#define BP_DRAM_CTL18_RSVD3 23 +#define BM_DRAM_CTL18_RSVD3 0x800000 +#define BF_DRAM_CTL18_RSVD3(v) (((v) & 0x1) << 23) +#define BFM_DRAM_CTL18_RSVD3(v) BM_DRAM_CTL18_RSVD3 +#define BF_DRAM_CTL18_RSVD3_V(e) BF_DRAM_CTL18_RSVD3(BV_DRAM_CTL18_RSVD3__##e) +#define BFM_DRAM_CTL18_RSVD3_V(v) BM_DRAM_CTL18_RSVD3 +#define BP_DRAM_CTL18_DLL_DQS_DELAY_0 16 +#define BM_DRAM_CTL18_DLL_DQS_DELAY_0 0x7f0000 +#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v) (((v) & 0x7f) << 16) +#define BFM_DRAM_CTL18_DLL_DQS_DELAY_0(v) BM_DRAM_CTL18_DLL_DQS_DELAY_0 +#define BF_DRAM_CTL18_DLL_DQS_DELAY_0_V(e) BF_DRAM_CTL18_DLL_DQS_DELAY_0(BV_DRAM_CTL18_DLL_DQS_DELAY_0__##e) +#define BFM_DRAM_CTL18_DLL_DQS_DELAY_0_V(v) BM_DRAM_CTL18_DLL_DQS_DELAY_0 +#define BP_DRAM_CTL18_RSVD2 13 +#define BM_DRAM_CTL18_RSVD2 0xe000 +#define BF_DRAM_CTL18_RSVD2(v) (((v) & 0x7) << 13) +#define BFM_DRAM_CTL18_RSVD2(v) BM_DRAM_CTL18_RSVD2 +#define BF_DRAM_CTL18_RSVD2_V(e) BF_DRAM_CTL18_RSVD2(BV_DRAM_CTL18_RSVD2__##e) +#define BFM_DRAM_CTL18_RSVD2_V(v) BM_DRAM_CTL18_RSVD2 +#define BP_DRAM_CTL18_INT_STATUS 8 +#define BM_DRAM_CTL18_INT_STATUS 0x1f00 +#define BF_DRAM_CTL18_INT_STATUS(v) (((v) & 0x1f) << 8) +#define BFM_DRAM_CTL18_INT_STATUS(v) BM_DRAM_CTL18_INT_STATUS +#define BF_DRAM_CTL18_INT_STATUS_V(e) BF_DRAM_CTL18_INT_STATUS(BV_DRAM_CTL18_INT_STATUS__##e) +#define BFM_DRAM_CTL18_INT_STATUS_V(v) BM_DRAM_CTL18_INT_STATUS +#define BP_DRAM_CTL18_RSVD1 5 +#define BM_DRAM_CTL18_RSVD1 0xe0 +#define BF_DRAM_CTL18_RSVD1(v) (((v) & 0x7) << 5) +#define BFM_DRAM_CTL18_RSVD1(v) BM_DRAM_CTL18_RSVD1 +#define BF_DRAM_CTL18_RSVD1_V(e) BF_DRAM_CTL18_RSVD1(BV_DRAM_CTL18_RSVD1__##e) +#define BFM_DRAM_CTL18_RSVD1_V(v) BM_DRAM_CTL18_RSVD1 +#define BP_DRAM_CTL18_INT_MASK 0 +#define BM_DRAM_CTL18_INT_MASK 0x1f +#define BF_DRAM_CTL18_INT_MASK(v) (((v) & 0x1f) << 0) +#define BFM_DRAM_CTL18_INT_MASK(v) BM_DRAM_CTL18_INT_MASK +#define BF_DRAM_CTL18_INT_MASK_V(e) BF_DRAM_CTL18_INT_MASK(BV_DRAM_CTL18_INT_MASK__##e) +#define BFM_DRAM_CTL18_INT_MASK_V(v) BM_DRAM_CTL18_INT_MASK + +#define HW_DRAM_CTL19 HW(DRAM_CTL19) +#define HWA_DRAM_CTL19 (0x800e0000 + 0x4c) +#define HWT_DRAM_CTL19 HWIO_32_RW +#define HWN_DRAM_CTL19 DRAM_CTL19 +#define HWI_DRAM_CTL19 +#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 24 +#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 0xff000000 +#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v) (((v) & 0xff) << 24) +#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v) BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS +#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS_V(e) BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(BV_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS__##e) +#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS_V(v) BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS +#define BP_DRAM_CTL19_RSVD1 23 +#define BM_DRAM_CTL19_RSVD1 0x800000 +#define BF_DRAM_CTL19_RSVD1(v) (((v) & 0x1) << 23) +#define BFM_DRAM_CTL19_RSVD1(v) BM_DRAM_CTL19_RSVD1 +#define BF_DRAM_CTL19_RSVD1_V(e) BF_DRAM_CTL19_RSVD1(BV_DRAM_CTL19_RSVD1__##e) +#define BFM_DRAM_CTL19_RSVD1_V(v) BM_DRAM_CTL19_RSVD1 +#define BP_DRAM_CTL19_DQS_OUT_SHIFT 16 +#define BM_DRAM_CTL19_DQS_OUT_SHIFT 0x7f0000 +#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v) (((v) & 0x7f) << 16) +#define BFM_DRAM_CTL19_DQS_OUT_SHIFT(v) BM_DRAM_CTL19_DQS_OUT_SHIFT +#define BF_DRAM_CTL19_DQS_OUT_SHIFT_V(e) BF_DRAM_CTL19_DQS_OUT_SHIFT(BV_DRAM_CTL19_DQS_OUT_SHIFT__##e) +#define BFM_DRAM_CTL19_DQS_OUT_SHIFT_V(v) BM_DRAM_CTL19_DQS_OUT_SHIFT +#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 8 +#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 0xff00 +#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) (((v) & 0xff) << 8) +#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 +#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1_V(e) BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(BV_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1__##e) +#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1_V(v) BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 +#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0 +#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0xff +#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) (((v) & 0xff) << 0) +#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 +#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0_V(e) BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(BV_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0__##e) +#define BFM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0_V(v) BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 + +#define HW_DRAM_CTL20 HW(DRAM_CTL20) +#define HWA_DRAM_CTL20 (0x800e0000 + 0x50) +#define HWT_DRAM_CTL20 HWIO_32_RW +#define HWN_DRAM_CTL20 DRAM_CTL20 +#define HWI_DRAM_CTL20 +#define BP_DRAM_CTL20_TRCD_INT 24 +#define BM_DRAM_CTL20_TRCD_INT 0xff000000 +#define BF_DRAM_CTL20_TRCD_INT(v) (((v) & 0xff) << 24) +#define BFM_DRAM_CTL20_TRCD_INT(v) BM_DRAM_CTL20_TRCD_INT +#define BF_DRAM_CTL20_TRCD_INT_V(e) BF_DRAM_CTL20_TRCD_INT(BV_DRAM_CTL20_TRCD_INT__##e) +#define BFM_DRAM_CTL20_TRCD_INT_V(v) BM_DRAM_CTL20_TRCD_INT +#define BP_DRAM_CTL20_TRAS_MIN 16 +#define BM_DRAM_CTL20_TRAS_MIN 0xff0000 +#define BF_DRAM_CTL20_TRAS_MIN(v) (((v) & 0xff) << 16) +#define BFM_DRAM_CTL20_TRAS_MIN(v) BM_DRAM_CTL20_TRAS_MIN +#define BF_DRAM_CTL20_TRAS_MIN_V(e) BF_DRAM_CTL20_TRAS_MIN(BV_DRAM_CTL20_TRAS_MIN__##e) +#define BFM_DRAM_CTL20_TRAS_MIN_V(v) BM_DRAM_CTL20_TRAS_MIN +#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 8 +#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 0xff00 +#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v) (((v) & 0xff) << 8) +#define BFM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v) BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS +#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS_V(e) BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(BV_DRAM_CTL20_WR_DQS_SHIFT_BYPASS__##e) +#define BFM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS_V(v) BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS +#define BP_DRAM_CTL20_RSVD1 7 +#define BM_DRAM_CTL20_RSVD1 0x80 +#define BF_DRAM_CTL20_RSVD1(v) (((v) & 0x1) << 7) +#define BFM_DRAM_CTL20_RSVD1(v) BM_DRAM_CTL20_RSVD1 +#define BF_DRAM_CTL20_RSVD1_V(e) BF_DRAM_CTL20_RSVD1(BV_DRAM_CTL20_RSVD1__##e) +#define BFM_DRAM_CTL20_RSVD1_V(v) BM_DRAM_CTL20_RSVD1 +#define BP_DRAM_CTL20_WR_DQS_SHIFT 0 +#define BM_DRAM_CTL20_WR_DQS_SHIFT 0x7f +#define BF_DRAM_CTL20_WR_DQS_SHIFT(v) (((v) & 0x7f) << 0) +#define BFM_DRAM_CTL20_WR_DQS_SHIFT(v) BM_DRAM_CTL20_WR_DQS_SHIFT +#define BF_DRAM_CTL20_WR_DQS_SHIFT_V(e) BF_DRAM_CTL20_WR_DQS_SHIFT(BV_DRAM_CTL20_WR_DQS_SHIFT__##e) +#define BFM_DRAM_CTL20_WR_DQS_SHIFT_V(v) BM_DRAM_CTL20_WR_DQS_SHIFT + +#define HW_DRAM_CTL21 HW(DRAM_CTL21) +#define HWA_DRAM_CTL21 (0x800e0000 + 0x54) +#define HWT_DRAM_CTL21 HWIO_32_RW +#define HWN_DRAM_CTL21 DRAM_CTL21 +#define HWI_DRAM_CTL21 +#define BP_DRAM_CTL21_OBSOLETE 24 +#define BM_DRAM_CTL21_OBSOLETE 0xff000000 +#define BF_DRAM_CTL21_OBSOLETE(v) (((v) & 0xff) << 24) +#define BFM_DRAM_CTL21_OBSOLETE(v) BM_DRAM_CTL21_OBSOLETE +#define BF_DRAM_CTL21_OBSOLETE_V(e) BF_DRAM_CTL21_OBSOLETE(BV_DRAM_CTL21_OBSOLETE__##e) +#define BFM_DRAM_CTL21_OBSOLETE_V(v) BM_DRAM_CTL21_OBSOLETE +#define BP_DRAM_CTL21_RSVD1 18 +#define BM_DRAM_CTL21_RSVD1 0xfc0000 +#define BF_DRAM_CTL21_RSVD1(v) (((v) & 0x3f) << 18) +#define BFM_DRAM_CTL21_RSVD1(v) BM_DRAM_CTL21_RSVD1 +#define BF_DRAM_CTL21_RSVD1_V(e) BF_DRAM_CTL21_RSVD1(BV_DRAM_CTL21_RSVD1__##e) +#define BFM_DRAM_CTL21_RSVD1_V(v) BM_DRAM_CTL21_RSVD1 +#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH 8 +#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH 0x3ff00 +#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v) (((v) & 0x3ff) << 8) +#define BFM_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v) BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH +#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH_V(e) BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(BV_DRAM_CTL21_OUT_OF_RANGE_LENGTH__##e) +#define BFM_DRAM_CTL21_OUT_OF_RANGE_LENGTH_V(v) BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH +#define BP_DRAM_CTL21_TRFC 0 +#define BM_DRAM_CTL21_TRFC 0xff +#define BF_DRAM_CTL21_TRFC(v) (((v) & 0xff) << 0) +#define BFM_DRAM_CTL21_TRFC(v) BM_DRAM_CTL21_TRFC +#define BF_DRAM_CTL21_TRFC_V(e) BF_DRAM_CTL21_TRFC(BV_DRAM_CTL21_TRFC__##e) +#define BFM_DRAM_CTL21_TRFC_V(v) BM_DRAM_CTL21_TRFC + +#define HW_DRAM_CTL22 HW(DRAM_CTL22) +#define HWA_DRAM_CTL22 (0x800e0000 + 0x58) +#define HWT_DRAM_CTL22 HWIO_32_RW +#define HWN_DRAM_CTL22 DRAM_CTL22 +#define HWI_DRAM_CTL22 +#define BP_DRAM_CTL22_RSVD2 27 +#define BM_DRAM_CTL22_RSVD2 0xf8000000 +#define BF_DRAM_CTL22_RSVD2(v) (((v) & 0x1f) << 27) +#define BFM_DRAM_CTL22_RSVD2(v) BM_DRAM_CTL22_RSVD2 +#define BF_DRAM_CTL22_RSVD2_V(e) BF_DRAM_CTL22_RSVD2(BV_DRAM_CTL22_RSVD2__##e) +#define BFM_DRAM_CTL22_RSVD2_V(v) BM_DRAM_CTL22_RSVD2 +#define BP_DRAM_CTL22_AHB0_WRCNT 16 +#define BM_DRAM_CTL22_AHB0_WRCNT 0x7ff0000 +#define BF_DRAM_CTL22_AHB0_WRCNT(v) (((v) & 0x7ff) << 16) +#define BFM_DRAM_CTL22_AHB0_WRCNT(v) BM_DRAM_CTL22_AHB0_WRCNT +#define BF_DRAM_CTL22_AHB0_WRCNT_V(e) BF_DRAM_CTL22_AHB0_WRCNT(BV_DRAM_CTL22_AHB0_WRCNT__##e) +#define BFM_DRAM_CTL22_AHB0_WRCNT_V(v) BM_DRAM_CTL22_AHB0_WRCNT +#define BP_DRAM_CTL22_RSVD1 11 +#define BM_DRAM_CTL22_RSVD1 0xf800 +#define BF_DRAM_CTL22_RSVD1(v) (((v) & 0x1f) << 11) +#define BFM_DRAM_CTL22_RSVD1(v) BM_DRAM_CTL22_RSVD1 +#define BF_DRAM_CTL22_RSVD1_V(e) BF_DRAM_CTL22_RSVD1(BV_DRAM_CTL22_RSVD1__##e) +#define BFM_DRAM_CTL22_RSVD1_V(v) BM_DRAM_CTL22_RSVD1 +#define BP_DRAM_CTL22_AHB0_RDCNT 0 +#define BM_DRAM_CTL22_AHB0_RDCNT 0x7ff +#define BF_DRAM_CTL22_AHB0_RDCNT(v) (((v) & 0x7ff) << 0) +#define BFM_DRAM_CTL22_AHB0_RDCNT(v) BM_DRAM_CTL22_AHB0_RDCNT +#define BF_DRAM_CTL22_AHB0_RDCNT_V(e) BF_DRAM_CTL22_AHB0_RDCNT(BV_DRAM_CTL22_AHB0_RDCNT__##e) +#define BFM_DRAM_CTL22_AHB0_RDCNT_V(v) BM_DRAM_CTL22_AHB0_RDCNT + +#define HW_DRAM_CTL23 HW(DRAM_CTL23) +#define HWA_DRAM_CTL23 (0x800e0000 + 0x5c) +#define HWT_DRAM_CTL23 HWIO_32_RW +#define HWN_DRAM_CTL23 DRAM_CTL23 +#define HWI_DRAM_CTL23 +#define BP_DRAM_CTL23_RSVD2 27 +#define BM_DRAM_CTL23_RSVD2 0xf8000000 +#define BF_DRAM_CTL23_RSVD2(v) (((v) & 0x1f) << 27) +#define BFM_DRAM_CTL23_RSVD2(v) BM_DRAM_CTL23_RSVD2 +#define BF_DRAM_CTL23_RSVD2_V(e) BF_DRAM_CTL23_RSVD2(BV_DRAM_CTL23_RSVD2__##e) +#define BFM_DRAM_CTL23_RSVD2_V(v) BM_DRAM_CTL23_RSVD2 +#define BP_DRAM_CTL23_AHB1_WRCNT 16 +#define BM_DRAM_CTL23_AHB1_WRCNT 0x7ff0000 +#define BF_DRAM_CTL23_AHB1_WRCNT(v) (((v) & 0x7ff) << 16) +#define BFM_DRAM_CTL23_AHB1_WRCNT(v) BM_DRAM_CTL23_AHB1_WRCNT +#define BF_DRAM_CTL23_AHB1_WRCNT_V(e) BF_DRAM_CTL23_AHB1_WRCNT(BV_DRAM_CTL23_AHB1_WRCNT__##e) +#define BFM_DRAM_CTL23_AHB1_WRCNT_V(v) BM_DRAM_CTL23_AHB1_WRCNT +#define BP_DRAM_CTL23_RSVD1 11 +#define BM_DRAM_CTL23_RSVD1 0xf800 +#define BF_DRAM_CTL23_RSVD1(v) (((v) & 0x1f) << 11) +#define BFM_DRAM_CTL23_RSVD1(v) BM_DRAM_CTL23_RSVD1 +#define BF_DRAM_CTL23_RSVD1_V(e) BF_DRAM_CTL23_RSVD1(BV_DRAM_CTL23_RSVD1__##e) +#define BFM_DRAM_CTL23_RSVD1_V(v) BM_DRAM_CTL23_RSVD1 +#define BP_DRAM_CTL23_AHB1_RDCNT 0 +#define BM_DRAM_CTL23_AHB1_RDCNT 0x7ff +#define BF_DRAM_CTL23_AHB1_RDCNT(v) (((v) & 0x7ff) << 0) +#define BFM_DRAM_CTL23_AHB1_RDCNT(v) BM_DRAM_CTL23_AHB1_RDCNT +#define BF_DRAM_CTL23_AHB1_RDCNT_V(e) BF_DRAM_CTL23_AHB1_RDCNT(BV_DRAM_CTL23_AHB1_RDCNT__##e) +#define BFM_DRAM_CTL23_AHB1_RDCNT_V(v) BM_DRAM_CTL23_AHB1_RDCNT + +#define HW_DRAM_CTL24 HW(DRAM_CTL24) +#define HWA_DRAM_CTL24 (0x800e0000 + 0x60) +#define HWT_DRAM_CTL24 HWIO_32_RW +#define HWN_DRAM_CTL24 DRAM_CTL24 +#define HWI_DRAM_CTL24 +#define BP_DRAM_CTL24_RSVD2 27 +#define BM_DRAM_CTL24_RSVD2 0xf8000000 +#define BF_DRAM_CTL24_RSVD2(v) (((v) & 0x1f) << 27) +#define BFM_DRAM_CTL24_RSVD2(v) BM_DRAM_CTL24_RSVD2 +#define BF_DRAM_CTL24_RSVD2_V(e) BF_DRAM_CTL24_RSVD2(BV_DRAM_CTL24_RSVD2__##e) +#define BFM_DRAM_CTL24_RSVD2_V(v) BM_DRAM_CTL24_RSVD2 +#define BP_DRAM_CTL24_AHB2_WRCNT 16 +#define BM_DRAM_CTL24_AHB2_WRCNT 0x7ff0000 +#define BF_DRAM_CTL24_AHB2_WRCNT(v) (((v) & 0x7ff) << 16) +#define BFM_DRAM_CTL24_AHB2_WRCNT(v) BM_DRAM_CTL24_AHB2_WRCNT +#define BF_DRAM_CTL24_AHB2_WRCNT_V(e) BF_DRAM_CTL24_AHB2_WRCNT(BV_DRAM_CTL24_AHB2_WRCNT__##e) +#define BFM_DRAM_CTL24_AHB2_WRCNT_V(v) BM_DRAM_CTL24_AHB2_WRCNT +#define BP_DRAM_CTL24_RSVD1 11 +#define BM_DRAM_CTL24_RSVD1 0xf800 +#define BF_DRAM_CTL24_RSVD1(v) (((v) & 0x1f) << 11) +#define BFM_DRAM_CTL24_RSVD1(v) BM_DRAM_CTL24_RSVD1 +#define BF_DRAM_CTL24_RSVD1_V(e) BF_DRAM_CTL24_RSVD1(BV_DRAM_CTL24_RSVD1__##e) +#define BFM_DRAM_CTL24_RSVD1_V(v) BM_DRAM_CTL24_RSVD1 +#define BP_DRAM_CTL24_AHB2_RDCNT 0 +#define BM_DRAM_CTL24_AHB2_RDCNT 0x7ff +#define BF_DRAM_CTL24_AHB2_RDCNT(v) (((v) & 0x7ff) << 0) +#define BFM_DRAM_CTL24_AHB2_RDCNT(v) BM_DRAM_CTL24_AHB2_RDCNT +#define BF_DRAM_CTL24_AHB2_RDCNT_V(e) BF_DRAM_CTL24_AHB2_RDCNT(BV_DRAM_CTL24_AHB2_RDCNT__##e) +#define BFM_DRAM_CTL24_AHB2_RDCNT_V(v) BM_DRAM_CTL24_AHB2_RDCNT + +#define HW_DRAM_CTL25 HW(DRAM_CTL25) +#define HWA_DRAM_CTL25 (0x800e0000 + 0x64) +#define HWT_DRAM_CTL25 HWIO_32_RW +#define HWN_DRAM_CTL25 DRAM_CTL25 +#define HWI_DRAM_CTL25 +#define BP_DRAM_CTL25_RSVD2 27 +#define BM_DRAM_CTL25_RSVD2 0xf8000000 +#define BF_DRAM_CTL25_RSVD2(v) (((v) & 0x1f) << 27) +#define BFM_DRAM_CTL25_RSVD2(v) BM_DRAM_CTL25_RSVD2 +#define BF_DRAM_CTL25_RSVD2_V(e) BF_DRAM_CTL25_RSVD2(BV_DRAM_CTL25_RSVD2__##e) +#define BFM_DRAM_CTL25_RSVD2_V(v) BM_DRAM_CTL25_RSVD2 +#define BP_DRAM_CTL25_AHB3_WRCNT 16 +#define BM_DRAM_CTL25_AHB3_WRCNT 0x7ff0000 +#define BF_DRAM_CTL25_AHB3_WRCNT(v) (((v) & 0x7ff) << 16) +#define BFM_DRAM_CTL25_AHB3_WRCNT(v) BM_DRAM_CTL25_AHB3_WRCNT +#define BF_DRAM_CTL25_AHB3_WRCNT_V(e) BF_DRAM_CTL25_AHB3_WRCNT(BV_DRAM_CTL25_AHB3_WRCNT__##e) +#define BFM_DRAM_CTL25_AHB3_WRCNT_V(v) BM_DRAM_CTL25_AHB3_WRCNT +#define BP_DRAM_CTL25_RSVD1 11 +#define BM_DRAM_CTL25_RSVD1 0xf800 +#define BF_DRAM_CTL25_RSVD1(v) (((v) & 0x1f) << 11) +#define BFM_DRAM_CTL25_RSVD1(v) BM_DRAM_CTL25_RSVD1 +#define BF_DRAM_CTL25_RSVD1_V(e) BF_DRAM_CTL25_RSVD1(BV_DRAM_CTL25_RSVD1__##e) +#define BFM_DRAM_CTL25_RSVD1_V(v) BM_DRAM_CTL25_RSVD1 +#define BP_DRAM_CTL25_AHB3_RDCNT 0 +#define BM_DRAM_CTL25_AHB3_RDCNT 0x7ff +#define BF_DRAM_CTL25_AHB3_RDCNT(v) (((v) & 0x7ff) << 0) +#define BFM_DRAM_CTL25_AHB3_RDCNT(v) BM_DRAM_CTL25_AHB3_RDCNT +#define BF_DRAM_CTL25_AHB3_RDCNT_V(e) BF_DRAM_CTL25_AHB3_RDCNT(BV_DRAM_CTL25_AHB3_RDCNT__##e) +#define BFM_DRAM_CTL25_AHB3_RDCNT_V(v) BM_DRAM_CTL25_AHB3_RDCNT + +#define HW_DRAM_CTL26 HW(DRAM_CTL26) +#define HWA_DRAM_CTL26 (0x800e0000 + 0x68) +#define HWT_DRAM_CTL26 HWIO_32_RW +#define HWN_DRAM_CTL26 DRAM_CTL26 +#define HWI_DRAM_CTL26 +#define BP_DRAM_CTL26_OBSOLETE 16 +#define BM_DRAM_CTL26_OBSOLETE 0xffff0000 +#define BF_DRAM_CTL26_OBSOLETE(v) (((v) & 0xffff) << 16) +#define BFM_DRAM_CTL26_OBSOLETE(v) BM_DRAM_CTL26_OBSOLETE +#define BF_DRAM_CTL26_OBSOLETE_V(e) BF_DRAM_CTL26_OBSOLETE(BV_DRAM_CTL26_OBSOLETE__##e) +#define BFM_DRAM_CTL26_OBSOLETE_V(v) BM_DRAM_CTL26_OBSOLETE +#define BP_DRAM_CTL26_RSVD1 12 +#define BM_DRAM_CTL26_RSVD1 0xf000 +#define BF_DRAM_CTL26_RSVD1(v) (((v) & 0xf) << 12) +#define BFM_DRAM_CTL26_RSVD1(v) BM_DRAM_CTL26_RSVD1 +#define BF_DRAM_CTL26_RSVD1_V(e) BF_DRAM_CTL26_RSVD1(BV_DRAM_CTL26_RSVD1__##e) +#define BFM_DRAM_CTL26_RSVD1_V(v) BM_DRAM_CTL26_RSVD1 +#define BP_DRAM_CTL26_TREF 0 +#define BM_DRAM_CTL26_TREF 0xfff +#define BF_DRAM_CTL26_TREF(v) (((v) & 0xfff) << 0) +#define BFM_DRAM_CTL26_TREF(v) BM_DRAM_CTL26_TREF +#define BF_DRAM_CTL26_TREF_V(e) BF_DRAM_CTL26_TREF(BV_DRAM_CTL26_TREF__##e) +#define BFM_DRAM_CTL26_TREF_V(v) BM_DRAM_CTL26_TREF + +#define HW_DRAM_CTL27 HW(DRAM_CTL27) +#define HWA_DRAM_CTL27 (0x800e0000 + 0x6c) +#define HWT_DRAM_CTL27 HWIO_32_RW +#define HWN_DRAM_CTL27 DRAM_CTL27 |