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authorAmaury Pouly <amaury.pouly@gmail.com>2013-06-16 17:56:10 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2013-06-16 18:21:48 +0200
commit96b1d02b057164d4e521d7e9aa50ee5e1223008a (patch)
tree24783034c863c27e42dae5638b24239a804dd5cc /firmware/target/arm/imx233/system-target.h
parenta759242b559cab9c2cd02bf0888945edfd146ac0 (diff)
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imx233: rewrite digctl using new register headers
Change-Id: I910a09e07b9f5a82bb6cb150739fcebc942cb7c1
Diffstat (limited to 'firmware/target/arm/imx233/system-target.h')
-rw-r--r--firmware/target/arm/imx233/system-target.h29
1 files changed, 2 insertions, 27 deletions
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h
index c6073a9ae3..407369af7e 100644
--- a/firmware/target/arm/imx233/system-target.h
+++ b/firmware/target/arm/imx233/system-target.h
@@ -28,33 +28,8 @@
#include "icoll-imx233.h"
#include "clock-target.h" /* CPUFREQ_* are defined here */
-/* Digital control */
-#define HW_DIGCTL_BASE 0x8001C000
-#define HW_DIGCTL_CTRL (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0))
-#define HW_DIGCTL_CTRL__USB_CLKGATE (1 << 2)
-
-#define HW_DIGCTL_HCLKCOUNT (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x20))
-
-#define HW_DIGCTL_MICROSECONDS (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0))
-
-#define HW_DIGCTL_ARMCACHE (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x2b0))
-#define HW_DIGCTL_ARMCACHE__ITAG_SS_BP 0
-#define HW_DIGCTL_ARMCACHE__ITAG_SS_BM (3 << 0)
-#define HW_DIGCTL_ARMCACHE__DTAG_SS_BP 4
-#define HW_DIGCTL_ARMCACHE__DTAG_SS_BM (3 << 4)
-#define HW_DIGCTL_ARMCACHE__CACHE_SS_BP 8
-#define HW_DIGCTL_ARMCACHE__CACHE_SS_BM (3 << 8)
-#define HW_DIGCTL_ARMCACHE__DRTY_SS_BP 12
-#define HW_DIGCTL_ARMCACHE__DRTY_SS_BM (3 << 12)
-#define HW_DIGCTL_ARMCACHE__VALID_SS_BP 16
-#define HW_DIGCTL_ARMCACHE__VALID_SS_BM (3 << 16)
-
-/* USB Phy */
-#define HW_USBPHY_BASE 0x8007C000
-#define HW_USBPHY_PWD (*(volatile uint32_t *)(HW_USBPHY_BASE + 0))
-#define HW_USBPHY_PWD__ALL (7 << 10 | 0xf << 17)
-
-#define HW_USBPHY_CTRL (*(volatile uint32_t *)(HW_USBPHY_BASE + 0x30))
+#include "regs/regs-digctl.h"
+#include "regs/regs-usbphy.h"
/**
* Absolute maximum CPU speed: 454.74 MHz