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authorAmaury Pouly <pamaury@rockbox.org>2011-05-04 18:00:22 +0000
committerAmaury Pouly <pamaury@rockbox.org>2011-05-04 18:00:22 +0000
commitffee0b5e94e565f94b7a312bcbee12d932b6e332 (patch)
tree11bcea325aba3ff18613db58ddf8f3831cfd878e /firmware/target/arm/imx233/system-target.h
parent37a9a200b2ab93f02b8085e78aac91b8ff68419c (diff)
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fuze+: move defines from .c to .h; implement button reading for volume up/down and power
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29822 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx233/system-target.h')
-rw-r--r--firmware/target/arm/imx233/system-target.h27
1 files changed, 27 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h
index 675adb448b..4d767b3a9f 100644
--- a/firmware/target/arm/imx233/system-target.h
+++ b/firmware/target/arm/imx233/system-target.h
@@ -30,6 +30,33 @@
#define HW_DIGCTL_BASE 0x8001C000
#define HW_DIGCTL_MICROSECONDS (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0))
+#define HW_POWER_BASE 0x80044000
+#define HW_POWER_STS (*(volatile uint32_t *)(HW_POWER_BASE + 0xc0))
+#define HW_POWER_STS__PSWITCH_BP 20
+#define HW_POWER_STS__PSWITCH_BM (3 << 20)
+
+#define HW_POWER_RESET (*(volatile uint32_t *)(HW_POWER_BASE + 0x100))
+#define HW_POWER_RESET__UNLOCK 0x3E770000
+#define HW_POWER_RESET__PWD 0x1
+
+#define HW_ICOLL_BASE 0x80000000
+
+#define HW_ICOLL_VECTOR (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x0))
+
+#define HW_ICOLL_LEVELACK (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x10))
+#define HW_ICOLL_LEVELACK__LEVEL0 0x1
+
+#define HW_ICOLL_CTRL (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x20))
+#define HW_ICOLL_CTRL__IRQ_FINAL_ENABLE (1 << 16)
+#define HW_ICOLL_CTRL__ARM_RSE_MODE (1 << 18)
+
+#define HW_ICOLL_VBASE (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x40))
+#define HW_ICOLL_INTERRUPT(i) (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x120 + (i) * 0x10))
+#define HW_ICOLL_INTERRUPT__PRIORITY_BM 0x3
+#define HW_ICOLL_INTERRUPT__ENABLE 0x4
+#define HW_ICOLL_INTERRUPT__SOFTIRQ 0x8
+#define HW_ICOLL_INTERRUPT__ENFIQ 0x10
+
#define INT_SRC_USB_CTRL 11
#define INT_SRC_TIMER(nr) (28 + (nr))
#define INT_SRC_LCDIF_DMA 45