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authorAmaury Pouly <amaury.pouly@gmail.com>2013-06-16 14:46:58 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2013-06-16 14:46:58 +0200
commitf545908c160702c826add431c467fe9c05a7d825 (patch)
tree0da8ca62cd23f55414ee75b5ce237a0532c80db0 /firmware/target/arm/imx233
parent81224c62bb6cdd0cac9c3406f55ae5096109e602 (diff)
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imx233: rewrite icoll to use new register headers
Change-Id: I0bf30849d18a8493627025b383ce75ce524777ab
Diffstat (limited to 'firmware/target/arm/imx233')
-rw-r--r--firmware/target/arm/imx233/icoll-imx233.c18
-rw-r--r--firmware/target/arm/imx233/icoll-imx233.h19
2 files changed, 9 insertions, 28 deletions
diff --git a/firmware/target/arm/imx233/icoll-imx233.c b/firmware/target/arm/imx233/icoll-imx233.c
index 0d785337d0..1bd363e781 100644
--- a/firmware/target/arm/imx233/icoll-imx233.c
+++ b/firmware/target/arm/imx233/icoll-imx233.c
@@ -113,7 +113,7 @@ static uint32_t irq_count[INT_SRC_NR_SOURCES];
struct imx233_icoll_irq_info_t imx233_icoll_get_irq_info(int src)
{
struct imx233_icoll_irq_info_t info;
- info.enabled = !!(HW_ICOLL_INTERRUPT(src) & HW_ICOLL_INTERRUPT__ENABLE);
+ info.enabled = BF_RDn(ICOLL_INTERRUPTn, src, ENABLE);
info.freq = irq_count_old[src];
return info;
}
@@ -145,7 +145,7 @@ void irq_handler(void)
do_irq_stat();
(*(isr_t *)HW_ICOLL_VECTOR)();
/* acknowledge completion of IRQ (all use the same priority 0) */
- HW_ICOLL_LEVELACK = HW_ICOLL_LEVELACK__LEVEL0;
+ HW_ICOLL_LEVELACK = BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0;
}
void fiq_handler(void)
@@ -155,23 +155,21 @@ void fiq_handler(void)
void imx233_icoll_enable_interrupt(int src, bool enable)
{
if(enable)
- __REG_SET(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE;
+ BF_SETn(ICOLL_INTERRUPTn, src, ENABLE);
else
- __REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE;
+ BF_CLRn(ICOLL_INTERRUPTn, src, ENABLE);
}
void imx233_icoll_init(void)
{
imx233_reset_block(&HW_ICOLL_CTRL);
- /* disable all interrupts */
+ /* disable all interrupts:
+ * priority = 0, disable, disable fiq */
for(int i = 0; i < INT_SRC_NR_SOURCES; i++)
- {
- /* priority = 0, disable, disable fiq */
- HW_ICOLL_INTERRUPT(i) = 0;
- }
+ HW_ICOLL_INTERRUPTn(i) = 0;
/* setup vbase as isr_table */
HW_ICOLL_VBASE = (uint32_t)&isr_table;
/* enable final irq bit */
- __REG_SET(HW_ICOLL_CTRL) = HW_ICOLL_CTRL__IRQ_FINAL_ENABLE;
+ BF_SET(ICOLL_CTRL, IRQ_FINAL_ENABLE);
}
diff --git a/firmware/target/arm/imx233/icoll-imx233.h b/firmware/target/arm/imx233/icoll-imx233.h
index d1bf8a18aa..e44b67f1d4 100644
--- a/firmware/target/arm/imx233/icoll-imx233.h
+++ b/firmware/target/arm/imx233/icoll-imx233.h
@@ -24,24 +24,7 @@
#include "config.h"
#include "system.h"
-/* Interrupt collector */
-#define HW_ICOLL_BASE 0x80000000
-
-#define HW_ICOLL_VECTOR (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x0))
-
-#define HW_ICOLL_LEVELACK (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x10))
-#define HW_ICOLL_LEVELACK__LEVEL0 0x1
-
-#define HW_ICOLL_CTRL (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x20))
-#define HW_ICOLL_CTRL__IRQ_FINAL_ENABLE (1 << 16)
-#define HW_ICOLL_CTRL__ARM_RSE_MODE (1 << 18)
-
-#define HW_ICOLL_VBASE (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x40))
-#define HW_ICOLL_INTERRUPT(i) (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x120 + (i) * 0x10))
-#define HW_ICOLL_INTERRUPT__PRIORITY_BM 0x3
-#define HW_ICOLL_INTERRUPT__ENABLE 0x4
-#define HW_ICOLL_INTERRUPT__SOFTIRQ 0x8
-#define HW_ICOLL_INTERRUPT__ENFIQ 0x10
+#include "regs/regs-icoll.h"
#define INT_SRC_SSP2_ERROR 2
#define INT_SRC_VDD5V 3