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authorMichael Sevakis <jethead71@rockbox.org>2012-01-03 15:57:55 +0000
committerMichael Sevakis <jethead71@rockbox.org>2012-01-03 15:57:55 +0000
commit68ccefed5a7d0f3183ddbf132ec079e83ca68757 (patch)
tree4ab50c131dad7ee053844bb811f9bc944665a850 /firmware/target/arm/imx31
parent40786042df12b2297161ca986b431d64a5df56db (diff)
downloadrockbox-68ccefed5a7d0f3183ddbf132ec079e83ca68757.tar.gz
rockbox-68ccefed5a7d0f3183ddbf132ec079e83ca68757.zip
Gigabeat S: Dump some now-irrelevant comments.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31538 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c2
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c4
2 files changed, 1 insertions, 5 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
index 5ee0ba5224..2ed6d80afe 100644
--- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c
@@ -34,8 +34,6 @@ static struct i2c_node si4700_i2c_node =
{
.num = I2C2_NUM,
.ifdr = I2C_IFDR_DIV192, /* 66MHz/.4MHz = 165, closest = 192 = 343750Hz */
- /* Just hard-code for now - scaling may require
- * updating */
.addr = (0x20),
};
diff --git a/firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c
index 6ae8c23c48..76001dddd6 100644
--- a/firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/mc13783-gigabeat-s.c
@@ -32,11 +32,9 @@
/* Gigabeat S mc13783 serial interface node. */
-/* This is all based on communicating with the MC13783 PMU which is on
- * CSPI2 with the chip select at 0. The LCD controller resides on
- * CSPI3 cs1, but we have no idea how to communicate to it */
struct spi_node mc13783_spi =
{
+ /* Based upon original firmware settings */
CSPI2_NUM, /* CSPI module 2 */
CSPI_CONREG_CHIP_SELECT_SS0 | /* Chip select 0 */
CSPI_CONREG_DRCTL_DONT_CARE | /* Don't care about CSPI_RDY */