path: root/firmware/target/arm/iriver/
diff options
authorMichael Sevakis <>2008-04-06 04:34:57 +0000
committerMichael Sevakis <>2008-04-06 04:34:57 +0000
commit05099149f193cac0c81b0129c17feb78b1a9681a (patch)
tree3dd5494dd494bcb4490ddcedef99e9f3a895cd3f /firmware/target/arm/iriver/
parentbe698f086de4641a45dffd9289671588c2391a3c (diff)
Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit).
git-svn-id: svn:// a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/iriver/')
1 files changed, 2 insertions, 0 deletions
diff --git a/firmware/target/arm/iriver/ b/firmware/target/arm/iriver/
index 5fbe999333..971ec6627b 100644
--- a/firmware/target/arm/iriver/
+++ b/firmware/target/arm/iriver/
@@ -27,6 +27,7 @@ SECTIONS
+ *(.ncdata*);
_dataend = . ;
@@ -48,6 +49,7 @@ SECTIONS
_edata = .;
+ *(.ncbss*);
_end = .;