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authorSolomon Peachy <pizza@shaftnet.org>2021-04-01 10:52:51 -0400
committerSolomon Peachy <pizza@shaftnet.org>2021-04-01 10:57:29 -0400
commit2f785c7797d0a40a0c797208cbcc753ddfe9193a (patch)
treea982829ef08cabc77b2a630d873fd1f83ef6abff /firmware/target/arm/pp/system-pp502x.c
parent9f7f1a841a11b9eb3c4c356a875c82ed58658a63 (diff)
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PP: More cache invalidation fixes
Take into account the size of the pointer in the loop termination condition. Change-Id: Ib4f7625ef143149a0d691a2109bad67aece6241c
Diffstat (limited to 'firmware/target/arm/pp/system-pp502x.c')
-rw-r--r--firmware/target/arm/pp/system-pp502x.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/target/arm/pp/system-pp502x.c b/firmware/target/arm/pp/system-pp502x.c
index b1e791ec59..d6dfad1b24 100644
--- a/firmware/target/arm/pp/system-pp502x.c
+++ b/firmware/target/arm/pp/system-pp502x.c
@@ -253,15 +253,15 @@ static void ICODE_ATTR cache_invalidate_special(void)
if (CURRENT_CORE == CPU)
{
for (p = &CACHE_STATUS_BASE_CPU;
- p < (&CACHE_STATUS_BASE_CPU) + CACHE_SIZE;
- p += CACHEALIGN_BITS) /* sizeof(p) * CACHEALIGN_BITS */
+ p < (&CACHE_STATUS_BASE_CPU) + CACHE_SIZE/sizeof(*p);
+ p += CACHEALIGN_SIZE/sizeof(*p))
*p = CACHE_LINE_VALID | CACHE_ADDRESS_MASK;
}
else
{
for (p = &CACHE_STATUS_BASE_COP;
- p < (&CACHE_STATUS_BASE_COP) + CACHE_SIZE;
- p += CACHEALIGN_BITS)
+ p < (&CACHE_STATUS_BASE_COP) + CACHE_SIZE/sizeof(*p);
+ p += CACHEALIGN_SIZE/sizeof(*p))
*p = CACHE_LINE_VALID | CACHE_ADDRESS_MASK;
}
}