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authorandypotter <liveboxandy@gmail.com>2013-04-15 20:09:39 +0100
committerMarcin Bukat <marcin.bukat@gmail.com>2013-04-25 21:02:09 +0200
commitecaa40166000e3d6b49542d42804127c0a6079e2 (patch)
tree35ce073fb6d63f90fa3be39aa7433907327b8998 /firmware/target/arm/pp/system-pp502x.c
parent354c9894062886443e1c53cc4dc5669a1d72a5f4 (diff)
downloadrockbox-ecaa40166000e3d6b49542d42804127c0a6079e2.tar.gz
rockbox-ecaa40166000e3d6b49542d42804127c0a6079e2.zip
Add Serial Port 1 support for iPod Photo/Color/4G/Mini2G
Based on FS#9920 by Ryan Press with changes to selection logic so that it works on my iPod Photo. Should also work on iPod Color/4G and Mini2G. Moved all target specific code from firmware/drivers/serial.c into new file firmware/target/arm/pp/uart-pp.c in the same manner as other target specific uart code. Update to fix build error on ipodmini2g by adding defines in config file. Removed unwanted whitespace Tested on iPod Photo. Change-Id: Ia5539563966198e06372d70b5adf2ef78882f863 Reviewed-on: http://gerrit.rockbox.org/455 Reviewed-by: andypotter <liveboxandy@gmail.com> Tested-by: andypotter <liveboxandy@gmail.com> Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
Diffstat (limited to 'firmware/target/arm/pp/system-pp502x.c')
-rw-r--r--firmware/target/arm/pp/system-pp502x.c20
1 files changed, 9 insertions, 11 deletions
diff --git a/firmware/target/arm/pp/system-pp502x.c b/firmware/target/arm/pp/system-pp502x.c
index d3331bf9f4..af2e6d7761 100644
--- a/firmware/target/arm/pp/system-pp502x.c
+++ b/firmware/target/arm/pp/system-pp502x.c
@@ -32,7 +32,7 @@
#if !defined(BOOTLOADER) || defined(HAVE_BOOTLOADER_USB_MODE)
extern void TIMER1(void);
extern void TIMER2(void);
-extern void SERIAL0(void);
+extern void SERIAL_ISR(void);
#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
static struct corelock cpufreq_cl SHAREDBSS_ATTR;
@@ -126,7 +126,6 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void)
button_int();
if (GPIOD_INT_STAT & 0x80)
headphones_int();
-
}
else if (CPU_HI_INT_STAT & GPIO2_MASK) {
if (GPIOL_INT_STAT & 0x04)
@@ -169,8 +168,8 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void)
/* end PBELL_VIBE500 */
#endif
#ifdef IPOD_ACCESSORY_PROTOCOL
- else if (CPU_HI_INT_STAT & SER0_MASK) {
- SERIAL0();
+ else if (CPU_HI_INT_STAT & (SER0_MASK | SER1_MASK)) {
+ SERIAL_ISR();
}
#endif
} else {
@@ -310,7 +309,7 @@ void set_cpu_frequency(long frequency)
#else
static void pp_set_cpu_frequency(long frequency)
#endif
-{
+{
#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
corelock_lock(&cpufreq_cl);
#endif
@@ -334,7 +333,7 @@ static void pp_set_cpu_frequency(long frequency)
PLL_CONTROL &= ~0x80000000; /* disable PLL */
DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */
break;
-
+
case CPUFREQ_MAX:
cpu_frequency = CPUFREQ_MAX;
DEV_INIT2 |= INIT_PLL; /* enable PLL power */
@@ -379,7 +378,7 @@ static void pp_set_cpu_frequency(long frequency)
DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */
break;
#else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/
- case CPUFREQ_NORMAL:
+ case CPUFREQ_NORMAL:
cpu_frequency = CPUFREQ_NORMAL;
DEV_INIT2 |= INIT_PLL; /* enable PLL power */
PLL_CONTROL |= 0x88000000; /* enable PLL */
@@ -421,7 +420,7 @@ static void pp_set_cpu_frequency(long frequency)
DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */
break;
}
-
+
#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
corelock_unlock(&cpufreq_cl);
#endif
@@ -447,7 +446,7 @@ void system_init(void)
DEV_RS2 = 0xffffdfff;
DEV_RS = 0x00000000;
DEV_RS2 = 0x00000000;
-#elif defined (IPOD_VIDEO)
+#elif defined (IPOD_VIDEO)
/* set minimum startup configuration */
DEV_EN = 0xc2000124;
DEV_EN2 = 0x00000000;
@@ -461,7 +460,7 @@ void system_init(void)
DEV_RS2 = 0xffffffff;
DEV_RS = 0x00000000;
DEV_RS2 = 0x00000000;
-#elif defined (IPOD_NANO)
+#elif defined (IPOD_NANO)
/* set minimum startup configuration */
DEV_EN = 0xc2000124;
DEV_EN2 = 0x00002000;
@@ -625,4 +624,3 @@ int system_memory_guard(int newmode)
(void)newmode;
return 0;
}
-