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authorBarry Wardell <rockbox@barrywardell.net>2007-03-03 17:25:20 +0000
committerBarry Wardell <rockbox@barrywardell.net>2007-03-03 17:25:20 +0000
commit8b061252c4359aa960ae31c0a4b2ba92f6771017 (patch)
treeaad5ba8e1defbf09e68887d6d06db362e66f3b67 /firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
parenta7311331d551cb09b0573a7935915de6dc54a4d1 (diff)
downloadrockbox-8b061252c4359aa960ae31c0a4b2ba92f6771017.tar.gz
rockbox-8b061252c4359aa960ae31c0a4b2ba92f6771017.zip
Replace some inl/outl with register #define's instead. Also tidy up pp5020.h so that it's in increasing address order.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12574 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/sandisk/sansa-e200/lcd-e200.c')
-rw-r--r--firmware/target/arm/sandisk/sansa-e200/lcd-e200.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
index 25bb6f04aa..e34ebd7c5a 100644
--- a/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
+++ b/firmware/target/arm/sandisk/sansa-e200/lcd-e200.c
@@ -110,7 +110,7 @@ static inline void cache_flush(void)
{
#ifndef BOOTLOADER
outl(inl(0xf000f044) | 0x2, 0xf000f044);
- while ((inl(0x6000c000) & 0x8000) != 0)
+ while ((CACHE_CTL & 0x8000) != 0)
{
}
#endif
@@ -141,12 +141,12 @@ inline void lcd_init_device(void)
outl(((inl(0x70000010) & (0x03ffffff)) | (0x15 << 26)), 0x70000010);
outl(((inl(0x70000014) & (0x0fffffff)) | (0x5 << 28)), 0x70000014);
outl((inl(0x70000020) & ~(0x3 << 10)), 0x70000020);
- outl((inl(0x6000600c) | (1 << 26)), 0x6000600c); /* Enable controller */
+ DEV_EN |= (1 << 26); /* Enable controller */
outl(0x6, 0x600060d0);
- outl((inl(0x60006004) | (1 << 26)), 0x60006004); /* Reset controller? */
+ DEV_RS |= (1 << 26); /* Reset controller */
outl((inl(0x70000020) & ~(1 << 14)), 0x70000020);
lcd_bus_idle();
- outl((inl(0x60006004) & ~(1 << 26)), 0x60006004); /* Clear reset? */
+ DEV_RS &=~(1 << 26); /* Clear reset */
udelay(1000);
LCD_REG_0 = (LCD_REG_0 & (0x00ffffff)) | (0x22 << 24);