diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2007-11-27 01:20:26 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2007-11-27 01:20:26 +0000 |
commit | a8b388fb86096b265780ac682adddcec22005f79 (patch) | |
tree | d200d0ef25dcca41eecf5f0565970cc481fedb03 /firmware/target/arm/system-pp5002.c | |
parent | 0ade09bd6b14f4c27d28d055306ccd63569f5c49 (diff) | |
download | rockbox-a8b388fb86096b265780ac682adddcec22005f79.tar.gz rockbox-a8b388fb86096b265780ac682adddcec22005f79.zip |
Enable dualcore for the pp5002 processor by adding the needed cache handling and sleep/wakeup sync to the kernel. Refine some handling of fw/bl startup for all.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15827 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-pp5002.c')
-rw-r--r-- | firmware/target/arm/system-pp5002.c | 71 |
1 files changed, 55 insertions, 16 deletions
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c index 08783280be..164913f0f6 100644 --- a/firmware/target/arm/system-pp5002.c +++ b/firmware/target/arm/system-pp5002.c @@ -44,9 +44,7 @@ void irq(void) } else { - if (COP_INT_STAT & TIMER1_MASK) - TIMER1(); - else if (COP_INT_STAT & TIMER2_MASK) + if (COP_INT_STAT & TIMER2_MASK) TIMER2(); } } @@ -61,24 +59,60 @@ void irq(void) some other CPU frequency scaling. */ #ifndef BOOTLOADER +void flush_icache(void) ICODE_ATTR; +void flush_icache(void) +{ + intptr_t b, e; + + for (b = (intptr_t)&CACHE_FLUSH_BASE, e = b + CACHE_SIZE; + b < e; b += 16) { + outl(0x0, b); + } +} + +void invalidate_icache(void) ICODE_ATTR; +void invalidate_icache(void) +{ + intptr_t b, e; + + /* Flush */ + for (b = (intptr_t)&CACHE_FLUSH_BASE, e = b + CACHE_SIZE; + b < e; b += 16) { + outl(0x0, b); + } + + /* Invalidate */ + for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE; + b < e; b += 16) { + outl(0x0, b); + } +} + static void ipod_init_cache(void) { - int i =0; + intptr_t b, e; + /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */ - outl(inl(0xcf004050) & ~0x700, 0xcf004050); + PROC_STAT &= ~0x700; outl(0x4000, 0xcf004020); - outl(0x2, 0xcf004024); + CACHE_CTL = CACHE_INIT; - /* PP5002 has 8KB cache */ - for (i = 0xf0004000; i < (int)(0xf0006000); i += 16) { - outl(0x0, i); + for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE; + b < e; b += 16) { + outl(0x0, b); } - outl(0x0, 0xf000f020); - outl(0x3fc0, 0xf000f024); + /* Cache if (addr & mask) >> 16 == (mask & match) >> 16: + * yes: 0x00000000 - 0x03ffffff + * no: 0x04000000 - 0x1fffffff + * yes: 0x20000000 - 0x23ffffff + * no: 0x24000000 - 0x3fffffff <= range containing uncached alias + */ + CACHE_MASK = 0x00001c00; + CACHE_OPERATION = 0x3fc0; - outl(0x3, 0xcf004024); + CACHE_CTL = CACHE_INIT | CACHE_RUN; } #ifdef HAVE_ADJUSTABLE_CPU_FREQ @@ -132,9 +166,10 @@ void system_init(void) #ifndef BOOTLOADER if (CURRENT_CORE == CPU) { - /* Remap the flash ROM from 0x00000000 to 0x20000000. */ - MMAP3_LOGICAL = 0x20000000 | 0x3a00; - MMAP3_PHYSICAL = 0x00000000 | 0x3f84; + /* Remap the flash ROM on CPU, keep hidden from COP: + * 0x00000000-0x03ffffff = 0x20000000-0x23ffffff */ + MMAP1_LOGICAL = 0x20003c00; + MMAP1_PHYSICAL = 0x00003f84; #if defined(IPOD_1G2G) || defined(IPOD_3G) DEV_EN = 0x0b9f; /* don't clock unused PP5002 hardware components */ @@ -150,7 +185,11 @@ void system_init(void) GPIOC_INT_EN = 0; GPIOD_INT_EN = 0; -#ifndef HAVE_ADJUSTABLE_CPU_FREQ +#ifdef HAVE_ADJUSTABLE_CPU_FREQ +#if NUM_CORES > 1 + cpu_boost_init(); +#endif +#else pp_set_cpu_frequency(CPUFREQ_MAX); #endif } |