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authorThomas Martitz <kugel@rockbox.org>2010-09-08 17:05:49 +0000
committerThomas Martitz <kugel@rockbox.org>2010-09-08 17:05:49 +0000
commitdd5dd8cfd9d3e98b87d64e34f449fff2df30fe7f (patch)
tree9d774686283a67152dba13d4079eca5aec33dde1 /firmware/target/arm/system-pp5002.c
parentca0e95ad08263d4dc7e121074eaa07dab6c07507 (diff)
downloadrockbox-dd5dd8cfd9d3e98b87d64e34f449fff2df30fe7f.tar.gz
rockbox-dd5dd8cfd9d3e98b87d64e34f449fff2df30fe7f.zip
Rename cache coherency functions.
The old cache coherency function names where wrong and misleading. The new names are (purposely different from vendor manuals) * commit_* (write-back only) * discard_* (removing lines from cache only) * commit_discard_* (write-back and removing lines from cache) It's suspected the old names have led to wrong uses. The old names still exist (as aliases) so every call via the old names need to be double checked and changed to the new name. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28045 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-pp5002.c')
-rw-r--r--firmware/target/arm/system-pp5002.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c
index 746441113e..04e052fa83 100644
--- a/firmware/target/arm/system-pp5002.c
+++ b/firmware/target/arm/system-pp5002.c
@@ -62,7 +62,7 @@ void __attribute__((interrupt("IRQ"))) irq_handler(void)
some other CPU frequency scaling. */
#ifndef BOOTLOADER
-void ICODE_ATTR __attribute__((naked)) cpucache_flush(void)
+void ICODE_ATTR __attribute__((naked)) cpucache_commit(void)
{
asm volatile(
"mov r0, #0xf0000000 \n"
@@ -70,14 +70,15 @@ void ICODE_ATTR __attribute__((naked)) cpucache_flush(void)
"add r1, r0, #0x2000 \n" /* r1 = CACHE_FLUSH_BASE + CACHE_SIZE */
"mov r2, #0 \n"
"1: \n"
- "str r2, [r0], #16 \n" /* Flush */
+ "str r2, [r0], #16 \n" /* Commit */
"cmp r0, r1 \n"
"blo 1b \n"
"bx lr \n"
);
}
+void cpucache_flush(void) __attribute__((alias("cpucache_commit")));
-void ICODE_ATTR __attribute__((naked)) cpucache_invalidate(void)
+void ICODE_ATTR __attribute__((naked)) cpucache_commit_discard(void)
{
asm volatile(
"mov r0, #0xf0000000 \n"
@@ -86,13 +87,14 @@ void ICODE_ATTR __attribute__((naked)) cpucache_invalidate(void)
"add r1, r0, #0x2000 \n" /* r2 = CACHE_FLUSH_BASE + CACHE_SIZE */
"mov r3, #0 \n"
"1: \n"
- "str r3, [r0], #16 \n" /* Flush */
- "str r3, [r2], #16 \n" /* Invalidate */
+ "str r3, [r0], #16 \n" /* Commit */
+ "str r3, [r2], #16 \n" /* Discard */
"cmp r0, r1 \n"
"blo 1b \n"
"bx lr \n"
);
}
+void cpucache_invalidate(void) __attribute__((alias("cpucache_commit_discard")));
static void ipod_init_cache(void)
{