summaryrefslogtreecommitdiffstats
path: root/firmware/target/arm/system-pp502x.c
diff options
context:
space:
mode:
authorPaul Louden <paulthenerd@gmail.com>2007-11-20 01:46:18 +0000
committerPaul Louden <paulthenerd@gmail.com>2007-11-20 01:46:18 +0000
commit9873d33bf535923265b07163785bd73d3b2759b3 (patch)
treebfb65bfefda326feaa1965101356fd37063315a8 /firmware/target/arm/system-pp502x.c
parent19c86e86131f839508c5924201db3146d61853b3 (diff)
downloadrockbox-9873d33bf535923265b07163785bd73d3b2759b3.tar.gz
rockbox-9873d33bf535923265b07163785bd73d3b2759b3.zip
Fix for Nano timing issues, should resolve crashes, data aborts, and
general glitchiness in playback. Based on the patch in FS#7510 by Jordan Anderson. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15705 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-pp502x.c')
-rw-r--r--firmware/target/arm/system-pp502x.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index a1c4d1639e..4d7e603a16 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -178,6 +178,9 @@ static void pp_set_cpu_frequency(long frequency)
case CPUFREQ_MAX:
CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */
DEV_TIMING1 = 0x00000303;
+#ifdef IPOD_NANO
+ IDE0_CFG |= (0x10000000); /* Set CPU > 65MHz bit */
+#endif
#ifdef IPOD_MINI2G
MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
#endif
@@ -199,6 +202,9 @@ static void pp_set_cpu_frequency(long frequency)
case CPUFREQ_NORMAL:
CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */
DEV_TIMING1 = 0x00000303;
+#ifdef IPOD_NANO
+ IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */
+#endif
#ifdef IPOD_MINI2G
MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
#endif
@@ -229,6 +235,9 @@ static void pp_set_cpu_frequency(long frequency)
#ifdef IPOD_MINI2G
MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
#endif
+#ifdef IPOD_NANO
+ IDE0_CFG &=~(0x10000000); /* clear > 65MHz bit */
+#endif
PLL_CONTROL &= ~0x80000000; /* disable PLL */
cpu_frequency = CPUFREQ_DEFAULT;
PROC_CTL(CURRENT_CORE) = 0x4800001f; nop;