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authorMichael Sevakis <jethead71@rockbox.org>2008-04-06 04:34:57 +0000
committerMichael Sevakis <jethead71@rockbox.org>2008-04-06 04:34:57 +0000
commit05099149f193cac0c81b0129c17feb78b1a9681a (patch)
tree3dd5494dd494bcb4490ddcedef99e9f3a895cd3f /firmware/target/arm/system-target.h
parentbe698f086de4641a45dffd9289671588c2391a3c (diff)
downloadrockbox-05099149f193cac0c81b0129c17feb78b1a9681a.tar.gz
rockbox-05099149f193cac0c81b0129c17feb78b1a9681a.zip
Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-target.h')
-rw-r--r--firmware/target/arm/system-target.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index 8dcbf0f9da..2a72b524f7 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -108,7 +108,7 @@ static inline unsigned int processor_id(void)
/* Certain data needs to be out of the way of cache line interference
* such as data for COP use or for use with UNCACHED_ADDR */
#define PROC_NEEDS_CACHEALIGN
-#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
+#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
/** cache functions **/
#ifndef BOOTLOADER