summaryrefslogtreecommitdiffstats
path: root/firmware/target/arm/tms320dm320
diff options
context:
space:
mode:
authorTomasz Moń <desowin@gmail.com>2011-12-21 14:56:22 +0000
committerTomasz Moń <desowin@gmail.com>2011-12-21 14:56:22 +0000
commit37f4dfc2597e98c7aa4922c1b32b2337c18a2ca6 (patch)
treede78aa8912cd8dcf90c9cb76bfa8db452c0f9270 /firmware/target/arm/tms320dm320
parent3aced71e541d66b3f7051294ea58a93ec5a22d3f (diff)
downloadrockbox-37f4dfc2597e98c7aa4922c1b32b2337c18a2ca6.tar.gz
rockbox-37f4dfc2597e98c7aa4922c1b32b2337c18a2ca6.zip
TMS320DM320: Prevent lockup in udelay() when this function is called with interrupts disabled.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31392 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320')
-rw-r--r--firmware/target/arm/tms320dm320/system-dm320.c19
1 files changed, 17 insertions, 2 deletions
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c
index 5d7872f2bc..741516a950 100644
--- a/firmware/target/arm/tms320dm320/system-dm320.c
+++ b/firmware/target/arm/tms320dm320/system-dm320.c
@@ -412,6 +412,9 @@ void set_cpu_frequency(long frequency)
}
#endif
+/*
+ * Waits for specified amount of microseconds
+ */
void udelay(int usec) {
unsigned short count = IO_TIMER1_TMCNT;
unsigned short stop;
@@ -432,16 +435,28 @@ void udelay(int usec) {
stop -= tmp;
}
+ /*
+ * Status in IO_INTC_IRQ0 is changed even when interrupts are
+ * masked. If IRQ_TIMER1 bit in IO_INTC_IRQ0 is set to 0, then
+ * there is pending current_tick update.
+ *
+ * Relaying solely on current_tick value when interrupts are disabled
+ * can lead to lockup.
+ * Interrupt status bit check below is used to prevent this lockup.
+ */
+
if (stop < count)
{
/* udelay will end after counter reset (tick) */
while ((IO_TIMER1_TMCNT < stop) ||
- (current_tick == prev_tick)); /* ensure new tick */
+ ((current_tick == prev_tick) /* ensure new tick */ &&
+ (IO_INTC_IRQ0 & IRQ_TIMER1))); /* prevent lock */
}
else
{
/* udelay will end before counter reset (tick) */
- while ((IO_TIMER1_TMCNT < stop) && (current_tick == prev_tick));
+ while ((IO_TIMER1_TMCNT < stop) &&
+ ((current_tick == prev_tick) && (IO_INTC_IRQ0 & IRQ_TIMER1)));
}
}