path: root/firmware/target/arm
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authorSolomon Peachy <>2020-04-04 16:17:57 -0400
committerSolomon Peachy <>2020-04-04 23:07:04 +0200
commit5bd86eb4b4ce1b98a5f8b369d218fd1de41b4822 (patch)
tree986ae5fd5227ff977e6f50bd48edc8b3481641c2 /firmware/target/arm
parent00c0d2012f2e8d977bad5487ab6f3b8ca46c8572 (diff)
pp502x: Don't fill the cache starting from address 0x0
The pp502x cache init code tries to flush the cache by reading a block of DRAM. Change the starting point from 0x0 to 0x1000 so the compiler doesn't helpfully insert an undefined instruction to deliberately crash the target. (This behavior is intentional on the part of GCC, and was triggered by using -Os with my experimental 4.9.4 toolchain) Change-Id: I2d2719615a1164a035f3dac8a56dd3737bbab1d5
Diffstat (limited to 'firmware/target/arm')
1 files changed, 5 insertions, 1 deletions
diff --git a/firmware/target/arm/pp/system-pp502x.c b/firmware/target/arm/pp/system-pp502x.c
index 102cfd8fea..ad0577c38f 100644
--- a/firmware/target/arm/pp/system-pp502x.c
+++ b/firmware/target/arm/pp/system-pp502x.c
@@ -277,8 +277,12 @@ static void init_cache(void)
/* Ensure all cache lines are valid for the next flush. Since this
* can run from cached RAM, rewriting of cache status words may not
* be safe and the cache is filled instead by reading. */
+ /* Note: Don't start at 0x0, as the compiler thinks it's a
+ null pointer dereference and will helpfully blow up the code. */
register volatile char *p;
- for (p = (volatile char *)0; p < (volatile char *)0x2000; p += 0x10)
+ for (p = (volatile char *)0x1000; p < (volatile char *)0x3000; p += 0x10)