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authorSolomon Peachy <pizza@shaftnet.org>2020-10-02 07:02:51 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-10-02 09:50:38 -0400
commit90af40e90c13eb5d6c9d6fa05bc2d1ca64fcdd0c (patch)
tree8318f832bda0b3d3b11bdc18a5551a43e7109c43 /firmware/target/arm
parent9892e468d5c68f0d84ada26ea9737fae9dd41496 (diff)
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imx233: Hardware codec supports up to 192KHz. Make it so!
Change-Id: If08a1d244f28092a5d5332d666fb9afdc78f35a9
Diffstat (limited to 'firmware/target/arm')
-rw-r--r--firmware/target/arm/imx233/audioin-imx233.c5
-rw-r--r--firmware/target/arm/imx233/audioout-imx233.c5
2 files changed, 8 insertions, 2 deletions
diff --git a/firmware/target/arm/imx233/audioin-imx233.c b/firmware/target/arm/imx233/audioin-imx233.c
index e221ac07e9..b1bd8ec655 100644
--- a/firmware/target/arm/imx233/audioin-imx233.c
+++ b/firmware/target/arm/imx233/audioin-imx233.c
@@ -181,7 +181,7 @@ void imx233_audioin_enable_mic(bool enable)
void imx233_audioin_set_freq(int fsel)
{
- static struct
+ static const struct
{
int base_mult;
int src_hold;
@@ -201,6 +201,9 @@ void imx233_audioin_set_freq(int fsel)
HW_HAVE_64_([HW_FREQ_64] = { 0x2, 0x0, 0x17, 0xe00},)
HW_HAVE_88_([HW_FREQ_88] = { 0x2, 0x0, 0x11, 0x37 },)
HW_HAVE_96_([HW_FREQ_96] = { 0x2, 0x0, 0xf, 0x13ff },)
+// HW_HAVE_128_([HW_FREQ_128] = { 0x4, 0x0, 0x17, 0xe00 },)
+ HW_HAVE_176_([HW_FREQ_176] = { 0x4, 0x0, 0x11, 0x37 },)
+ HW_HAVE_192_([HW_FREQ_192] = { 0x4, 0x0, 0xf, 0x13ff },)
};
BF_WR_ALL(AUDIOIN_ADCSRR,
diff --git a/firmware/target/arm/imx233/audioout-imx233.c b/firmware/target/arm/imx233/audioout-imx233.c
index a33e3c8a2a..2d8527ed16 100644
--- a/firmware/target/arm/imx233/audioout-imx233.c
+++ b/firmware/target/arm/imx233/audioout-imx233.c
@@ -185,7 +185,7 @@ void imx233_audioout_set_hp_vol(int vol_l, int vol_r)
void imx233_audioout_set_freq(int fsel)
{
- static struct
+ static const struct
{
int base_mult;
int src_hold;
@@ -205,6 +205,9 @@ void imx233_audioout_set_freq(int fsel)
HW_HAVE_64_([HW_FREQ_64] = { 0x2, 0x0, 0x17, 0xe00},)
HW_HAVE_88_([HW_FREQ_88] = { 0x2, 0x0, 0x11, 0x37 },)
HW_HAVE_96_([HW_FREQ_96] = { 0x2, 0x0, 0xf, 0x13ff },)
+// HW_HAVE_128_([HW_FREQ_128] = { 0x4, 0x0, 0x17, 0xe00 },)
+ HW_HAVE_176_([HW_FREQ_176] = { 0x4, 0x0, 0x11, 0x37 },)
+ HW_HAVE_192_([HW_FREQ_192] = { 0x4, 0x0, 0xf, 0x13ff },)
};
BF_WR_ALL(AUDIOOUT_DACSRR,