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authorThomas Martitz <kugel@rockbox.org>2009-07-06 13:13:47 +0000
committerThomas Martitz <kugel@rockbox.org>2009-07-06 13:13:47 +0000
commitc292a8eb1f5c09f19565fdc41010ff70ada77228 (patch)
tree24023fb84eee6d1c19c5671252012f7538eae2b6 /firmware/target/arm
parenta306e90f217086228f30dad20d1495f7057f6ea4 (diff)
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Sansa AMS: Disable voltage scaling for now until we found a way to make it reliable for everyone, it's causing problems with storage for many people.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21687 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm')
-rw-r--r--firmware/target/arm/as3525/system-as3525.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c
index 3b24ac2f39..60be7ddac0 100644
--- a/firmware/target/arm/as3525/system-as3525.c
+++ b/firmware/target/arm/as3525/system-as3525.c
@@ -329,13 +329,14 @@ void set_cpu_frequency(long frequency)
{
if(frequency == CPUFREQ_MAX)
{
+#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
/* Increasing frequency so boost voltage before change */
ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20));
/* Wait for voltage to be at least 1.20v before making fclk > 200 MHz */
while(adc_read(ADC_CVDD) < 480) /* 480 * .0025 = 1.20V */
;
-
+#endif
asm volatile(
"mrc p15, 0, r0, c1, c0 \n"
@@ -358,10 +359,10 @@ void set_cpu_frequency(long frequency)
"bic r0, r0, #3<<30 \n" /* fastbus clocking */
"mcr p15, 0, r0, c1, c0 \n"
: : : "r0" );
-
+#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
/* Decreasing frequency so reduce voltage after change */
ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10));
-
+#endif
cpu_frequency = CPUFREQ_NORMAL;
}
}